EP0544355B1 - Digital phase lock loop - Google Patents

Description

Digital phase locked loops are known, for example, from US-A-5 050 195.

The invention relates to a digital phase locked loop (PLL), which adjusts to a rectangular input signal with a frequency f _E and which has a switch which is switched to square wave signals of different frequencies and which is followed by a main divider, which works with a divisor D, which forms the output signal of the phase locked loop, the changeover switch being actuated as a function of this output signal and the input signal.

A known phase-locked loop of this type, which is built into the Matsushita IC MN6163, has a changeover switch which switches between two input frequencies, one of which is obtained by dividing the other down. An exclusive-or comparison takes place between the signal to be adjusted and the output signal of the circuit, depending on which the switch is switched between the two input frequencies. It switches to the first frequency during the times when both signals have a low level or a high level at the same time and to the second frequency during the other times. The main disadvantage of this circuit is that the pulses of the output signal of the circuit are not adjusted symmetrically with their leading edge to the pulses of the input signal. In addition, the phase relationship between these two signals is subject to phase jitter. The phase relationship also depends on the pulse width of the signals, since there is a constant comparison between the two signals, depending on which switch is actuated. Because a phase comparison during the entire time takes place, the capture and hold range of the circuit is relatively large, which is undesirable for many purposes.

It is an object of the invention to provide a digital phase-locked loop of the type mentioned at the outset, which has a small capture and hold range.

• daß der Umschalter zwischen einem ersten Rechtecksignal mit der Frequenz f₁, einem zweiten Rechtecksignal mit der zweiten Frequenz f₂ und einem dritten Rechtecksignal mit der Frequenz f₃ umgeschaltet wird, wobei gilt: $${\text{f}}_{\text{1}}{\text{· 1/D = f}}_{\text{E}}{\text{sowie k · f}}_{\text{1}}{\text{= f}}_{\text{2}}{\text{+ (k-1) · <figure-callout id="3" label="f" filenames="imgf0001.png,imgf0002.png" state="{{state}}">f</figure-callout>}}_{\text{3}}\text{,}$$
  
• daß eine Umschaltlogik vorgesehen ist, welche den Umschalter in der Weise steuert, daß er im Zeitraum zwischen zwei Impulsen des Ausgangssignals auf das Signal mit der ersten Frequenz f₁ und daß er während eines Impulses des Ausgangssignals und eines ersten Zustands des Eingangssignals auf das Signal mit der zweiten Frequenz f₂ und während eines Impulses des Ausgangssignals und eines zweiten Zustands des Eingangssignals auf das Signal mit der dritten Frequenz f₃ geschaltet wird,
• und daß für ein Einrasten der Schaltung auf die Vorderflanken der Impulse des Eingangssignals f₂ > f₃ bzw. auf die Rückflanken f₂ < f₃ gilt.

This object is achieved in that

• that the switch is switched between a first square-wave signal with the frequency f ₁ , a second square-wave signal with the second frequency f ₂ and a third square-wave signal with the frequency f ₃ , where: $${\text{<figure-callout id="1" label="f" filenames="imgf0001.png" state="{{state}}">f</figure-callout>}}_{\text{1}}{\text{1 / D = f}}_{\text{E}}{\text{as well as k · <figure-callout id="1" label="f" filenames="imgf0001.png" state="{{state}}">f</figure-callout>}}_{\text{1}}{\text{= f}}_{\text{2nd}}{\text{+ (k-1) · f}}_{\text{3rd}}\text{,}$$
  
• that a changeover logic is provided which controls the changeover switch in such a way that it switches to the signal with the first frequency f ₁ in the period between two pulses of the output signal and that it switches to the signal during a pulse of the output signal and a first state of the input signal the second frequency f ₂ and during a pulse of the output signal and a second state of the input signal is switched to the signal with the third frequency f ₃ ,
• and that for a latching of the circuit on the leading edges of the pulses of the input signal f ₂ > f ₃ or on the trailing edges f ₂ <f ₃ applies.

The changeover switch of the digital phase locked loop is thus supplied with three square-wave signals with three different frequencies, the relationships between these frequencies specified above having to be fulfilled. Both the pulses of the input signal as well those of the output signal represent a digital signal that can basically only take two amplitude values. It is also immaterial whether the input signal and / or the output signal has a high level in the idle state and has pulses that have a low level, or whether the reverse applies. In the following, it is assumed for the explanation that both signals have a low level in their idle state and have pulses with a high level.

In any case, the second square-wave signal with the frequency f _{2 must have} a higher frequency than the third square-wave signal with the frequency f ₃ for the circuit to snap onto the leading edges of the pulses. The reverse applies if the reverse is to be snapped onto the trailing edges of the input signal.

A switchover logic is provided which switches the switchover between the three square-wave signals, its output signal being fed to the main divider.

During the time in which the input signal has a low level, the changeover switch is switched to the signal with the first frequency f ₁ by the changeover logic. During the pulses of the input signal of the circuit, which have a high level, the amplitude of the output signal of the circuit is also considered. If this has a low level, the second square-wave signal is switched at the second frequency. If, on the other hand, it has a high level, then the third square-wave signal with the third frequency is switched to. The relationship of the frequencies or the division ratio of the main divider to one another ensures that the output signal of the circuit arrangement or the pulses contained in it, with its leading edge, are timed to a predefinable point in time during the pulses of the input signal the circuit fall.

The choice of the frequencies f ₁ , f ₂ and f ₃ or the frequency relationships to one another can be used to determine the area to which the pulses of the input signal of the circuit should be locked. In the equation k · f ₁ = f ₂ + (k-1) · f ₃ this rest time can be set using the factor k. k is a natural number in the range from 1 to infinity. If k = 1 is selected, the trailing edge of the pulses of the input signal is locked; at k towards infinity on the trailing edge of these pulses. If it is desired to snap to the center of the pulses of the input signal, then k = 2 should be selected, as is provided according to an embodiment of the invention; the following then applies: 2f ₁ = f ₂ + f ₃ .

The frequencies of the signals or the pulses occurring in them can thus be selected so that the output signal of the main divider changes from low to high level just in the middle of a pulse of the input signal. If the circuit is not yet properly engaged and the leading edge of the pulses of the output signal of the circuit appears after the middle of the pulses of the input signal, the time during which the switch is switched to the second square-wave signal with the second frequency f ₂ is greater. This relatively higher-frequency signal therefore generates more pulses which are supplied to the divider D. The next output pulse of divider D therefore appears relatively earlier, so that the next leading edges of the output pulses appear earlier and adjust to the middle of the pulses of the input signal. Conversely, when the circuit is not engaged and when the leading edges of the pulses of the output signal appear, the time before the middle of the pulses of Input signal, the period in which pulses of the second square-wave signal are fed to the main divider is relatively shorter and the period in which pulses of the third square-wave signal f _{3 of} lower frequency are fed to the main divider is relatively longer. This, in turn, causes the leading edges of the divider's output signal to appear relatively later on the next pulse of the input signal because relatively fewer pulses were fed to it during the previous pulse. In this way, the edge then moves back a little at the next pulse, since the divider D delivers an output signal a little later. Here, too, the center of the pulses of the input signal snaps into place. This version applies in a corresponding manner to k ≠ 2, that is to say to a snap-in to a point which is not in the middle of the pulses of the input signal.

A small catch and hold area can also be achieved by symmetrically engaging the circuit; both are the same size.

Compared to the circuit known from the prior art, the digital phase-locked loop according to the invention also has the advantage that both the frequency condition, that is to say the desired frequency of the output signal of the circuit, and the phase condition, that is to say the phase position of, by the choice of the different frequencies Input and output signals can be set independently of one another in the desired manner. The frequency condition can be set by choosing the frequency f ₁ and the divisior D of the main divider. These must be designed such that the frequency f _{1 divided} by the divisor D results in the output frequency of the circuit or corresponds to the frequency of the input signal to which it is to be locked.

The frequencies f ₂ and f _{3 of} the second and third square-wave signals determine the phase condition, that is to say the relative position of the pulses of the output signal to the pulses of the input signal of the circuit.

For the circuit to be as simple as possible, it is advantageous to generate the first, second and third square-wave signals from one signal. For this purpose, according to an embodiment of the invention, dividers are provided, by means of which the three square-wave signals with the frequencies f ₁ , f ₂ and f _{3 are} obtained by dividing a generator square-wave signal with a frequency f ₀ .

Because of the free choice described above, on the one hand the frequency condition and on the other hand the phase condition, it is possible, as is provided according to a further embodiment, to let the divisors work with integer divisors. This simplifies the construction of the circuit and saves complicated dividers that work with non-integer Devisors.

Another embodiment of the invention provides that the frequency f ₂ is chosen twice as large as the frequency f ₁ and that the third square wave signal has a frequency f ₃ = 0, that is to say has a constant amplitude. With this choice of frequencies, the above-mentioned conditions for the three frequencies are met and there is the advantage that only a square-wave signal and a divider are required to generate the three signals. The circuit can, as is provided according to one embodiment, be designed so that a square-wave signal generator is provided, which supplies a signal with the second frequency f ₂ , which is fed to a divider with the divisor 2, the output signal of which includes the square-wave signal represents the first frequency f ₁ .

According to a further embodiment, it is provided that the phase-locked loop is provided in a television receiver for detecting the horizontal synchronizing pulses of a television signal that may be received in an output signal of a tuner of the television receiver. The above-described symmetrical latching of the circuit and the consequently small capture and hold area can be used particularly well in the detection of the horizontal synchronizing pulses of a television signal, since this small capture and hold area leads to an occurrence of interference being unlikely. The phase-locked loop can be used to detect whether the television receiver or the tuner of the television receiver receives a television signal or not. Depending on this knowledge, further circuits in the television receiver can be set accordingly. Especially for the application for the detection of the horizontal synchronizing pulses in a television signal, it is advantageous that the square-wave signal generator works with a frequency f ₀ = 843.75 MHz and that a division by D = 27 is carried out in the main divider. This results in a frequency for the output signal of the circuit which corresponds almost exactly to the frequency of the horizontal synchronizing signal in a television signal.

If the horizontal synchronizing pulses of a television signal are to be detected in a television receiver in the manner described, it is advantageous not to supply these pulses directly to the circuit, since they are usually superimposed by interference and so the circuit can not always function properly. To eliminate interference, it is therefore advantageous, as is provided in a further embodiment, that the output signal of the tuner is fed to an amplitude filter, by means of which the synchronizing pulses are separated which are fed to a downstream low-pass filter which acts as an integrator and whose output signal is compared in a comparator with a switching threshold, a monoflop being triggered when the switching threshold is exceeded, the output signal of which represents the input signal of the phase-locked loop. By selecting the time constant of the integrator or the switching threshold of the comparator, the sensitivity or insensitivity of the circuit and the time delay with which the monoflop delivers an output signal can be influenced when horizontal synchronizing pulses have been separated by the amplitude sieve. The choice of these two parameters also influences how many interference pulses reach the input of the phase-locked loop. The output signal of the monoflop is now a digital signal that can only assume two states and that can be further processed by the phase locked loop.

For the use of the phase-locked loop in a television receiver, it is further provided that the phase-locked loop is followed by an evaluation circuit in which a D flip-flop is provided, the D input of which is supplied with the input signal of the phase locked loop and the clock input of which is supplied with the output signal of the phase locked loop and the output signal of which is two Current mirror controls, the outputs of which are guided to a capacitor connected to a reference potential, one current mirror circuit charging the capacitor and the other discharging it, and that the voltage across the capacitor is fed to a comparator whose output signal indicates whether the phase-locked loop indicates a television signal with horizontal sync pulses has engaged or not.

The state of charge of the capacitor is a measure of whether the circuit has locked or not. The voltage across the capacitor can be evaluated by means of a comparator with hysteresis, which eliminates switching uncertainties, which in turn provides an output signal that can be easily further processed and that indicates the latched state of the circuit. The weighting can be adjusted with the level of the charge or discharge current of the two current mirrors. A charge-discharge current ratio of 4: 1 to 7: 1 is advantageous for use in a television receiver. If the current ratio is higher, noise is also recognized as a signal; if it is lower, a noisy signal is no longer recognized as such.

According to a further embodiment of the invention, it is provided that a horizontal phase locked loop is provided in the television receiver, to which the horizontal synchronization signal contained in a received television signal is fed, which has a phase comparator and a controllable oscillator, that the input of the controllable oscillator is switched to via a controllable switch Output of the phase comparator or an output of a DC voltage source is switchable, which supplies a voltage which causes the oscillator to oscillate at a predetermined horizontal frequency, and that the controllable switch is controlled in dependence on the output signal of the comparator so that the controllable oscillator when not locked Phase controller emits a signal with the target horizontal frequency.

The television receiver thus has a horizontal phase locked loop which locks onto the horizontal sync pulses and its output signal for further processing in the television receiver, in particular for the deflection circuit processed for display on a screen. In this case, the digital phase locked loop according to the invention serves to recognize whether a television signal is being received or not. If no television signal is received, the problem with the circuits known from the prior art arises that the horizontal phase locked loop delivers an arbitrary frequency, since it can no longer adjust itself to an input frequency. However, this in turn means that the display on the screen is no longer possible due to fluctuating horizontal frequencies. In particular, so-called on-screen display representations can no longer be made. The digital phase locked loop according to the invention can be used in the manner described above to detect whether a television signal is being received or not. This information, which can in particular be taken from the output signal of the value circuit described above, can now be used to switch the oscillator of the horizontal phase locked loop to its nominal frequency during those times in which the comparator of the evaluation circuit indicates that no television signal is being received. It is also possible to display it on the screen when no television signal is being received. For example, a display on the screen can also take place during a channel search. This representation can be given, for example, by fading in certain setting values of the television receiver.

• Fig. 1 eine erste Ausführungsform des digitalen Phasenregelkreises,
• Fig. 2 eine zweite Ausführungsform des digitalen Phasenregelkreises,
• Fig. 3 ein Impulsdiagramm des Phasenregelkreises gemäß Fig. 2,
• Fig. 4 den digitalen Phasenregelkreis mit vorgeschaltetem Amplitudensieb, Integrator, Komparator und Monoflop sowie nachgeschalteter Auswerteeinheit und
• Fig. 5 die Auswerteeinheit gemäß Fig. 4 sowie ein Blockschaltbild eines Horizontalphasenregelkreises eines sehempfängers.

Some exemplary embodiments of the invention are explained in more detail with reference to the drawing. Show it:

• 1 shows a first embodiment of the digital phase locked loop,
• 2 shows a second embodiment of the digital phase locked loop,
• 3 shows a pulse diagram of the phase locked loop according to FIG. 2,
• Fig. 4 shows the digital phase-locked loop with an upstream amplitude filter, integrator, comparator and monoflop and downstream evaluation unit and
• 5 shows the evaluation unit according to FIG. 4 as well as a block diagram of a horizontal phase locked loop of a vision receiver.

A first embodiment of the digital phase locked loop according to the invention shown in FIG. 1 has a changeover switch 1 which has three inputs. Switching positions a, b and c are provided for switching to the three inputs. In the phase locked loop shown in FIG. 1, the three square-wave signals fed to these inputs of the changeover switch 1 are obtained from a square-wave signal with the frequency f ₀ , which in turn can originate from a generator not shown in the FIG. The square-wave signal with the frequency f ₀ is divided in a first divider 2 by a divisor A, so that the divider 2 provides at its output a square-wave signal with the frequency f ₁ , which is supplied to the switch 1 at its switch contact a.

In a second divider 3, the signal with the frequency f _{0 is divided} by a divisor B, so that the divider 3 delivers at its output a second square wave signal with the frequency f ₂ , which is supplied to the switch contact b of the changeover switch 1.

For the generation of the third square-wave signal with the frequency f ₃ , the signal with the frequency f _{0 is divided} in a third divider 4 by a divisor C. The third square wave signal is supplied to the switch contact C of the changeover switch 1.

The switch 1, which delivers a signal U at its output, is followed by a main divider 5, which works with a divisor D. The output signal of the main divider 5 also represents the output signal of the phase locked loop, which is denoted by H _PLL in the figure.

A switchover logic 6 is also provided, which is supplied on the input side with the output signal of the phase locked loop H _PLL and on the other hand with the input signal to which the phase locked loop is to adjust. This input signal is designated H in the figure; it has a frequency f ₁ . The changeover logic 6 controls the changeover switch 1 as a function of these signals. The changeover logic 6 can of course be integrated in the changeover switch 1.

erfüllt sein. Die Frequenz f₁ des ersten Rechtecksignals muß also heruntergeteilt mit dem Divisor D gerade der Frequenz des Eingangssignals entsprechen, auf die die Schaltung einrasten soll. Die Summe der Frequenzen f₂ und f₃ muß dem doppelten Wert der Frequenz des Signals f₁ entsprechen. Dies ist erforderlich, um ein Einrasten der Schaltung zu gewährleisten. Für ein symmetrisches Einrasten ist k = 2 zu wählen.For the relationships of the frequencies f ₁ , f ₂ , f ₃ , or the divisors A, B and C and the divisor D, the conditions must be met $${\text{<figure-callout id="1" label="f" filenames="imgf0001.png" state="{{state}}">f</figure-callout>}}_{\text{1}}{\text{1 / D = f}}_{\text{E}}{\text{as well as k · <figure-callout id="1" label="f" filenames="imgf0001.png" state="{{state}}">f</figure-callout>}}_{\text{1}}{\text{= f}}_{\text{2nd}}{\text{+ (k-1) f}}_{\text{3rd}}$$

be fulfilled. The frequency f _{1 of} the first square-wave signal must therefore be divided down with the divisor D to correspond to the frequency of the input signal to which the circuit is to snap. The sum of the frequencies f ₂ and f ₃ must correspond to twice the value of the frequency of the signal f ₁ . This is required to snap the Ensure circuit. Select k = 2 for a symmetrical engagement.

To make the circuit structure as simple as possible, the dividers 2, 3, 4 and 5 should work with integer divisors. Taking into account the above-mentioned relationships between the frequencies or the divisors, the divisors 2, 3 and 4 can work with the following divisors, for example: table A B C. 2nd 1 00 4th 3rd 6 6 4th 12th 8th 5 20th 10th 6 30th 12th 7 40

The first line of this table shows a design in which divisor C has a design against infinity. Mathematically, this means nothing other than that the third square-wave signal with the frequency f _{3 has} a frequency = 0. The signal is therefore always at a constant level. The interpretation of the divisors according to the first line also shows that the divisor B = 1; the divider 3 can thus be completely omitted and the signal f _{0 can} simultaneously be designed as signal f ₂ .

Fig. 2 shows a second embodiment of the digital phase locked loop, in which the divisors according to the first Row of the table.

The second divider 3 according to the circuit in FIG. 1 can be omitted since the divisor B = 1. The signal with the frequency f ₀ can thus be used directly as a second square wave signal with the signal f ₂ . The frequency of the third signal f ₃ is 0, so that the contact c of the changeover switch 1 can be supplied with a signal of constant amplitude. In the illustration according to FIG. 2, this contact is connected to ground.

The circuit according to FIG. 2 has no functional disadvantages compared to the circuit according to FIG. 1, but two dividers are saved.

The mode of operation of the circuits both in accordance with FIG. 1 and in accordance with FIG. 2 is explained in more detail below with reference to a pulse diagram shown in FIG. 3, in which some signals are shown over time.

A first curve shown in FIG. 3 shows the input signal H. This input signal can assume two levels, namely low level, marked 0 in FIG. 3 and high level, marked 1 in FIG. The signal has a low level in its idle state. The signal is high during pulses contained in the signal. This signal H can be, in particular, a horizontal synchronizing signal of a television signal or a signal derived from this signal.

A second curve shown in FIG. 3 shows the output signal U of the changeover switch 1 of the circuit according to FIG. 2.

3 shows the output signal H _{PLL of} the circuit or the output signal of the divider 5 of the circuit according to FIG. 2.

The control logic 6 of the phase locked loop according to FIG. 2 controls the changeover switch 1 as a function of the output signal H _PLL and the input signal H. The illustration according to FIG. 3 shows that the changeover switch to its position a, ie to the signal with the frequency f ₁ during of those times in which the input signal H has a low level. During these periods, the level of the output signal H _{PLL of} the circuit for the switch position of the switch 6 is irrelevant.

In contrast, during those times when the input signal H is high, ie when a pulse occurs in this signal, the instantaneous level of the output signal H _{PLL is also} taken into account. If this signal has a low level during a pulse of the signal H, the changeover switch is switched to its position b, that is to say the signal with the frequency f ₂ . If, on the other hand, the signal H _{PLL is} high during a pulse of the signal H, the changeover switch 1 is switched to its contact c, that is to say the signal with the frequency f ₃ .

The mode of operation of the circuit will be explained in more detail below with the aid of the illustration according to FIG. 3 shows the locked state of the circuit, that is to say the state in which the output signal H _PLL is synchronized with its leading edges exactly to the center of the pulses of the signal H.

In this synchronized or adjusted state of the circuit, the divider 5 according to FIG. 2 as shown in FIG. 3 during the period from Time t ₂ , that is, the time at which the signal at the output of divider 5 changes from low to high level until time t ₃ , at which the trailing edge of the IM pulse of the input signal appears, no pulses are supplied. From t ₃ , the pulses divided by divider 2 arrive at the input of divider 5. At time t ₄ , the input signal supplied to divider 5 again generates a pulse at the output of divider 5 by dividing by divisor D. During the subsequent time period t ₄ to t ₅ , that is, to the leading edge of the next pulse of the input signal H, the changeover switch 6 receives the signal f _{1 divided} down by the divider 2 and subsequently until the time t ₆ , at which the output signal of the divider 5 changes back to high level, the undivided signal f ₂ = f _{0 is} supplied. The counter has counted once, for example, in the period t ₂ to t ₆ . During the period t ₂ to t ₃ , the divider 5 was supplied with the signal with the frequency f ₃ , which in the embodiment according to FIG. 2 has a frequency f ₃ = 0, that is to say has a constant level. During the time period t ₃ to t ₅ , the divider 5 was supplied with the first signal with the frequency f ₁ . During the time period t ₅ to t ₆ , the signal with the relatively higher frequency f _{2 was} fed to the divider. The values of the frequencies f ₁ , f ₂ and f ₃ and the divisor D of the divider 5 according to FIG. 2 are chosen so that the divider receives just enough pulses in the time period t2 to t6 that an output signal at times t ₂ and t ₆ , that is, in the middle of the time of the pulses of the signal H changes from low to high level. This sequence continues in the synchronized state of the circuit between two pulses of the signal H.

In the non-synchronized state of the circuit, the transition from low level to high level takes place at time t ₂ Signal H _PLL does not take place in the middle of the pulse of signal H. Nevertheless, from time t ₂ to time t ₃ , at which the pulse of the signal has ended, no pulse is supplied to divider 5d. Between times t ₃ and t ₅ , the divider receives the same number of pulses of the signal with frequency f ₁ as in the synchronized state. During the period t ₅ to t ₆ , however, the divider receives a number of pulses which differs from the synchronized state. The number of pulses depends on the flank position. The output signal of divider 5 will change from low to high level again at time t ₆ , this time being chosen in accordance with the frequency relationships of f ₁ or the pulses supplied to divider 5 in the same way as in the synchronized state so that the Time t ₆ the temporal center of a pulse of the signal H falls. The output signal of the divider 5 or the overall circuit is thus synchronized again to the temporal center of the pulses of the signal H. This synchronization can also take several periods.

Even if the transition from the low to the high level of the signal H _PLL takes place in the unsynchronized state of the circuit at a time in which no pulse is contained in the signal H, the circuit regulates itself slowly. This is because, at time t _3, regardless of the state of the H _PLL signal, in this case the signal f _{1 is switched} to the input of the divisor 5 according to FIG. 2. The dividing process of the divider 5 then continues in the manner described above, so that at time t ₆ , the adjustment process possibly extending over several periods of the signal H _PLL , a change in the signal from low to high at its output Level takes place, provided the signal H is high at this time.

3, as explained, the frequency f ₃ = 0 was selected. This means a relatively simple design of the circuit, corresponding to the illustration according to FIG. 1. The pulse diagram according to FIG. 3 can in principle also be read for a circuit according to FIG. 1, in which the frequency f _{3 is} not equal to 0, but for one Detection on the leading edges of the pulses of signal H should have a lower frequency than the signal with frequency f ₂ . In this case, pulses would also be counted during the time periods t ₂ to t ₃ or t ₆ to t ₇ , but it would be a smaller number of pulses during this time period than would arrive at the divider 5 during the remaining time periods. The selection of the frequencies f ₁ , f ₂ , f ₃ and the divisor D of the divider 5 of the circuit according to FIG. 1 would have to be designed in such a way that the output signal of the divider 5 in the synchronized state of the circuit just at times t ₂ or t _{6 changes} from low to high level. The phase position of H and H _PLL in the adjusted state depends on the choice of the frequencies f ₁ , f ₂ , f ₃ and the divisor D. If they are chosen so that t ₂ or t _{6 are} in the middle of the sync pulse, the control range is symmetrical with respect to the rest position. Even with this configuration of a circuit, for example according to FIG. 1, synchronization to the pulses of the signal H takes place in the non-synchronized state of the circuit. If, for example, the transition from low to high level in signal H _PLL occurs at time t ₂ before the middle of the pulse of signal H, time period t ₂ to t ₃ becomes longer and time period t ₅ to t ₆ increases. However, since significantly fewer pulses per time (relatively low-frequency signals) reach counter 5 (FIG. 2) during the time period t ₂ to t ₃ than during the time period t ₅ to t ₆ (relatively high-frequency signal), the time period t ₂ up to t ₆ longer than in the synchronized state, because the counter takes longer to count through. The edge at time t ₆ thus shifts backwards in time, so that the circuit slowly synchronizes. The same applies in the reverse manner to a flank of the signal H _{PLL which is} shifted backwards in time with respect to the pulse H.

For both circuit variants, the same number of pulses is always counted as a result of the switching on of the signal of frequency f ₁ to divider 5 regardless of the state of the signal H _PLL during times t ₃ to t ₅ , that is to say none during this time period Readjustment takes place. Readjustment only takes place during the time periods t ₁ to t ₃ or t ₅ to t ₇ .

FIG. 4 shows a block diagram of some circuit elements of a television receiver, which is otherwise not shown in FIG. The digital phase locked loop described above is indicated here as block 11. The signal H supplied to the block 11, that is to say the phase-locked loop, on the input side is obtained from a horizontal synchronizing signal of a television signal. For this purpose, a tuner 12 is provided, which is followed by an amplitude filter 13 which separates horizontal synchronizing pulses contained in the television signal. A low-pass filter connected downstream of the amplitude filter 13 acts as an integrator. Its output signal is fed to a further amplitude filter or a comparator, which then delivers an output signal when the signal supplied by the low-pass filter 14 exceeds a certain value. A monoflop 16 is then triggered, which delivers a pulse. The output signal of the monoflop 16 represents the signal H, which is fed to the digital phase locked loop 11, which is the phase locked loop according to FIG. 1 or FIG. 2.

An evaluation unit 17 is connected downstream of the phase-locked loop 11, to which both the output signal H _{PLL of} the phase-locked loop and the output signal H of the monoflop 16 are fed. The evaluation unit 17 in turn supplies an output signal H _A which indicates whether the digital phase locked loop 11 has locked in or not.

The upstream connection of the circuit elements 13 to 16 has the advantage that any interference that may be superimposed on the television signal supplied by the tuner 12 and thus also on the horizontal sync pulses contained therein, is largely filtered out. For example, the monoflop 16 delivers clear pulses with superimposed noise, which are overlaid by significantly fewer interference pulses.

FIG. 5 shows the evaluation unit 17 according to FIG. 4 in more detail. 5 also shows one

Horizontal phase locked loop, as can be provided in a television receiver, not otherwise shown.

On the input side, the evaluation unit has a D flip-flop 21, the clock input of which is supplied with the output signal of the digital phase locked loop. The input signal of the phase locked loop is fed to the D input of the flip-flop 21. The flip-flop 21 therefore always takes over the current value of the input signal of the phase locked loop with the positive edge of the signal H _PLL , that is to say the output signal. If the phase-locked loop is locked, this input signal is always high at these times. If the phase-locked loop is not locked, the signal has a low level at these times. The output signal of the D flip-flop 21 thus has a high level in the locked state of the circuit and a low level in the non-locked state.

This signal is fed to a first current mirror circuit 22 with a transistor 23 and a second current mirror circuit 24 with a transistor 25. During those times in which the output signal of the D flip-flop 21 is high, the transistor 23 is turned on and the first current mirror circuit 22 supplies a current with which a capacitance 26 connected to ground is charged.

During those times when the output signal of the D flip-flop 21 is low, the transistor 25 is turned on and the second current mirror circuit 24 discharges the capacitance 26. The voltage appearing across the capacitance 26 is evaluated by means of a comparator 27 with hysteresis, which delivers a high signal when the voltage exceeds a certain value and which delivers a low signal when the voltage falls below this value.

The weighting can be adjusted with the level of the charge or discharge current, that is to say the currents of the two current mirror circuits 22 and 24. A charge-discharge current ratio of 4: 1 to 7: 1 was found experimentally. If the current ratio is higher, noise is also recognized as a signal; if it is lower, a noisy signal is no longer reliably recognized as a signal.

The output signal H _{A of} the comparator 27 thus indicates in a time-integrated form whether the phase-locked loop 11 has latched in accordance with FIG. 4 or not.

This information can now be used in a television receiver to correspondingly control a horizontal phase locked loop provided in this. This horizontal phase locked loop, its output signal For example, is used to control the horizontal deflection of a picture tube to display the picture, has the property that it delivers almost any output signal when there is no input signal. This in turn means that display on the screen is no longer possible.

The output signal H _{A of} the comparator 27 is now used to switch the oscillator of the horizontal phase locked loop to its desired value and thus to allow a screen display, even if no signal is received.

The horizontal phase locked loop is indicated in FIG. 5 by means of a phase comparator 31, a filter 32 connected downstream of it and a controllable oscillator 33. In a known manner, this phase-locked loop is intended to lock onto the horizontal synchronizing pulses which are contained in a television signal. For this purpose, the oscillator 33 is controlled on the input side such that it delivers a signal at the desired frequency at its output. This signal is designated H ' _SYNC in FIG. 5.

If no television signal is received, this control signal for the oscillator 33 can assume almost any and, in particular, also fluctuating values, so that the signal H ' _{SYNC also takes on} fluctuating values and a screen display is no longer possible.

Exactly in this case, in which no television signal is received, however, the digital phase-locked loop according to the invention is not locked and the comparator 27 supplies an output signal H _A which has a low level. This signal H _A is now used to supply a diode 43 connected to the output of the comparator 27 on the cathode side switch. The diode 43 is connected on the anode side to a switch 44 which it controls. As an alternative, the switch 44 can be used to switch the output of the phase comparator 33 or an output of a DC voltage source 45 to the input of the filter 32.

If a received television signal or the horizontal synchronizing pulses contained in it are recognized by the phase locked loop according to the invention, the output signal of the comparator 27 has a high level. The diode 43 is then switched on and the switch 44 is switched to the output of the phase comparator 31 of the H _PLL . The horizontal phase locked loop, which is formed from the elements 31, 32 and 33, then operates in a normal manner, ie it adjusts itself to the horizontal synchronizing signals contained in the television signal.

If, on the other hand, no television signal is detected by the phase locked loop according to the invention, the output signal H _{A is} low, so that the diode 43 is blocked. The switch 44 is then connected to the output of the DC voltage generator 45. The DC voltage supplied by this arrives at the input of the controllable oscillator 33. The DC voltage supplied by the generator 45 is selected so that the controllable oscillator 33 supplies a signal of a desired horizontal frequency, that is to say that frequency which is contained in a television signal Horizontal synchronizing signal normally has. In this way, the control of the deflection circuit of the television set etc. is possible, so that although no television signal is received, displays on the screen are still possible, which can be, for example, so-called on-screen displays, that is to say representations of certain ones Setting parameters of the television set.

Claims (11)

1. A digital phase-locked loop (PLL) which responds to a square-wave input signal of a frequency f_E and comprises a change-over switch (1) which is switched in response to square-wave signals of different frequencies and precedes a main divider (5) operating with a divisor D and constituting the output signal of the phase-locked loop, the change-over switch (I) being activated in dependence upon said output signal and the input signal, characterized in that

   - the change-over switch is switched between a first square-wave signal of the frequency f₁, a second square-wave signal of the second frequency f₂ and a third square-wave signal of the frequency f₃, in which: $${\text{f}}_{\text{1}}{\text{. 1/D = f}}_{\text{E}}{\text{and k. f}}_{\text{1}}{\text{= f}}_{\text{2}}{\text{+ (k-1) . f}}_{\text{3}}\text{,}$$

   

   with k being a natural number between 1 and infinity;

   - a switching logic (6) is provided which controls the change-over switch (1) in such a way that it is switched to the signal of the first frequency f₁ in the period between two pulses of the output signal, and to the signal of the second frequency f₂ during a pulse of the output signal and a first state of the input signal, and to the signal of the third frequency f₃ during a pulse of the output signal and a second state of the input signal,

   - and in that f₂ > f₃ when the circuit locks in on the leading edges of the pulses of the input signal and f₂ < f₃ when the circuit locks in on the trailing edges.
2. A phase-locked loop as claimed in Claim 1, characterized in that 2 . f₁ = f₂ + f₃.
3. A phase-locked loop as claimed in Claim 1 or 2, characterized in that dividers (2, 3, 4) are provided by means of which the three square-wave signals of the frequencies f₁, f₂ and f₃ are gained by dividing a generator square-wave signal of a frequency f₀.
4. A phase-locked loop as claimed in Claim 3, characterized in that the dividers (2, 3, 4) operate with integral divisors.
5. A phase-locked loop as claimed in Claim 2, characterized in that f₂ = 2f₁ and f₃ = 0.
6. A phase-locked loop as claimed in Claim 5, characterized in that a square-wave signal generator is provided which supplies a signal of the second frequency f₂ which is applied to a divider operating with the divisor 2 whose output signal represents the square-wave signal of the first frequency f₁.
7. A phase-locked loop as claimed in any one of Claims 1 to 6, characterized in that the phase-locked loop is arranged in a television receiver for detecting the horizontal sync pulses of a possibly received television signal in an output signal of a tuner of the television receiver.
8. A phase-locked loop as claimed in Claims 5, 6 and 7, characterized in that the square-wave signal generator operates at a frequency f₀ of 843.75 MHz and in that the main divider performs a division by D = 27.
9. A television receiver including a phase-locked loop as claimed in Claim 7 or 8, characterized in that the output signal of the tuner is applied to an amplitude separator (13) by means of which the sync pulses are separated and applied to a subsequently arranged low-pass filter (14) operating as an integrator whose output signal is compared in a comparator (15) with a switching threshold, a monoflop (16), whose output signal represents the input signal of the phase-locked loop, being triggered when the switching threshold is exceeded.
10. A television receiver including a phase-locked loop as claimed in Claim 7, 8 or 9, characterized in that the phase-locked loop precedes an evaluation circuit (17) which includes a D flip-flop (21) whose D input receives the input signal of the phase-locked loop and whose clock input receives the output signal of the phase-locked loop and whose output signal controls two current mirrors (22, 24) whose output currents are applied to a capacitor (26) connected to a reference potential, one current mirror circuit charging the capacitor and the other discharging the capacitor, and in that the voltage across the capacitor (26) is applied to a comparator (27) whose output signal indicates whether the phase-locked loop has locked in or not locked in on a television signal comprising horizontal sync pulses.
11. A television receiver including a phase-locked loop as claimed in Claim 10, characterized in that the television receiver includes a horizontal phase-locked loop (31, 32, 33) which receives the horizontal synchronizing signal in a received television signal, said loop comprising a phase comparator (31) and a controllable oscillator (33), in that the input of the controllable oscillator (33) is connectable to the output of the phase comparator (31) or to an output of a DC source via a controllable switch (44), said DC source supplying a voltage causing the oscillator (33) to oscillate at a predeterminable nominal horizontal frequency, and in that the controllable switch (44) is controlled in dependence upon the output signal (H_A) of the comparator (27) in such a way that the controllable oscillator (31) supplies a signal at the nominal horizontal frequency when the phase-locked loop has not locked in.

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