DE10007414B4 - Process for the through-plating of a substrate for power semiconductor modules by solder and substrate produced by the method - Google Patents
Process for the through-plating of a substrate for power semiconductor modules by solder and substrate produced by the method Download PDFInfo
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- DE10007414B4 DE10007414B4 DE10007414A DE10007414A DE10007414B4 DE 10007414 B4 DE10007414 B4 DE 10007414B4 DE 10007414 A DE10007414 A DE 10007414A DE 10007414 A DE10007414 A DE 10007414A DE 10007414 B4 DE10007414 B4 DE 10007414B4
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- hole
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- plate
- metal
- solder
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000007747 plating Methods 0.000 title 1
- 239000000919 ceramic Substances 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229910052802 copper Inorganic materials 0.000 claims description 39
- 239000010949 copper Substances 0.000 claims description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 35
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 150000001879 copper Chemical class 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Verfahren
zur Durchkontaktierung eines Substrats (1) für Leistungshalbleitermodule,
das zwei Platten (3o, 3u) aus Metall und eine schichtweise zwischen den
Metallplatten aufgenommene Platte (2) aus Keramik mit einem Durchgangsloch
(2a) aufweist,
mit den Schritten:
– Einbringen eines Durchgangsloch
(4) in eine der Metallplatten (3o) in Ausrichtung mit dem Durchgangsloch
(2a) der Keramikplatte (2),
– wobei das Durchgangloch (4)
durch Ätzen
der Metallplatte (3o) gebildet wird,
– Aufbringen eines Pastenlots
(9) auf eine Seite des Substrats (1) und
– Durchführen einer Ofenfahrt, so dass
das Pastenlot (9) in die Durchgangslöcher (2a, 4) hineinfließt und die
beiden Metallplatten (3o, 3u) durch das Lot (9) dauerhaft miteinander
kontaktiert werden.A method of through-contacting a substrate (1) for power semiconductor modules comprising two metal plates (3o, 3u) and a ceramic plate (2) sandwiched between the metal plates and having a through-hole (2a),
with the steps:
Inserting a through hole (4) into one of the metal plates (3o) in alignment with the through hole (2a) of the ceramic plate (2),
- wherein the through hole (4) is formed by etching the metal plate (3o),
- Applying a paste solder (9) on one side of the substrate (1) and
- Carrying out a furnace ride, so that the paste solder (9) flows into the through holes (2 a, 4) and the two metal plates (3 o, 3 u) are permanently contacted by the solder (9).
Description
Die Erfindung betrifft ein Verfahren zur Durchkontaktierung eines Substrats für Leistungshalbleitermodule nach Patentanspruch 1 und ein nach dem Verfahren hergestelltes Substrat für Leistungshalbleitermodule nach Patentanspruch 4.The The invention relates to a method for through-contacting a substrate for power semiconductor modules according to claim 1 and a substrate produced by the process for power semiconductor modules according to claim 4.
Leistungshalbleiter finden in den letzten Jahren in breitem Maße Anwendung in der Automobilelektronik, dem Energiemanagement und zunehmend auch in der industriellen Antriebs- und Automatisierungstechnik. In der Regel sind diese Leistungshalbleiter zu Modulen zusammengefaßt, die auf kundenspezifische Anforderungen abgestimmt sind.Power semiconductor have been widely used in automotive electronics in recent years, energy management and increasingly also in industrial drive and automation technology. As a rule, these are power semiconductors grouped into modules, which are tailored to customer-specific requirements.
Bei
derartigen Leistungshalbleitermodulen sind einzelne elektronische
Bauteile im allgemeinen auf einem Substrat angebracht. Ein derartiges
Substrat ist üblicherweise
in Form eines Sandwiches ausgestaltet, wobei eine Platte aus Keramik
zwischen zwei äußeren Platten
aus Metall schichtweise aufgenommen ist. Diese Metallplatten bestehen
in der Regel aus Kupfer, da dieses Material sehr gute Eigenschaften
bezüglich
der elektrischen Leitfähigkeit
und der Wärmeleitfähigkeit
zeigt. Ein solches Substrat, das aus dem Sandwich Kupfer-Keramik-Kupfer
besteht, ist aus der
Zur Herstellung dieser DCB-Substrate werden die Kupferplatten stark oxidiert und auf die Keramikplatte gelegt. Das somit gebildete Sandwich Kupfer-Keramik-Kupfer wird anschließend während einer Ofenfahrt auf ca. 1000°C erhitzt, wobei ein dabei erzeugtes Eutektikum Kupferoxid-Aluminiumoxid die einzelnen Schichten untrennbar miteinander verbindet (bondet). Zum Löten der elektrischen Bauteile wird typisch in eine Kupfer platte eine Struktur geätzt, wobei die andere Kupferplatte für eine bessere Wärmeabfuhr auf eine Bodenplatte (Heat-Sink) gelötet wird.to Making these DCB substrates will strengthen the copper plates oxidized and placed on the ceramic plate. The sandwich thus formed Copper-ceramic-copper is then heated to approx. Heated to 1000 ° C, wherein a thereby produced eutectic copper oxide-alumina the individual Inseparable layers (bonds). To solder the electrical components is typically in a copper plate a structure etched, where the other copper plate for a better heat dissipation is soldered to a bottom plate (heat-sink).
Zudem kann auch ein beidseitiges Abführen von Potentialen von dem bekannten DCB-Substrat notwendig sein. In diesem Fall ist eine leitende Verbindung zwischen den beiden äußeren Kupferplatten erforderlich, die durch eine Durchkontaktierung erzielt wird.moreover can also be a two-sided discharge of Potentials from the known DCB substrate may be necessary. In this Case, a conductive connection is required between the two outer copper plates, which is achieved by a via.
Eine
solche Durchkontaktierung wird z.B. bei den bekannten DCB-Substraten
dadurch realisiert, dass in die Keramikplatte ein Durchgangsloch
eingebracht wird. Desweiteren wird in dieses Loch vor dem Bonden
des Sandwiches ein separates Teil manuell eingelegt. Zum Beispiel
wird hierfür
eine Kugel aus Kupfer verwendet. Das Positionieren dieser Kupferkugel
hat jedoch einerseits den Nachteil, dass das Durchgangsloch in der
Keramik ein hohes Maß an Genauigkeit
zur exakten Aufnahme der Kupferkugel aufweisen muß, was beispielsweise
durch ein aufwendiges Lasertrennverfahren erzielt werden kann. Desweiteren
stellt das separate Einlegen dieser Kupferkugel einen zusätzlichen
Arbeitsschritt und als auch einen Mehraufwand an Material dar, vergleiche dazu
noch die ältere
nachveröffentlichte
In
Abwandlung zu dem Einlegen eines separaten Teils ist es alternativ
möglich,
wie aus der
Entsprechend liegt der Erfindung die Aufgabe zugrunde, ein Verfahren und ein Substrat für Leistungshalbleitermodule mit einer Durchkontaktierung vorzusehen, die noch einfacher und kostengünstiger herzustellen ist.Corresponding the invention has the object, a method and a Substrate for Provide power semiconductor modules with a via, make the even easier and cheaper is.
Im erfindungsgemäßen Verfahren zur Durchkontaktierung eines Substrats für Leistungshalbleitermodule weist das Substrat zwei Platten aus Metall und eine schichtweise zwischen den Metallplatten aufgenommene Platte aus Keramik mit einem Durchgangsloch auf. Ein weiteres Durchgangsloch wird in eine der beiden Metallplatten in Ausrichtung mit dem Durchgangsloch der Keramikplatte hineingeätzt, anschließend wird ein Pastenlot auf eine Seite des Substrats aufgebracht und eine Ofenfahrt durchgeführt, so dass das Pastenlot in die Durchgangslöcher hineinfließt und die beiden Metallplatten durch das Lot dauerhaft miteinander kontaktiert werden.in the inventive method for through-contacting a substrate for power semiconductor modules For example, the substrate has two plates of metal and one layered between the metal plates recorded ceramic plate with a Through hole on. Another through hole is in one of both metal plates in alignment with the through hole of the ceramic plate etched, subsequently a paste solder is applied to one side of the substrate and carried out a kiln ride, so that the paste solder flows into the through holes and the both metal plates by the solder permanently contacted with each other become.
Das erfindungsgemäße Verfahren kommt vorteilhaft bei den eingangs erläuterten DCB-Substraten zum Einsatz. In die Oberfläche eines derartigen Substrats werden Strukturen geätzt, auf die in einem nachfolgenden Schritt weitere elektronische Bauteile gelötet werden. Erfindungsgemäß wird das Durchgangsloch in einer der Kupferplatten hineingeätzt, so dass gleichzeitig die o.g. Strukturen mitgeätzt werden können. Auf diese Weise lassen sich zwei Verfahrensschritte zu einem Schritt zusammenfassen, wodurch eine noch rationellere Fertigung erzielt wird.The method according to the invention is advantageously used in the DCB substrates explained in the introduction. Structures are etched into the surface of such a substrate, to which further electronic components are soldered in a subsequent step. According to the invention, the through-hole is etched into one of the copper plates, so that at the same time the above-mentioned structures can be etched. In this way, two ver To summarize driving steps to a single step, whereby an even more rational production is achieved.
Vor dem Verlöten der elektrischen Bauteile wird ein Pastenlot auf das Substrat aufgebracht. Dabei gelangt das Pastenlot auch auf die Stelle, an der das Durchgangsloch in die Kupferplatte hineingeätzt ist. Somit ist es möglich, dass das Pastenlot während einer Ofenfahrt, bei der gleichzeitig die e lektrischen Bauteile mit dem Substrat verlötet werden können, durch das Durchgangsloch der Kupferplatte in das Durchgangsloch der Keramikplatte hineinfließt, um auf die Fläche der anderen Kupferplatte zu gelangen und somit die beiden Kupferplatten miteinander zu kontaktieren.In front the soldering the electrical components, a paste solder is applied to the substrate. The paste solder also gets to the point where the through hole etched into the copper plate. Thus, it is possible that the paste solder during a Oven ride, at the same time the e lektrischen components with the Soldered substrate can be through the through hole of the copper plate in the through hole of the ceramic plate flows, around on the surface to get to the other copper plate and thus the two copper plates to contact each other.
In einer Weiterbildung der Erfindung hat das Durchgangsloch in der Kupferplatte einen kleineren Durchmesser als das Durchgangsloch in der Keramikplatte. Bezüglich des Zerfließens des Lots ist dabei ein genaues Toleranzmaß für das Durchgangsloch in der Keramikplatte unwesentlich. Folglich ist es möglich, die gewünschten Durchgangslöcher in die Keramikplatte mittels Stanzen einzubringen, bevor sie mit den oxidierten Kupferplatten zu dem Sandwich-Substrat gebondet wird.In a development of the invention has the through hole in the Copper plate has a smaller diameter than the through hole in the ceramic plate. In terms of of bleeding The solder is an exact measure of tolerance for the through hole in the Ceramic plate insignificant. Consequently, it is possible the desired Through holes in the ceramic plate by means of punching before they with the oxidized copper plates is bonded to the sandwich substrate.
Ein Stempel, beispielsweise in Form eines stumpfen Kegels, fährt nach dem Ätzen auf das Substrat nieder, wodurch ein innerer Rand des in der oberen Kupferplatte gebildeten Durchgangslochs in das Durchgangsloch der Keramikplatte hinein umgeformt wird. Dadurch wird vorteilhaft ein besseres Hineinfließen des Pastenlots in das Durchgangsloch der Keramikplatte in Richtung auf die andere Kupferplatte gewährleistet.One Stamp, for example in the form of a blunt cone, moves to the etching down to the substrate, creating an inner edge of the upper one Copper plate formed through hole in the through hole of Ceramic plate is transformed into it. This is advantageous better flow in of the paste solder in the through hole of the ceramic plate in the direction ensured on the other copper plate.
Ein Substrat für Leistungshalbleitermodule, mit zwei Platten aus Metall und einer schichtweise zwischen den Metallplatten aufgenommenen Platte aus Keramik, die ein Durchgangsloch aufweist und eine der beiden Metallplatten ein mit dem Durchgangsloch der Keramikplatte ausgerichtetes Durchgangsloch aufweist und die beiden Metallplatten durch ein Lot miteinander kontaktiert sind, wird mit dem erfindungsgemäßen Verfahren hergestellt.One Substrate for Power semiconductor modules, with two metal plates and one Layer by layer between the metal plates recorded plate Ceramic having a through hole and one of the two metal plates a through hole aligned with the through hole of the ceramic plate and the two metal plates by a solder together are contacted, is prepared by the method according to the invention.
Weitere vorteilhafte Ausgestaltungen und Weiterbildungen des Erfindungsgedankens sind in der nachfolgenden Beschreibung näher erläutert oder in abhängigen Patentansprüchen definiert.Further advantageous embodiments and developments of the inventive concept are explained in more detail in the following description or defined in the dependent claims.
Die Erfindung und vorteilhafte Einzelheiten werden nachfolgend unter Bezug auf die Zeichnungen in einer beispielsweisen Ausführungsform näher erläutert. Es zeigen:The Invention and advantageous details are below Referring to the drawings in an exemplary embodiment explained in more detail. It demonstrate:
In
der
In
der
Die
einzelnen Schichten des Substrats in der hier gezeigten Form weisen
unterschiedliche Dicken auf. Die Keramikplatte
Die
In
der
Die
Nachdem
das Durchgangsloch
In
der
Durch
das erfindungsgemäße Hineinätzen eines
Durchgangsloches
- 11
- Substratsubstratum
- 22
- Platte aus Keramikplate made of ceramic
- 2a2a
- DurchgangslochThrough Hole
- 3o3o
- Platte aus Metallplate made of metal
- 3u3u
- Platte aus Metallplate made of metal
- 44
- DurchgangslochThrough Hole
- d1 d 1
-
Durchmesser
des Durchgangslochs
4 Diameter of the through hole4 - d2 d 2
-
Durchmesser
des Durchgangslochs
2a Diameter of the through hole2a - rr
-
innerer
Rand des Durchgangslochs
4 inner edge of the through hole4 - 55
- Stempelstamp
- 66
-
Abschnitt
des Stempels
5 in Form eines stumpfen KegelsSection of the stamp5 in the form of a blunt cone - 77
- Lotsolder
- 88th
-
Fläche der
Metallplatte
3u Surface of the metal plate3u
Claims (8)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10007414A DE10007414B4 (en) | 2000-02-18 | 2000-02-18 | Process for the through-plating of a substrate for power semiconductor modules by solder and substrate produced by the method |
JP2001038608A JP2001284800A (en) | 2000-02-18 | 2001-02-15 | Substrate for output semiconductor module having through contact by solder and method for manufacturing substrate |
US09/789,341 US6715203B2 (en) | 2000-02-18 | 2001-02-20 | Substrate for power semiconductor modules with through-plating of solder and method for its production |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE10007414A DE10007414B4 (en) | 2000-02-18 | 2000-02-18 | Process for the through-plating of a substrate for power semiconductor modules by solder and substrate produced by the method |
Publications (2)
Publication Number | Publication Date |
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DE10007414A1 DE10007414A1 (en) | 2001-09-06 |
DE10007414B4 true DE10007414B4 (en) | 2006-07-06 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE10007414A Expired - Fee Related DE10007414B4 (en) | 2000-02-18 | 2000-02-18 | Process for the through-plating of a substrate for power semiconductor modules by solder and substrate produced by the method |
Country Status (3)
Country | Link |
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US (1) | US6715203B2 (en) |
JP (1) | JP2001284800A (en) |
DE (1) | DE10007414B4 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4003556B2 (en) * | 2002-06-27 | 2007-11-07 | 株式会社デンソー | Printed circuit board manufacturing method |
WO2004027866A2 (en) * | 2002-09-23 | 2004-04-01 | Johnson Controls Technology Company | Method for creating a link in an integrated metal substrate |
TWI451817B (en) * | 2011-05-26 | 2014-09-01 | 豐田自動織機股份有限公司 | Wiring board and method of manufacturing the wiring board |
US9397053B2 (en) | 2014-10-15 | 2016-07-19 | Hong Kong Applied Science and Technology Research Institute Company Limited | Molded device with anti-delamination structure providing multi-layered compression forces |
DE102019113308A1 (en) * | 2019-05-20 | 2020-11-26 | Rogers Germany Gmbh | A method for producing a metal-ceramic substrate and a metal-ceramic substrate produced by such a method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4103294A1 (en) * | 1991-02-04 | 1992-08-13 | Akyuerek Altan | Electrically conductive vias through ceramic substrates - are made by drawing metal from tracks into holes by capillary action using filling of holes by suitable powder |
DE4338706A1 (en) * | 1993-08-24 | 1995-05-04 | Schulz Harder Juergen | Multilayer substrate |
US5465898A (en) * | 1993-06-01 | 1995-11-14 | Schulz-Harder; Jurgen | Process for producing a metal-ceramic substrate |
DE19802347A1 (en) * | 1997-09-12 | 1999-04-08 | Lg Semicon Co Ltd | Semiconductor substrate with stackable semiconductor module |
DE19945794A1 (en) * | 1999-09-15 | 2001-04-12 | Curamik Electronics Gmbh | Process for manufacturing a printed circuit board and printed circuit board |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2963050D1 (en) * | 1978-02-17 | 1982-07-29 | Du Pont | Use of photosensitive stratum to create through-hole connections in circuit boards |
JPS5731198A (en) | 1981-04-27 | 1982-02-19 | Yazaki Corp | Copper-coated laminated board and method of producing same |
CH650373A5 (en) * | 1982-07-16 | 1985-07-15 | Jean Paul Strobel | PRINTED CIRCUIT AND METHOD FOR MANUFACTURING THE CIRCUIT. |
JPS6071579A (en) * | 1983-09-28 | 1985-04-23 | 株式会社日立製作所 | Method of bonding alumina and metal |
JPS61193496A (en) | 1985-02-21 | 1986-08-27 | シャープ株式会社 | Manufacture of flexible substrate |
JPS61197476A (en) * | 1985-02-26 | 1986-09-01 | 株式会社東芝 | Composite body and manufacture |
US4700473A (en) * | 1986-01-03 | 1987-10-20 | Motorola Inc. | Method of making an ultra high density pad array chip carrier |
DE3630429C2 (en) * | 1986-09-06 | 1994-07-21 | Metallgesellschaft Ag | Wall element for security structures |
US4918811A (en) * | 1986-09-26 | 1990-04-24 | General Electric Company | Multichip integrated circuit packaging method |
JPS63181400A (en) * | 1987-01-22 | 1988-07-26 | 松下電器産業株式会社 | Ceramic multilayer board |
US5241216A (en) * | 1989-12-21 | 1993-08-31 | General Electric Company | Ceramic-to-conducting-lead hermetic seal |
JP2827472B2 (en) | 1990-08-02 | 1998-11-25 | 松下電器産業株式会社 | Method of manufacturing through-hole printed wiring board |
US5401911A (en) * | 1992-04-03 | 1995-03-28 | International Business Machines Corporation | Via and pad structure for thermoplastic substrates and method and apparatus for forming the same |
US5769989A (en) * | 1995-09-19 | 1998-06-23 | International Business Machines Corporation | Method and system for reworkable direct chip attach (DCA) structure with thermal enhancement |
US5747358A (en) * | 1996-05-29 | 1998-05-05 | W. L. Gore & Associates, Inc. | Method of forming raised metallic contacts on electrical circuits |
JPH09326144A (en) | 1996-06-04 | 1997-12-16 | Matsushita Electric Ind Co Ltd | Magnetic recording/reproducing device and shifting offset measuring device for it |
US5785800A (en) * | 1996-06-21 | 1998-07-28 | International Business Machines Corporation | Apparatus for forming cavity structures using thermally decomposable surface layer |
SG76530A1 (en) * | 1997-03-03 | 2000-11-21 | Hitachi Chemical Co Ltd | Circuit boards using heat resistant resin for adhesive layers |
JP4334054B2 (en) * | 1999-03-26 | 2009-09-16 | 株式会社東芝 | Ceramic circuit board |
US6239382B1 (en) * | 1999-09-01 | 2001-05-29 | Agere Systems Guardian Corp. | Device and method of controlling the bowing of a soldered or adhesively bonded assembly |
US6562709B1 (en) * | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6562657B1 (en) * | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6587008B2 (en) * | 2000-09-22 | 2003-07-01 | Kyocera Corporation | Piezoelectric oscillator and a method for manufacturing the same |
-
2000
- 2000-02-18 DE DE10007414A patent/DE10007414B4/en not_active Expired - Fee Related
-
2001
- 2001-02-15 JP JP2001038608A patent/JP2001284800A/en active Pending
- 2001-02-20 US US09/789,341 patent/US6715203B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4103294A1 (en) * | 1991-02-04 | 1992-08-13 | Akyuerek Altan | Electrically conductive vias through ceramic substrates - are made by drawing metal from tracks into holes by capillary action using filling of holes by suitable powder |
US5465898A (en) * | 1993-06-01 | 1995-11-14 | Schulz-Harder; Jurgen | Process for producing a metal-ceramic substrate |
DE4338706A1 (en) * | 1993-08-24 | 1995-05-04 | Schulz Harder Juergen | Multilayer substrate |
DE19802347A1 (en) * | 1997-09-12 | 1999-04-08 | Lg Semicon Co Ltd | Semiconductor substrate with stackable semiconductor module |
DE19945794A1 (en) * | 1999-09-15 | 2001-04-12 | Curamik Electronics Gmbh | Process for manufacturing a printed circuit board and printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
US6715203B2 (en) | 2004-04-06 |
US20010022236A1 (en) | 2001-09-20 |
DE10007414A1 (en) | 2001-09-06 |
JP2001284800A (en) | 2001-10-12 |
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Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE |
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