DE102005027276B3 - Production process for a stack of at least two base materials comprising printed circuit boards photostructures the boards applies solder stacks and melts with lacquer separating the boards - Google Patents
Production process for a stack of at least two base materials comprising printed circuit boards photostructures the boards applies solder stacks and melts with lacquer separating the boards Download PDFInfo
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- DE102005027276B3 DE102005027276B3 DE102005027276A DE102005027276A DE102005027276B3 DE 102005027276 B3 DE102005027276 B3 DE 102005027276B3 DE 102005027276 A DE102005027276 A DE 102005027276A DE 102005027276 A DE102005027276 A DE 102005027276A DE 102005027276 B3 DE102005027276 B3 DE 102005027276B3
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- circuit boards
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- printed circuit
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- stacking
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10666—Plated through-hole for surface mounting on PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
Die Erfindung betrifft ein Verfahren zur Herstellung einer Stapelanordnung aus mindestens zwei Leiterplatten.The The invention relates to a method for producing a stack arrangement from at least two printed circuit boards.
Die Technologie der modularen Mikrosysteme ist in den letzten Jahren vorangeschritten, wobei diese modularen Mikrosysteme unter dem Begriff "Match-X" bekannt sind. Dabei sind Bausteine mit elektrischen, elektronischen, mechanischen, fluidischen und optischen Funktionen auf Leiterplatten aufgebracht, die zu standardisierten "Packages" zusammengefasst sind. Dabei sind entsprechend den Funktionen Schnittstellen definiert, die in einer Veröffentlichung des VDMA (Verband der Investitionsgüterindustrie) niedergeschrieben sind.The Technology of modular microsystems has been in recent years advanced, these modular microsystems are known by the term "Match-X". there are building blocks with electrical, electronic, mechanical, fluidic and optical functions applied to printed circuit boards, which are grouped into standardized "packages" are. Here are defined according to the functions interfaces, in a publication written down by the VDMA (Association of the Capital Goods Industry) are.
Dreidimensionale Packages bestehen aus übereinandergelöteten Leiterplatten aus Materialien wie FR4. Da bei werden gegenüberliegende Pads oder Kontakte auf den Leiterplatten oder anderen Substraten mit Lotpaste bedruckt und umgeschmolzen. Im nächsten Schritt werden die Leiterplatten übereinander gelegt, zueinander justiert und nochmals umgeschmolzen. So bildet sich eine Lotverbindung zwischen den beiden Leiterplatten aus. Dabei wurde schnell erkannt, dass die Leiterplatten einen gleichmäßigen Abstand haben müssen und ein gewisser Druck beim Stapeln ausgeübt werden muss, um Unebenheiten im Substrat zu verringern.Three-dimensional Packages consist of printed circuit boards soldered over each other from materials like FR4. Because there are opposite pads or contacts printed on the circuit boards or other substrates with solder paste and remelted. In the next Step the PCBs are placed one above the other, to each other adjusted and remelted again. This forms a solder joint between the two circuit boards. It was quickly recognized that the circuit boards must have a uniform distance and a certain pressure must be exerted when stacking to bumps to reduce in the substrate.
Bei
der Herstellung des dreidimensionalen Stapels oder des "Package" werden die mit Lotpaste bedruckten
und mit Bauteilen bestückten
sowie umgeschmolzenen Leiterplatten mit Hilfe eines Ausrichtwerkzeuges,
wie es beispielsweise in der
Um Verwölbungen in den Leiterplatten auszugleichen wird der gesamte Stapel mit Hilfe zweier Andrückplatten verspannt. Damit die Lotpaste zu einem Lotring zusammenfließen kann bzw. die einzelnen Pads zusam menfließen können, können zwischen die einzelnen Lagen Metallbleche mit einer bestimmten Dicke gelegt werden. Diese Bleche stellen Abstandshalter dar. Eine solche Lösung ist jedoch umständlich und sehr kostenaufwendig, da die Bleche vorher in einem getrennten Vorgang gestanzt werden müssen.Around warpage in the circuit boards to balance the entire stack with the help two pressure plates braced. So that the solder paste can flow together to form a solder ring or the individual pads can flow together, can between the individual Laying metal sheets with a certain thickness can be laid. These Sheets are spacers. However, such a solution is cumbersome and very expensive, since the sheets previously in a separate operation must be punched.
Um
den Abstand zwischen den einzelnen Leiterplatten, die auch als Rahmen
ausgebildet sein können,
zu realisieren, sind folgende Vorgehensweisen möglich:
das Verwenden von
Loten, die bei unterschiedlichen Temperaturen schmelzen und so die
höher schmelzenden
Lote den Abstand für
niederschmelzende Lote halten. Es kommt dabei jedoch zu intermetallischen
Phasen und bei den unterschiedlichen Ausdehnungskoeffizienten kommt
es zu Spannungen im Bauteil.
das Verwenden von dünnen Metallblechen,
die zwischen die Leiterplatten gelegt werden, wobei hier eine aufwendige
Montage und eine aufwendige Herstellung der Fläche nachteilig sind.
das
Verwenden von Loten mit z.B. kleinen Kupferkugeln, die höheren Schmelzpunkt
als das Lot haben. Die Kupferkugeln verhindern das Zusammendrücken des
Lotes beim Umschmelzen. Dabei sind die Kupferkugeln zufällig im
Lot verteilt, es kommt auch hier zu intermetallischen Phasen und
bei den unterschiedlichen Ausdehnungskoeffizienten kommt es zu Spannungen
im Bauteil. Bei Verwendung anderer Materialien statt Kupfer kann
es auch zu Spannungen im Bauteil kommen.
das Verwenden von
kleinen Bauteilen als Abstandshalter, wobei die Kosten für die Bauteile
relativ hoch sind, der Montageaufwand größer ist und die Bauteile selbst
relativ hoch sind.In order to realize the distance between the individual printed circuit boards, which can also be designed as frames, the following procedures are possible:
using solders that melt at different temperatures to keep the higher melting solders at a distance for low melting solders. However, it comes to intermetallic phases and in the different expansion coefficients there are tensions in the component.
the use of thin metal sheets, which are placed between the circuit boards, in which case a complex assembly and a complicated production of the surface are disadvantageous.
using solders with eg small copper balls that have higher melting point than the solder. The copper balls prevent the compression of the solder during remelting. The copper balls are randomly distributed in the solder, it also comes here to intermetallic phases and the different expansion coefficients there are tensions in the component. When using other materials instead of copper, it can also lead to stresses in the component.
the use of small components as spacers, wherein the cost of the components are relatively high, the assembly cost is greater and the components themselves are relatively high.
Aus der US 2002/0119597 A1 ist eine Anordnung von zwei übereinanderliegenden Wafern mit Leiterbahnen und Kontakten bekannt, zwischen denen Abstandshalter aus dielektrischem Material, wie Polymeren, Polyimiden oder laminierten Polymerschichten, bestehen.Out US 2002/0119597 A1 is an arrangement of two superimposed ones Wafers with interconnects and contacts known, between which spacers of dielectric material, such as polymers, polyimides or laminated Polymer layers exist.
Die
Der Erfindung liegt daher die Aufgabe zugrunde, eine Stapelanordnung aus mindestens zwei Leiterplatten mit Abstandshalter zu schaffen, der bzw. die einen immer gleichmäßigen Abstand zwischen den Lagen bzw. Leiterplatten des Stapels garantieren und somit das Lot nicht zerquetschen, wobei der bzw. die Abstandshalter kostengünstig sein sollen und die Stapelanordnung ohne mechanische Beanspruchungen mit den gewünschten Abständen versehen.The invention is therefore an object of the invention to provide a stacking arrangement of at least two printed circuit boards with spacers, which guarantee an always uniform distance between the layers or circuit boards of the stack and thus do not crush the solder, the or the spacer cost be should and provide the stack assembly without mechanical stress at the desired intervals.
Diese Aufgabe wird erfindungsgemäß durch die kennzeichnenden Merkmale des Hauptanspruchs in Verbindung mit den Merkmalen des Oberbegriffs gelöst.These The object is achieved by the characterizing features of the main claim in connection with the Characteristics of the preamble solved.
Durch die in den Unteransprüchen angegebenen Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen möglich.By in the subclaims specified measures Advantageous developments and improvements are possible.
Dadurch, dass die Abstandshalter aus einer Lackstruktur, d.h. aus einem Material bestehen, das im Wesentlichen den gleichen Ausdehnungskoeffizienten aufweist wie die Leiterplatten, und das bei der Herstellung von Leiterplatten allgemein verwendet wird, wobei die Lackstruktur beim Fotostrukturieren der Leiterplatte in der gewünschten Dicke aufgebracht wird, wird eine Stapelanordnung zur Verfügung gestellt, die kostengünstig herzustellen ist und die auch bei unterschiedlichen Temperaturen keine Schäden aufgrund von mechanischen Spannungen erleidet, so dass ihre Lebensdauer verlängert wird.Thereby, the spacers consist of a lacquer structure, i. from a material consist essentially of the same coefficient of expansion As the circuit boards, and that in the production of PCB is generally used, the paint structure in the Photo-structuring the printed circuit board is applied in the desired thickness, a stacking arrangement is provided which is inexpensive to manufacture is and does not cause damage even at different temperatures suffers from mechanical stress, so that its life is extended.
Vorteilhaft ist, den fotostrukturierbaren Lack, wie Abdeck- oder Lötstopplack, zu verwenden, da der oder die Abstandshalter vom Designer der Leitplatten in die Vorgaben der Fertigungsunterlagen integriert werden können. Es ist einfach, verschiedene Lackdicken, die an die Schablonendicke, d.h. an die Lotmenge auf den jeweiligen Kontakten der Leiterplatte und/oder an die elektrischen, fluidischen, mechanischen und/oder thermischen Verbindungen abgestimmt sein müssen, zu realisieren. Es wird somit eine gleichmäßige Dicke der Verbindungsschicht aus Lot erreicht.Advantageous is the photoimageable varnish, such as cover or solder mask, to use, as the one or more spacers from the designer of the baffles can be integrated into the specifications of the production documents. It is simple, different paint thicknesses that match the stencil thickness, i.e. to the amount of solder on the respective contacts of the circuit board and / or to the electrical, fluidic, mechanical and / or Thermal connections must be coordinated to realize. It will thus a uniform thickness reaches the connecting layer of solder.
Es können mehrere 3D-Packages getrennt hergestellt und zu einer Stapelanordnung übereinander gestapelt werden.It can made several 3D packages separately and stacked on top of each other be stacked.
Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung dargestellt und wird in der nachfolgenden Beschreibung näher erläutert.One embodiment The invention is illustrated in the drawing and will be described in the following Description closer explained.
Die einzige Figur zeigt ein Beispiel für den Ablauf des Aufbaus einer dreidimensionalen Stapelanordnung mit Abstandshalter.The only figure shows an example of the sequence of construction of a three-dimensional stacking arrangement with spacers.
In
der Figur ist eine Stapelanordnung in den ver schiedenen Herstellungsschritten
dargestellt. Die Stapelanordnung
Mit
der auf dem Boden
Im
vorliegenden Fall sind die Abstandshalter
In
der darunter liegenden Ansicht b) sind Bauteile
Im
weiteren Bild c) wurde eine Umschmelzung vorgenommen, d.h. die in
der Darstellung nach b) aufgebrachten Lotpastendepots verändern ihre Form
und werden zu Lotpunkten oder "Lotballs"
Anschließend werden
die dargestellten Leiterplatten
Die Verwendung von Lack als Abstandshalter bringt den Vorteil, dass bei der Herstellung und Fotostrukturierung der Leiterplatte der Abstandshalter gleich mitaufgebracht werden kann, so dass nach der Leiterplattenbestellung beim Aufbau nicht Wesentliches mehr zu beachten ist, da die Leiterplatte durch den Lack bereits alle wesentlichen Funktionen für einen Abstandshalter erhält. Weiterhin bringt der Lack als Abstandshalter den Vorteil, dass der Abstand auch noch nach dem Vereinzeln des Nutzenaufbaus vorhanden ist. So können beim Stapeln mehrerer modularer Packages und dem dann zweiten oder dritten Umschmelzen noch zuverlässige Verbindungen hergestellt werden.The use of paint as a spacer brings the advantage that in the production and Photo structuring of the circuit board of the spacer can be mitaufgebracht so that after the PCB order during construction is not essential to pay attention, since the circuit board already receives all the essential functions for a spacer through the paint. Furthermore, the paint brings as a spacer the advantage that the distance is still present after the separation of the benefit structure. Thus, when stacking several modular packages and then remelting second or third still reliable connections can be made.
Der in der Figur dargestellte Technologieablauf für den Aufbau eines dreidimensionalen Stapels mit Abstandshalter ist nur beispielhaft, es sind Änderungen im Ablauf durchaus möglich. So kann das zweimalige Umschmelzen wegfallen, wenn das Stapeln der Leiterplatten mit noch nasser, also nicht umgeschmolzener Lotpaste durchgeführt wird.Of the in the figure illustrated technology flow for the construction of a three-dimensional Stack with spacer is just an example, there are changes in the Expiration absolutely possible. Thus, the two-fold remelting can be omitted when stacking the Circuit boards with still wet, so not remelted solder paste carried out becomes.
Im beschriebenen Ausführungsbeispiel wurde Lack als Abstandshalter verwendet, eine weitere Möglichkeit ist, sich diese vom Leiterplattenhersteller aus Innenlagenmaterial, z.B. FR4, herstellen zu lassen, um es beim Stapeln zwischen die Leiterplatten zu platzieren. Dabei kann es "lose eingelegt werden", aber es ist auch möglich, diese aus Innenlagenmaterial bestehende Abstandshalter auf die Oberfläche zu laminieren und damit ständig vorhandene Abstandshalter zu schaffen. Dieser permanente Abstandshalter hat den Vorteil, dass er auch noch nach dem Vereinzeln vorhanden ist und so auch noch beim zweiten oder dritten Umschmelzen seine Funktion erfüllen kann. Dies ist z.B. erforderlich, wenn verschiedene Stapel miteinander verlötet werden sollen.in the described embodiment Lack was used as a spacer, another option is, this from the PCB manufacturer from inner layer material, e.g. FR4, to make it when stacking between the To place printed circuit boards. It can be "loosely inserted", but it is too possible, laminating these spacers made of innerliner material to the surface and constantly to provide existing spacers. This permanent spacer has the advantage that it is still present after separation is and so also in the second or third remelt his Function can fulfill. This is e.g. required if different stacks with each other soldered should be.
Die Verwendung des Innenlagenmaterials einer Leiterplatte als Abstandshalter bringt den Vorteil mit sich, dass der Abstandshalter dann genau denselben Ausdehnungskoeffizienten hat wie die Leiterplatte selbst.The Use of the inner layer material of a printed circuit board as a spacer brings the advantage that the spacer then exactly has the same coefficient of expansion as the circuit board itself.
Die Formen der Abstandshalter können sowohl bei der Verwendung von Lack als auch bei der Verwendung von folienartigem Material der Leiterplatte an die Strukturierung und das Design der für die Stapelanordnung verwendeten Leiterplatten angepasst werden, so dass eine sichere Abstandhaltung über die gesamte Ausdehnung der Leiterplatten gewährleistet werden kann.The Shapes of the spacers can both in the use of paint and in the use of foil-like material of the circuit board to structuring and the design of the for the Stacking arrangement used printed circuit boards are adapted so that a safe distance over the entire extent of the circuit boards can be guaranteed.
Claims (4)
Priority Applications (1)
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---|---|---|---|
DE102005027276A DE102005027276B3 (en) | 2005-06-08 | 2005-06-08 | Production process for a stack of at least two base materials comprising printed circuit boards photostructures the boards applies solder stacks and melts with lacquer separating the boards |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005027276A DE102005027276B3 (en) | 2005-06-08 | 2005-06-08 | Production process for a stack of at least two base materials comprising printed circuit boards photostructures the boards applies solder stacks and melts with lacquer separating the boards |
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Publication Number | Publication Date |
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DE102005027276B3 true DE102005027276B3 (en) | 2007-01-11 |
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DE102005027276A Expired - Fee Related DE102005027276B3 (en) | 2005-06-08 | 2005-06-08 | Production process for a stack of at least two base materials comprising printed circuit boards photostructures the boards applies solder stacks and melts with lacquer separating the boards |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011079278A1 (en) | 2010-07-15 | 2012-05-16 | Ifm Electronic Gmbh | Manufacturing method of electronic module based on three-dimensional technology, involves applying solder paste on solder surfaces of individual printed circuit boards (PCBs) and heating PCB in reflow oven for melting the solder paste |
CN109769345A (en) * | 2019-02-20 | 2019-05-17 | 信利光电股份有限公司 | A kind of High density of PCB lamination |
CN114025479A (en) * | 2021-12-03 | 2022-02-08 | 中国电子科技集团公司第二十六研究所 | Vertical interconnection structure between circuit boards, packaged device, microsystem and method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3316017A1 (en) * | 1983-05-03 | 1984-11-08 | Siegert GmbH, 8501 Cadolzburg | Method of making electrical connections in multisubstrate circuits, and multisubstrate circuits produced thereby |
US20020119597A1 (en) * | 2001-01-30 | 2002-08-29 | Stmicroelectronics S.R.L. | Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby |
-
2005
- 2005-06-08 DE DE102005027276A patent/DE102005027276B3/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3316017A1 (en) * | 1983-05-03 | 1984-11-08 | Siegert GmbH, 8501 Cadolzburg | Method of making electrical connections in multisubstrate circuits, and multisubstrate circuits produced thereby |
US20020119597A1 (en) * | 2001-01-30 | 2002-08-29 | Stmicroelectronics S.R.L. | Process for sealing and connecting parts of electromechanical, fluid and optical microsystems and device obtained thereby |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011079278A1 (en) | 2010-07-15 | 2012-05-16 | Ifm Electronic Gmbh | Manufacturing method of electronic module based on three-dimensional technology, involves applying solder paste on solder surfaces of individual printed circuit boards (PCBs) and heating PCB in reflow oven for melting the solder paste |
DE102011079278B4 (en) | 2010-07-15 | 2023-02-16 | Ifm Electronic Gmbh | 3D electronic module |
CN109769345A (en) * | 2019-02-20 | 2019-05-17 | 信利光电股份有限公司 | A kind of High density of PCB lamination |
CN114025479A (en) * | 2021-12-03 | 2022-02-08 | 中国电子科技集团公司第二十六研究所 | Vertical interconnection structure between circuit boards, packaged device, microsystem and method thereof |
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