DD290947A5 - CIRCUIT ARRANGEMENT FOR DETERMINING THE APPLICATION POINT OF AN ULTRASONIC RECEIPT SIGNAL - Google Patents

Abstract

The invention relates to a circuit arrangement for determining the starting point of an ultrasonic received signal. Field of application are ultrasound measuring devices according to the transit time method, in which only a minimal time error with respect to the applied sound wave period is permissible. The aim of the invention is to improve the precision of ultrasonic transit time measurements and to expand the field of application. The task is the precise determination of the start time of an ultrasonic received signal without any special requirements for the ultrasonic transducers and without special operation of the ultrasonic transmitter / receiver. According to the invention, the received signal is fed to two voltage comparators with different thresholds. A transit time and a period duration signal are formed, which act as gate signals for a transit time or period counter. The Laufzeitzaehlerausgaenge address a RAM memory, in the circumferentially the received signal is binarily stored. After the runtime measurement has been completed, the RAM memory contents are checked for the occurrence of periods of the received signal before the end of the delay measurement by backward clocking of the runtime error, and the runtime value is correspondingly corrected {ultrasonic received signal; Determination of point of use; Ultrasonic Meszeinrichtungen; Transit time method; more precise transit time measurements; Extension field of application; voltage comparators; different thresholds; Run time signal; Period signal}

Description

For this 2 pages drawings

field of use

The invention is advantageously applicable to ultrasonic measuring devices according to the transit time method, in which only a minimal temporal error based on the applied sound wave period is permissible and which require the use of robust ultrasonic transducers.

Characteristic of the known technical solutions

Known arrangements for ultrasonic measuring devices evaluate the response of a trigger or comparator stage in the receiving branch as the starting time of the Ultraschall Empfangsslgnales or end of the ultrasonic transit time (DD-WP 260570). The present before the trigger stage proportions dos receive signals are ignored. In order to eliminate interference effects on the sound path, a control of the transmission signal amplitude or the trigger threshold is applied (DD-WP 240 081). This is connected to a further uncertainty for the exact detection of the start time of the ultrasonic received signal. For certain measurement tasks, e.g. Flow measurements in gas lines according to the transit time difference method, these uncertainties regarding the reception signal input are no longer negligible. For these purposes, the accuracy of these methods is no longer sufficient. A known solution for the exact detection of the start time of an ultrasonic received signal is based on an isochronous operation of the ultrasonic transmitter and receiver (DD-WP 160329). This mode of operation is associated with special requirements for the broadband of the ultrasonic transducers used and can not be applied in any case. For example, the use of such piezoelectric polymer film transducers in gas lines is not possible.

Object of the invention

The aim of the invention is to improve the precision of ultrasonic transit time measurements and the extension of the application.

Explanation of the essence of the invention

The object of the invention is to provide an arrangement for the precise determination of the start time of an ultrasonic signal received, which makes no special demands on the ultrasonic transducer and operates without special operation of the ultrasonic transmitter / receiver arrangement.

This object is achieved according to the invention in that the received signal is fed to two voltage comparators with different comparator thresholds. A first voltage comparator with a threshold value, which reliably suppresses interference signals, is supplied with the received signal, which is phase-shifted by 180 °, via a filter. The second voltage comparator with a threshold at zero volts receives the receive signal directly and forms a binary receive signal. By means of a logic circuit, a transit time and a period duration signal are formed which each act on a gate for time base pulses before a runtime or period duration counter. The runtime counter outputs address a RAM memory. The binary receive signal in the RAM memory is stored in the cycle of the time base pulses. The transit time pulse ends the transit time measurement and the signal storage is defined after a LOW half period of the binary received signal.

From the period duration counter content, a limit value for half the period of the received signal is obtained. The runtime value in the runtime counter is then corrected for the presence of receive signal components before the end of the runtime pulse.For this purpose, the RAM memory is addressed backwards by checking the runtime counter and its content is examined for the occurrence of periods of the binary receive signal before the end of the runtime measurement. The number of backward strokes is counted in a correction counter and, in the event of the presence of a complete period of the binary received signal, subtracted from the runtime value at the beginning of the correction The correction ends when no change in the binary received signal is detectable within the limit for half a period disturbances in the course of the binary received signal are hidden by means of a peak counter.

The arrangement according to the invention for determining the time of use of an ultrasonic received signal is characterized in that a sequence control for emitting a transmission pulse is connected to a transmission amplifier, the set input of the Laufzeitflipflop and the reset inputs of time and period counter. The transmitter is connected to the ultrasonic transmitter. An ultrasonic receiver is connected via a phase reversal stage and a filter to a first voltage comparator and directly to a second voltage comparator. The output of the first voltage comparator leads to the set input of a first flip-flop whose output is connected to an input of an AND gate. The other input of the AND gate is connected to the output of the second voltage comparator, the clock input of the period counter and the data input of the RAM memory. At the output of the AND gate of the set input of the second flip-flop is connected. The output of the second flip-flop is connected to transmit the period duration signal to the gate of the period counter, the loading input of the shift register and the sequencer.

The inverted output of the second flip-flop is connected to the reset ring of the period counter and a second AND gate. A data output of the period counter is connected to the return input of the Laufzeitflipflop whose inverted output is connected to the reset inputs of the first and second flip-flops. The output of the Laufzeitflipflop is connected to the other input of the second AND gate, the output of which supplies the transit time pulse to the gate of the runtime counter. The time base generator is connected to the output of time base pulses with the two gates of period duration and run time counter. The outputs of the period counter are connected to the data inputs of the shift register. The shift register is connected to the sequencer for transmission of the shift clock. Its parallel outputs are connected to the data inputs of the reference value counter. The sequencer is connected to the reference counter for delivering a count clock and a load pulse.

The outputs of the reference counter result in the provision of the limit value for half a period of time to the Referenzkompkomp '- ^ whose output is connected to the flow control.

The outputs of the runtime counter lead to data inputs of the arithmetic unit and to the address inputs of the RAM, whose read / write input and data output are each connected to the sequencer. The count-down input of the run-time counter, along with the count inputs of the limit and peak counters, feeds to the sequencer, which issues read clock pulses. Limit, peak and correction counters each have a reset signal line from the sequencer. The peak counter e.r holds a count clock from the sequencer via a line. Limit and correction counters are each connected via a line for transmitting a load pulse to the flow control. The outputs of the peak counter lead to data inputs of the limit counter, the correction counter, the peak comparator and the arithmetic unit. The other input of the peak comparator is supplied from a read-only memory, the limit for a peak width, while its output is connected to the flow control. The outputs of the Begrenzungszahlers are connected to the Begrenzungskomparator, the correction counter to the arithmetic unit. The outputs of the arithmetic unit, which are connected to the flow control via function control lines, lead with a validity signal from the flow control to subsequent evaluation units. The found arrangement works as follows:

The sequencer switches the RAM memory to the "write" operating mode and outputs a transmit pulse The transmit pulse leads via transmit amplifier and ultrasonic transmitter to the emission of an ultrasonic signal. This resets the first and second flip-flops and activates the run-time signal.

The runtime signal opens the gate for time base pulses on the runtime counter, whereby the transit time measurement starts. Outputs of the runtime counter form the address of the RAM memory, which continuously stores the binary receive signal present at its data input.

The ultrasonic signal arriving at the ultrasonic receiver passes as a received signal via the phase reversal stage and filter to the first voltage comparator with a selected for Störsignalunterdrückung Komparatorschwelle to form the trigger signal and further passes directly to the second voltage comparator with the comparator threshold zero volts to form the binary received signal. From the first pulse of the trigger signal, the first flip-flop is set, thereby enabling the second flip-flop to set by the next pulse of the binary receive signal. With the setting of the second flip-flop, the transit time pulse ends. As a result, the counting of the timebase pulses in the runtime counter ends and the storage of the binary receive signal in the RAM memory is completed with a completed LOW half period. Furthermore, the period duration pulse starts, which causes the counting of time base pulses in the period counter via the gate. As a further effect, after setting the second flip-flop, the period counter is enabled for the counting of periodon of the binary received signal. When the period counter reaches a fixed state, it resets the runtime flip-flop and above it first and second flip-flops. The consequence is the termination of the period duration pulse. The trailing edge of the period duration pulse loads the shift register with the state of the period duration counter and triggers the time correction in the sequence control. Since the limit comparator for half a period of the binary received signal must be available as a termination criterion of the time correction, is moved over the Schiebetaktleitung the assumed in the shift register period counter contents repeatedly under consideration of the fixed state in the period counter until the Schieberegisterinhdt a mittieron half period. Subsequently, by activating the corresponding load pulse line, the shift register contents are taken over into the reference value counter. The reference counter receives a fixed number of. Counting clocks, so that its outputs then provide the limit for half a period of the limiting comparator. Before the actual delay cycle cycles with the aim of accurately determining the received signal input, correction, limiting and peak counters are reset via the corresponding lines and the RAM memory is controlled in the "read" operating mode In accordance with the defined termination of the binary received signal storage in the RAM memory, the time-of-flight correction starts with the search for a LOW / HIGH transition.

The sequencer generates read clock pulses, which count back the runtime counter and thus address the value of the binary receive signal stored before the end of the runtime measurement and increase the correction and limit count.

If, in the course of the correction cycles, the content of the limit counter is greater than the limit value for half a period, then there is no LOW / HIGH transition in the stored received signal waveform; the signal input was determined with the last detected HIGH / LOW transition. In this case, the sequence control activates the validity signal for characterizing the output value of the arithmetic unit as a valid corrected propagation time value and initiates a new measurement process with the output of a transmission pulse.

As long as the limit counter contents remain below the limit for half a period, the RAM memory output determines the further process.

If the RAM output is HIGH, the peak counter is incremented by one step. If its content is greater than the limit value for a peak width, then there was a LOW / HIGH transition. The sequencer then proceeds to examine the stored waveform after the HIGH / LOW transition as described below. If the peak count remains below the peak width limit, the scheduler continues the search for a LOW / HIGH transition with the generation of a new latch clock pulse. If the RAM output is LOW, the peak counter content is checked before the output of a new read clock pulse. If this is smaller than the limit value for a peak width, then there was a HIGH peak. The scheduler then resets the peak counter, which means hiding a HIGH peak. If the peak counter content is greater than the threshold value for one peak width, then the peak counter remains unchanged since it is then a LOW peak in the other half period just started.

If the sequence control has detected a LOW / HIGH transition by means of the RAM output equal to HIGH and the peak counter input greater than the limit value for a peak width, then the further signal course with respect to a HIGH / LOW transition is examined. The peak counter contains the number of read clock pulses incurred in the already started second half cycle of the stored tone waveform. Accordingly, its content is loaded into the limit counter and then the peak counter is reset. The sequencer outputs read clock pulses again. The flow control is now from the limiter comparator

indicates that the limit counter content exceeds the limit for half a period, there is a

Wrong measurement with too long half period before. The sequencer then aborts the time-out correction by no Validity signal outputs, but with a transmit pulse initiates a new measurement process. If the limit counter contents remain below the limit for half a period, the RAM output determines the

further course. If the RAM output is LOW, the peak counter is incremented by elP9n step. If its content is greater than the limit for a peak width, then there was a HIGH / LOW transition, d. H. a complete period of the stored binary received signal has been processed.

The sequencer then causes the arithmetic unit from the last runtime value via the function control lines Subtract the contents of the correction counter and the peak counter. Subsequently, the correction and the limit counter

is loaded with the contents of the peak counter corresponding to the number of read clocks already applied in the new period of the stored binary received signal. The peak counter is reset and the flow control returns to

Looking for a LOW / HIGH transition over. If the peak count was below the peak width limit, the sequencer sets the search for a HIGH / LOW transition continues with a new read clock pulse. If the RAM output is high, the peak counter, as described above, will be before the output of a new read clock pulse

checked for suppression of LOW or HIGH peaks.

embodiment

The solution according to the invention will be explained in more detail with reference to a possible embodiment in conjunction with the figures of the drawing.

FIG. 1 shows the circuit arrangement for determining the time of use of an ultrasonic received signal. The arrangement consists of an ultrasonic transmitter 2 with transmission amplifier 1 for emitting the ultrasonic signal 101, an ultrasonic receiver 3 for obtaining the received signal 102, a phase reversal stage 4 and 5 with the filter 5 to the ultrasonic receiver 3 existing first voltage comparator 6 and a direct The trigger signal 104 leads from the first voltage comparator 6 to a first flip-flop 8, the output of which is connected to an AND gate 9. The AND gate 9 is further connected to the second voltage comparator 7, the period counter 11 and the RAM 22. At the AND gate 9, the second flip-flop 10 is connected. The period duration pulse 106 leads from the second flip-flop 10 to the gate 15, the shift register 17 and the sequencer 29. The second flip-flop 10 is connected to the period counter 11 and the AND gate 14. An output of the period counter 11 is connected to the Laufzeitflipflop 13 whose inverted output is connected to the first and second flip-flop 8.10. The output of the Laufzeitflipflop 13 is connected to the AND gate 14, whose output delivers the transit time pulse 105 to the gate 20. The timebase generator 12 is connected to the gates 15 and 20. The outputs of the period counter 16 are connected to the shift register 17. From the sequencer 29, the shift clock 108 leads to the shift register 17. The parallel outputs of the shift register 17 are connected to the data inputs of the reference value counter 18. From the sequence controller 29, the count clock 11 and the load pulse 112 are supplied to the reference value counter 18.

The outputs of the reference value counter 18 supply the limit value for half a period 120 to the reference value comparator 19 whose output is connected to the sequencer 29.

The outputs of the time counter 21 lead to data inputs of the arithmetic unit 28 and to the address inputs of the RAM memory 22, which is connected to the sequencer 29 via the read-write control line 109 and the RAM data line 110. The sequence controller 29 outputs read clock pulses 107 (Jen run time counter 21, the limit counter 24, and the correction counter 27.

Limit counters 24, peak counters 23 and correction counters 27 each have a line for transmitting the reset signals 116, 114, 118 from the sequencer 29. The peak counter 23 receives from the sequencer 29 a count clock 113. Clipping and correction counters 24, 27 are each via one line 115,117 connected to the flow control 29 for transmitting a load pulse. The outputs of the peak counter 23 lead to the limit counter 24, the correction counter 27, the peak comparator 26 and the arithmetic unit 28. The peak comparator 26 is supplied from a read-only memory 25, the limit for a peak width 121, while its output is connected to the flow control 29. The limit counter 24 is connected to the limit comparator 19, the correction counter 27 to the arithmetic unit 28. The outputs of the arithmetic unit 28, which is connected to the sequencer 29 via function control lines 119, provide the corrected runtime value 1? 2 together with a validity signal 123 from the sequencer 29. The sequence control 25 supplies to the transmission amplifier 1, the Laufzeitflipflop 13, the period counter 16 and the Laufzeitzähler 21 a transmission pulse 100. Figure 2 shows the timing of the transmission pulse 100, the received signal 102, the Auslpseslgnales 104, the binary received signal 103 with interfering peaks, the Running time signal 105, the period duration signal 106 and illustratively the hypothetical time course of a corrected runtime signal 124th

The transmission pulse 100 output by the sequence controller 29 leads to the start of the runtime signal 105 and thus to the continuous storage of the binary receive signal 103 in the RAM memory 22. If the receive signal 102 reaches an amplitude which is sufficient to respond to the first voltage comparator 6, the following LOW occurs / HIGH transition of the binary received signal 103, the runtime signal 105 terminates and thus also the storage of the binary receive signal 103 in the RAM 22. The still formed period duration signal 106 is used to obtain a limit for half a period 120 for the time correction.

The transit time correction is in each case over half periods of the binary received signal 103 stored in the RAM 22

by outputting read clock pulses 107 from the sequencer 29 to the reverse count clock input of the run time counter 21 upon evaluation of the RAM data line 110 fed to the sequencer 29 and the outputs of

Limiting comparator 19 and peak comparator 26 executed in the arithmetic unit 28. The corrected runtime value 122 exists only as an output variable of the arithmetic unit 28. The representation of the time course

a corrected runtime signal 124 serves only to illustrate the effect of the delay correction.

The arrangement found besides the advantage that there are no special requirements for the ultrasonic transducer, the

advantageous property, despite different propagation conditions for the ultrasonic signal with its diverse

Impact on the course of the envelope of the received signal amplitude always provide precise runtime values.

Claims (1)

Circuit arrangement for determining the time of use of an ultrasonic received signal with transmitter amplifier, ultrasonic transmitter, and ultrasonic receiver, characterized - That a sequence control (29) for dispensing a transmission pulse (100) with the transmission amplifier (1), the Laufzeitflipflop (13), the period counter (16) and the Laufzeitzähler (21) and for outputting a read clock pulse (107), with the Rückwärts-Zählclockingang the runtime counter (21), the limit counter (24) and the correction counter (27) and for outputting a shift clock (108) with the shift register (17) and the read-write control line (109) with the RAM memory (22) and to deliver a count clock (111) and a load pulse (112) with the reference value counter (18) and to deliver a count clock (113) and a reset signal (114) reduce peak counter (23) and for delivering a load pulse (115) and a reset signal (116) with the limit counter (24) and also for delivering a load pulse (117) and a reset signal (118) with the correction counter (27) and further via function control lines (119) with the Recheneinhe it (28) is connected and outputs a validity signal (123), - That the ultrasonic receiver (3) via a phase reversal stage (4) and a filter (5) with a first voltage comparator (6), the output of which delivers the trigger signal (104) to the set input of a first flip-flop (8), and directly with a second voltage comparator (7) whose output supplies the binary receive signal (103) to the AND gate (9), the period counter (11) and the RAM memory (22), - That the output of the first flip-flop (8) is connected to the AND gate (9) whose output leads to the set input of the second flip-flop (10) whose output the period duration signal (106) to the gate (15) before the period counter ( 16), to the charging input of the shift register (17) and to the sequencer (29), while the inverted output of the second flip-flop (10) with the reset input of the period counter (11) whose output leads to the reset input of the Laufzeitflipflop (13) , and connected to the AND gate (14), - That the inverted output of the Laufzeitflipflop (13) leads to the reset input of the first flip-flop (8) and the second flip-flop (10), while its output is connected to the AND gate (14), from whose output the runtime signal (105) to the gate (20) is delivered at the forward count clock input of the run time counter (21) while the time base generator (12) is connected to the port (15) and the port (20), - That the data outputs of the period counter (16) with data inputs of the shift register (17) and data outputs of the shift register (17) with data inputs of the reference value counter (18) and data outputs of the reference value counter (18) with data inputs of the Begrenzungskomparators (19) and the output of the Begrenzungskomparators ( 19) are connected to the sequence controller (29), - That the data outputs of Lcufzeitzählers (21) to address inputs of the RAM memory (22) whose output via the RAM data line (110) is connected to the flow control (29), and data inputs of the arithmetic unit (28), - That the data outputs of the peak counter (23) to data inputs of the Begrenzungszählers (24) whose outputs are connected to the Begrenzungskomparator (19), and to inputs of the peak comparator (26) whose output to the flow control (29) and whose other inputs for providing the limit value for a peak width (121) are connected to the read-only memory (25) and to inputs of the correction counter (27) whose outputs are connected to the arithmetic unit (28) and to the arithmetic unit (28 ), which provides the corrected runtime value (122) at their outputs.