DE4202677C1 - Periodic signal appts. for signal transmission paths - tests quality by injecting digital square wave signal for evaluation by shift register and comparator together with reference - Google Patents

Abstract

Test signals (2) in the form of square wave inputs are fed to an A-D converter (4) coupled to a line (5) that supplies a shift register (A). In addition short duration signal 'spikes' (3) are also supplied. Within the clock period of the A-D converter the pulses are moved between register stages (a1-a14). The register has ten outputs fed to multiplier stages together with the outputs of a memory (B) providing a reference pulse (6). The values are added together (7) to supply an output shift register (C) that provides a well defined signal output. ADVANTAGE - Efficient noise suppression for fast testing requiring no synchronisation of test signal.

Description

The invention relates to a device in the preamble of claim 1 Art.

Such devices are versatile, ins special in telecommunications technology when testing the quality of transmission links.

The important thing here is the arrival in a signal stream rising edge of a test pulse or the zero crossings a periodic test signal to determine the Record the test signal and its shape (height, Length, shape). The problems are here especially in that signals to be determined usually are disturbed. The original clean signal stream is due to interference, for example, on transmission stretches occur, distorted and layered, for example with noise or interference signals of a different frequency. Then but it is very difficult to have a zero crossing or an on to recognize the rising edge of a test signal exactly.

In known devices of the type mentioned it requires synchronization with the test signal to reach. But that is disadvantageous, especially since  synchronization takes a longer time to test synchronization is achieved. This can also be done can only be achieved with periodic test signals.

The object of the present invention is therefore to to create a device of the type mentioned at the outset, which enables shorter test times with good interference suppression light.

This object is achieved with the features of Labeling part of claim 1 solved.

The device according to the invention can be varied Run way. You can, for example, in a computer and its working memory are simulated. For higher ones Evaluation speeds are recommended, however, a hard goods solution. The device according to the invention delivers current values that correspond to the respective coverage ratio between the Comparison pulse and the test signal correspond. The out In their chronological order, initial values give impulse shapes where the first maximum is the temporal location of the Rising edge or the zero crossing of the test signal displays. It is not necessary to set the syn wait for chronization. Rather, it will be the first incoming test signal correctly displayed. This is the Destination time extremely fast and it can't even periodic, i.e. individual test signals are determined. Baseline values of significant height only occur in the case of similarity of the test signal with the comparison pulse. All off softening signal forms are suppressed. So there will be Disruptions of all kinds strongly suppressed. Even deviations the received form of the test signal from its transmitted Form as it is after overcoming long transmission distances occur are corrected because the initial values are also at the true rising edge of a disturbed test signal gene.  

The device according to the invention is suitable for determination of test signals in the form of rectangular pulses, but also to determine other test waveforms, e.g. B. from Sinussi gnalen.

The features of claim 2 are advantageously provided. This ensures that the comparison pulse is not is longer than the test signal, so that reaching a Maximum of the initial value the start of the test signal clearly indicates.

The features of claim 3 are advantageously provided. The more precisely the comparison pulse corresponds to the test signal, the better the interference suppression and the better ge the undisturbed waveform. At Rectangular signals correspond to the comparison pulse undisturbed rectangular pulse. For sinusoidal signals, the ver DC pulse advantageous as a corresponding sine half-wave educated.

According to claim 4, the signal amplitudes to be processed normalized, there is a reduction in the calculation effort especially when determining the rectangle signals as well as better interference suppression, and it lets the maximum of the initial value in a simple manner determine a threshold value comparator, since it is on detection of the specified test signal always has the same level.

The features of claim 5 are also advantageous intended. Here, the shape of the Output signals forming output values in the output value Analyze memory and thus the maximum of the output si Always determine gnales with certainty, especially when when working without standardized amplitudes.

The features of claim 6 are also advantageous intended. In this way the signal shift memory  fully used or the signal resolution of the front existing size of the shift memory adjusted. The An fit can be beneficial by changing the converter tactful happen.

The features of claim 7 are also advantageous intended. This type of calculation is sufficient because with nor values between the first and the last of Rectangular signal occupied place of the comparison pulse of the values are constant. It becomes the computational effort significantly reduced with the possibility of working increase speed accordingly.

In the drawing, the invention is for example and cal represented mathematically. Show it:

Fig. 1 is a schematic representation of a erfindungsge MAESSEN device in the block diagram,

Fig. 2a shows a signal stream to be tested with different union pulses and disorders,

FIG. 2b shows the waveform of the comparison pulse,

Fig. 2c in timed relation to the signal of Fig. 2a, the output signals of the device,

Fig. 3a, a sinusoidal signal to be processed with disorders

FIG. 3b, a comparison pulse in the form of a half sine wave,

Fig. 3c is a rectangular pulse comparison,

Fig. 4 shows a variant of Fig. 1 in partial representation of its block diagram and

Fig. 5 shows a further variant of the device of Fig. 1 in partial representation of its block diagram.

Fig. 1 shows an apparatus for testing the quality of a line which is introduced as an input line 1 to the device and test signals are sent in the form of rectangular pulses of about 2 of an unillustrated transmitter forth. Above the input line 1 , the incoming signal current is shown, which consists of an undisturbed pulse 2 and a nadelförmi gene interference pulse 3 of greater height in the example shown.

The signal current passes from the input line 1 to an A / D converter 4 and is converted there, namely at temporal intervals that are several times shorter than the test signals to be evaluated. The sampling frequency must therefore be several times greater than the test signal frequency. (In the illustrated embodiment, it is four times larger).

The converted values go via a line 5 into the input of a signal shift memory A which has memory locations a ₁ -a ₁₄ . In time with the A / D converter 4 , the converted values are pushed one after the other through the memory locations a ₁ -a _{14 of} the signal shift memory A.

Furthermore, a read-only memory B is provided, which has 10 memory locations b ₁ -b _{10 in the} exemplary embodiment.

In the example shown, the signal shift memory A contains the pulses 2 and 3 of the signal. In the fixed value memory B there is a comparison pulse 6 with which the pulses of the signal are to be compared in places b ₂ -b ₅ . To simplify the illustration, a simple embodiment is also selected with regard to the computing effort in the device, in which the values stored in the storage locations in the memories A and B are normalized to 1, that is to say they only consist of 0 and 1 be.

The memory locations of the same number of the Signalschiebespei chers A and the read-only memory B are each connected to a multiplier m ₁ -m ₁₀ . The output lines carrying the multiplication result of the multipliers m ₁ -m ₁₀ lead to an adder 7 , which adds up the multiplication results of all multipliers and outputs this sum as an output value on the output line 8 . The multipliers m ₁ -m ₁₀ and the adder 7 also operate in time with the A / D converter 4 .

In order to be able to examine the output values on the output line 8 more precisely, an output shift memory C is provided which corresponds to the signal shift memory A and in the exemplary embodiment shown has 16 memory locations c ₁ -c ₁₆ , in which the output values of the adder 7 in time with the A / D converter to be pushed.

If you now consider the pulses that are currently present in the memories A and B, you can see that the rectangular pulse 2 , ie the test signal, is currently on the memory locations zen a ₉ to a ₁₂ . The interference pulse 3 is currently on a ₆ . Both pulses have already passed the memory locations a ₂ to a _{5 of} the sliding memory A, which are compared with the locations b ₂ to b _{5 of} the read-only memory B who the. At the time shown, the output signal on line 8 is a 0, which has just been written into the first memory location c _{1 of} the output shift memory C.

The interference pulse 3 had previously run through the locations a ₂ to a _{5 of} the signal shift memory A, which resulted in a 1 on the output line 8 four times. This results in a low rectangular pulse 3 'of height 1 and length 4. Before that, there were twice a 0, which are now in positions 6 and 7 of the output value memory C. Again before that, the square-wave pulse 2 in signal shift memory A ran past its positions a ₂ to a ₅ , first in partial dec kung with output signal 1 , then increasing until it was completely covered, i.e. output value 4 and then decreasing again. This results in an essentially triangular signal 9 , which is shown in the output value memory C.

At the time when the pulse shift 2 in the signal shift memory A was exactly in the places a ₂ to a ₅ , i.e. exactly aligned with the comparison pulse 6 in the read-only memory B, there was full coverage between the pulses as a sign that the test signal, i.e. the pulse 2 , is recognized. This can easily be recognized in the output shift memory C in that the signal 9 has the maximum of 4.

The evaluation of the signals on the output line 8 can also be carried out more simply, that is to say without an output value memory C, only with a simple threshold value comparator 10 which is connected to the output line 8 and then generates an output signal when the output value on the output line 8 has the value 4 has reached.

If a maximum is determined by the output value store C or a threshold comparator 10, so the test signal located in the examined signal current is detected, the evaluation system, not shown, can circuits as an opportunity to take from the signal shift memory 2, the test signal, so the pulse 2, copy or copy it from a further signal memory, not shown, in order to pass it on to a closer examination, in which the quality of the transmission link is determined by comparison with the form originally sent.

Deviating from the device shown, in particular the signal shift memory A advantageously formed so be that it receives the signals of the incoming signal stream not in standardized form, but with their true ampli represents tude so that it is the signal stream in its true form which represents impulses.

The multipliers m ₁ -m ₁₀ and the adder 7 work particularly simply if the pulses in the signal shift memory A and in the read-only memory B are normalized in their amplitude, in particular if they are normalized to 1, as is shown in FIG. 1 is shown.

This normalization of the signal pulses can take place at various points in the device shown. An amplitude normalization can already be carried out on the input line 1 before the A / D converter is reached. The normation can also be done in the A / D converter 4 , in the signal shift memory A or even in the adder 7 .

With a device corresponding to FIG. 1, test signals in the form of rectangular pulses can be compared with a comparison pulse. This is shown in Fig. 2 using different rectangular pulses.

Fig. 2b shows the comparison pulse 6 against which the incoming pulses are to be compared. Fig. 2a shows different pulses to be determined. Fig. 2c shows the triangular pulses of the output value of the adder. 7 The pulses in Fig. 2a run on the line axis shown to the left, past the fixed comparison pulse 6 of Fig. 2b. The triangular pulses of FIG. 2c accordingly run to the left on the line axis.

The pulse 2 already mentioned in FIG. 1 results in the triangular pulse 9 . A pulse 2 c, which has the prescribed height, but has too large a width, results in a triangle-like pulse 9 c, which has the same height as the pulse 9 a, but is elongated trapezoidally. A pulse 2 d of correct height that is too short results in a three corner-like pulse 9 d, which is trapezoidal, but does not reach the maximum of the triangular pulse 9 a.

If test signals in the form of pulses 2 , 2 c or 2 d are evaluated with the device of FIG. 1, the threshold value comparator 10 is set to a threshold value, which is shown in FIG. 2 c as a horizontal dashed line. This threshold value goes exactly through the maximum of the triangular pulse 9 , which corresponds to the undisturbed test signal.

One can see in Fig. 2c that the threshold value would be 10 the triangular pulses 9 and 9 c reliably detect, but not the momentum 9 d, as it is at its maximum too low. It follows that the threshold value comparator 10 with the threshold value set in accordance with FIG. 2c, which is at the level of the maximum of the triangular pulse 9 for the undisturbed test signal 2 , detects all pulses 2 and 2 c that are at least as long or longer than the comparison pulse 6 . Too short pulses, e.g. B. the pulse 2 d, but lead to a triangular pulse 9 d with too low a maximum and are ignored.

If you also want to differentiate the longer pulse 2 d safely, we recommend using the output value memory C, on which the trapezoidal shape of the triangular pulse 9 c is shown and can be examined with suitable means.

Completely different impulses can also be recognized. A bipolar pulse 2 e leads to a triangular pulse 9 e with a positive and a negative maximum. A pulse 2 f, which has the length of the comparison pulse 6 , but has too low an amplitude, leads to a triangular pulse 9 f of a perfect triangular shape, but with a maximum that is too low. A correspondingly long but too high pulse 2 g leads to a perfect but too high triangular pulse 9 g.

Finally, a pulse 2 h is shown, which is half the length of the comparison pulse 6 , but is too high. This pulse 2 h leads to a triangular-like pulse 9 h, which is trapezoidal, but exceeds the maximum of the triangular pulse 9 a. If a threshold value comparator 10 were used which has the threshold value shown in FIG. 2 c, the pulse would be recognized, although it does not correspond to the comparison pulse 6 . Therefore, the normalization of the pulses of the signal already mentioned is advantageous. It leads the impulse back to form 2 d for 2 h. However, this leads to a triangular signal 9 d, the maximum of which is lower than that of the threshold value. Then the signal pulse 2 h can also be safely sorted out with a threshold value comparator 10 .

Sorting out the too short pulses 2 d and 2 h is also important because the first maximum, which corresponds exactly to the rising edge for pulses 2 , 2 c, 2 e, 2 f and 2 g, is somewhat advanced. If the pulses 2 d and 2 h were too short, the rising edge of the pulse to be determined would not be recognized exactly.

The main advantage of the device according to the invention is that signals are recognized even when they are severely disturbed. If, for example, immediately before the rising edge of a pulse to be detected, there is a disturbance, for example in the form of the interference pulse 3 shown in FIG. 2a, this is completely suppressed and does not lead to an error in the detection of the temporal position of the rising edge of the determining impulse.

Also in shape strong interference pulses as shown in Fig. 2a the example of the pulse 2a can be reproduced correctly. The corresponding triangular signal 9 a speaks ent of that of the undisturbed pulse 2nd The point at which the triangular pulse 9 a reaches its maximum, that is to say the threshold value shown, corresponds to the rising edge of the signal pulse 9 a, even if it is difficult to know there.

The device shown in Fig. 1 can be varied in diverse ge ways. In particular, it is advantageous to provide more than the memory locations for the memories A, B and C shown in each case. This allows the pulses to be divided much more finely, which enables more sensitive processing.

In Fig. 1 a very crude sampling of the signal is set to represent, in which the said compared pulse 6 in shape exactly corresponding pulse is divided into four parts 2, as can be seen on the occupancy of the memory locations in the signal shift memory A. Such a rough scan is sufficient for many purposes, but also has the disadvantage of less good interference suppression. For example, the needle-shaped interference pulse 3 leads to a relatively large interference pulse 3 'on the output line 8 . The value 1 would result in four adjacent storage locations in the output value memory C.

If the sampling frequency were increased significantly and the shift memories A, B and C would be extended accordingly, so that, for example, the pulse 2 would not be shown on two memory locations, but instead, for example on 100 memory locations, then the output value signal 3 ', which results in the compensation value memory C. , and that is generated by the needle-shaped interference pulse 3 , drop to below 1% of the threshold value and thus have no influence whatsoever. Such relationships correspond to the representation in FIG. 2.

In the previously mentioned embodiment, the multipliers m ₁ -m _{10 are designed in} such a way that the values of the memory cells a _x and b _{x are} normally multiplied with one another. Multiplying a positive number by a negative number produces a negative result. Therefore, from the bipolar pulse e 2 of the bipolar triangular pulse 9 is e accelerator as Fig. 2. The multiplication in the multipliers m ₁ -m ₁₀ can, however, also take place in amounts, so that the absolute values of the values in the memory cells a _x and b _x are multiplied. For example, the squares of the amounts can be multiplied. In the example of the bipolar pulse 2 e, this would result in this being treated as a unipolar pulse.

However, the device according to the invention can equally well be used to determine non-rectangular test signals. For example, it can be used to determine sinusoidal signals, triangular signals, etc. The comparison pulse should correspond as closely as possible to the undisturbed signal shape. In particular, it should have the length of the undisturbed signal shape. It can also be shorter. However, it should not be any longer, since otherwise time errors can result, as explained with the aid of the triangular pulses 9 d and 9 h in FIG. 2 c. The signal shape should also correspond as closely as possible to the comparison pulse, in other words be rectangular in the case of a rectangular signal. In the case of processing non-rectangular test signals, at least the signal shift memory A should be designed so that it can store a larger number of different amplitudes in order to be able to reproduce the signal shape, at least for the purpose of removing them from this memory when the evaluation circuit detects them To be able to copy their exact signal form for the purpose of further checks.

The device according to the invention is particularly advantageous when evaluating sinusoidal test signals. Fig. 3a shows such a sine signal 14 , which is superimposed by strong interference pulses. These interference pulses in particular prevent an exact determination of the zero crossings of the sinusoidal signal, since the interference signals themselves produce zero crossings. If this sine signal 14 is sent through the device shown in FIG. 1, a corresponding sine half-wave being present in the fixed value memory B as the comparison signal 11 , an output value signal results on line 8 of the device shown in FIG. 1, which corresponds to the cosine 12 shown in broken lines corresponds to Fig. 3a. With its maxima, this specifies the zero crossings of the sinusoidal signal 14 exactly and is completely interference-free.

As a comparison pulse 13 can also be the rectangle of Fig. 3c are used, substantially the same output value signal obtained in the form of the cosine 12th

In this way, the zero crossing can be determined very quickly on an incoming severely disturbed sinusoidal signal 14 , specifically already on the basis of the first half-wave, and the intended processing of the signal can be started. A longer, time-consuming synchronization is not necessary. In this way, even short sine burst signals consisting of a few periods can be reliably checked.

In the embodiment of the device according to the invention shown in FIG. 1, the signal shift memory A is used very uneconomically, since it is longer than the pulse 2 to be tested of the test signal. The signal shift memory A can be shortened to the length of pulse 2 , ie to the length of four memory locations. Correspondingly, the read-only memory B can also be shortened to length 4 . This also reduces the number of multipliers m. However, it is preferable to make optimal use of longer memories in that the pulse 2 is brought to the length of the signal shift memory A by increasing the converter clock of the AD converter 4 , which then results in the advantages of a finer resolution already discussed.

In the case of longer memories, the device shown in FIG. 1 naturally results in a considerable computational effort even if there are only standardized values in the individual memory locations. FIGS. 4 and 5 show executive variants with which the computation can be significantly reduced.

Fig. 4 shows a signal shift memory A ₄ , on the line 5 from the AD converter 4, not shown, the ge converted signal current is fed and pushed in the memory, just like the signal shift memory A of Fig. 1. In the case of Fig. 4th a test signal 15 is compared with a comparison memory pulse 16 long four. The conditions are the same as in the embodiment of FIG. 1, in which the comparison pulse 6 with four storage locations is compared. In the case of the embodiment variant of FIG. 4, however, this is done in a simpler manner, in that the signals stored in each case are removed from each of the four shift clocks via the four lines shown and are fed to an adder 17 , in which they are added, at only four adjacent memory locations of the signal shift memory A ₄ . The sum is given in the work cycle of the device via line 8 to the evaluation circuit, which can be constructed in accordance with the embodiment of FIG. 1, that is to say with an output value memory C or a threshold value comparator 10 . The resulting output signals on line 8 result in the same form as in the device of FIG. 1.

It can be seen that the signal shift memory A _{4 is also} unnecessarily long in the example shown in FIG. 4. In the example shown, it can be reduced to the four memory locations connected via lines to the adder 17 , or the number of lines leading to the adder 17 would have to be increased for higher resolution with a larger number of memory locations.

Fig. 5 shows a particularly simple Ausfüh tion variant with a signal shift memory A ₅ erhebli cher length of z. B. 256 memory locations. The computing effort when using the device of FIG. 1 would be considerable. It would be e.g. B. 256 multipliers required. In the example of FIG. 5 in the upstream A / D converter, care is taken to ensure that the test signal 18 , which corresponds, for example, to pulse 2 of FIG. 1, is converted such that it is shift-memory A exactly in the length of the signal ₅ fits. If its rising edge is in the last place, its rear falling edge is in the first (left) position of the signal shift memory A ₅ . This moment is shown in Fig. 5.

Care is also taken to ensure that the values stored in the signal shift memory A ₅ are normalized, for example to 1 and 0. Then simple considerations show that it is sufficient to add only the values entering the memory and those leaving the memory Subtract values to get the correct output signal on output line 8 . It is therefore sufficient to connect the first memory location with a positive input and the last memory location with a negative input of an adder 27 with one line each. The computing effort is thereby reduced in the example shown compared to the device of FIG. 1 by a factor of 256 or the processing speed is increased accordingly.

Claims (7)

1. A device for checking the quality of a transmission line by transmitting a test signal, its subsequent detection in the received signal current and by comparing the received test signal with its transmitted form, characterized in that for detecting the test signal ( 2 - 2 i, 10 , 15 , 18 ) an A / D converter ( 4 ) is provided which samples the signal current at intervals which are several times smaller than the pulse length or half the period length of the test signal, and the converted values at the input of a signal shift memory (A, A ₄ , A ₅ ) with several places (a ₁ -a ₁₄ ), in which they are shifted from place to place in the converter cycle and that a comparison device is provided which, for each converter cycle, the values of certain successive places (a ₂ -a ₅ ) of the signal shift memory with the values of the successive places (b ₂ -b ₅ ) of a comparison pulse divided into corresponding places ( 6 , 11 , 13 , 16 ), the length of which is essentially equal to the pulse length or half the period of the test signal, calculated multiplicatively and with each converter cycle, all products are added to an output value which is fed to an evaluation device ( 10 , C) . 2. Device according to claim 1, characterized in that the length of the comparison pulse ( 6 , 11 , 13 , 16 ) is shorter than the pulse length or half the period of the test signal ( 2 - 2 i, 10 , 15 , 18 ). 3. Device according to one of the preceding claims, characterized in that the shape of the comparison pulse ( 6 , 11 , 13 , 16 ) corresponds as closely as possible to the shape of the test signal. 4. Device according to one of the preceding claims, characterized in that the evaluation device is a threshold value comparator ( 10 ), the amplitudes in the signal shift memory (A, A ₄ , A ₅ ) and that of the comparison pulse ( 6 , 11 , 13 , 16 ) or the derived products are standardized. 5. Device according to one of the preceding claims, characterized in that the evaluation device has an output shift memory (C) in which the Output values are shifted further in the converter cycle. 6. Device according to one of the preceding claims, characterized in that the length of the signal shift memory (A, A ₄ , A ₅ ) corresponds to the length of the comparison pulse ( 6 , 11 , 13 , 16 ). 7. The device according to claim 6 for determining right corner signals, characterized in that the amplitudes in the signal shift memory (A ₄ ) are standardized, the values arriving in the signal shift memory are continuously added and the values expiring from the signal shift memory are continuously subtracted from this sum and the total is continuously fed to the evaluation device ( 10 , C).