DD281289A5 - CMOS GATE ARRAY ARRANGEMENT - Google Patents

Abstract

The invention relates to a CMOS gate array arrangement in silicon gate technology for the design and manufacture of integrated logic circuits. On strassenfoermigen active areas are arranged perpendicular to the Laengsrichtung these areas transistor gates. The transistor gates are branched at least once within the active regions. Within each active region partitioned by the transistor gate is at least one contact point. The drain-source regions of a transistor divided by the branched transistor gate make it possible to use different transistor sizes by connecting the corresponding contacting points. The possible dual use of a transistor for two functional cells increases the specific degree of integration of the gate array arrangement. {Microelectronics; Logic circuits; Silicon gate technology; CMOS technology; Gate array arrangement; continuous active areas; Gate insulation; branched transistor gate; variable transistor magnitudes}

Description

For this 3 pages drawings

Field of application of the invention

The invention relates to a CMOS gate array arrangement and is used in the construction of customer-requested logic circuits.

Characteristic of the known state of the art

CMOS gate array arrangements are known with which a flexible customer-specific configuration, in particular a definition of the sizes of the active transistor cells and the wiring areas, is possible on the basis of predefined and prefabricated basic structures.

According to DD-PS 262306 (H01L-27/10) a semiconductor device is known which uses the principle of gate isolation for structuring the size of the transistor cells. For this purpose, the active regions of both the n- and the p-channel transistors are formed as continuous strip-shaped regions. Perpendicular to the longitudinal direction of the active regions, the transistor gates are arranged at regular intervals. The determination of the Trai sistorzellengröße is done by those gates which form the later cell boundaries are connected to positive operating voltage and ground, that the active area located under these gates safely locked iso and the resulting partial areas are electrically isolated from each other. The size of the n- or p-channel transistors is determined by the width of the active regions once in the pre-structuring phase and can no longer be influenced within the design phase. For an adaptation of Transiütorgrößen to different electrical requirements, such as larger switching currents, not possible.

Object of the invention

The aim of the invention is to reduce the design effort for application specific logic circuits and to increase the performance of gate array circuits.

Explanation of the essence of the invention

The invention has for its object to provide a CMOS gate-Vray arrangement in silicon-gate technology using strip-shaped active areas and arranged perpendicular thereto transistor gates for building integrated logic circuits, which allows the use of different transistor sizes and the specific within the design phase Degree of integration increased.

According to the invention, the object is to provide a CMOS gate array arrangement in silicon gate technology with juxtaposed stripe-shaped active regions of opposite conductivity and perpendicularly arranged transistor gates for establishing integrated logic customer-desired circuits using the gate insulation, solved by

- That di3 transistor gates are branched at least once within the active regions,

- That the branched parts such as the non-branched parts of the transistor gates are guided to contact points, which are located on both sides outside the active areas,

- That within an iodine by the Trdnsistorgatec divided active region, the drain / source region, at least one contact point is arranged, and

- That the contacting of all transistor gates outside the active areas individually or in pairs different, parallel to each other guided straight wiring track, which are parallel to the transistor gates, are assigned.

To achieve a high packing density, it is expedient that the branched parts of the transistor gates are mutually arranged on both sides of the active areas.

For an advantageous guidance of the wiring tracks, it is expedient for the branched parts of the transistor gates to be arranged opposite each other in the η-conducting and p-conducting active regions.

To achieve a high packing density as well as a narrow and uniform grid for the contacting points of the transistor gates, it is expedient that the contacting points of the branched parts adjacent portions of the respective following transistor gates are arranged offset in the direction away from the branched parts.

The use of different transistor sizes within the Ausgestnltungsphase carried by appropriate connections of the divided by the branched transistor gate drain / source regions of a transistor at the intended contact points. With a single unbalanced branch, the use of three different transistor sizes is possible. Using the transfer switch technology, two functional cells can be connected to a common data signal simultaneously with a transistor gate of the arrangement according to the invention via a common control signal. In this case, the data signal is connected to a completely separated by the transistor gate drain / source region. The dual use of a transistor for two functional cells increases the specific degree of integration of the Gato array arrangement.

embodiment

The invention will be explained in more detail rachfolgend an Ausführungsboispiel. In the accompanying drawing show

1 shows a CMOS gate array arrangement according to the invention with a single-branched transistor gate, FIG. 2 shows an electrical circuit diagram of a transistor of the CMOS gate array arrangement according to the invention with indication of the relative transistor sizes,

FIG. 3: Combination of two columns of the CiMOS gate array arrangement, FIG. 4: Electrical circuit diagram of a CMOS holding stage, and FIG. 5: Layout of high packing density of stacked CMOS holding stages.

A CMOS gate array arrangement according to the invention consists of a stripe-shaped active region 2 with a width of four contacting points 3 '(FIG. 1). Transverse to the longitudinal direction dos active region 2 are between the contacting 3 'simply branched transistor gates 1; T; The individual branches of a transistor gate 1; V; 1 "have a relative width of 1: 2: 4. Within the through the transistor gates 1; 1'; All branches of a transistor gate 1, 1 ', 1 "terminate in contacting areas 3 arranged outside of the active area 2, which each have different wiring tracks 4 lying parallel to one another; 4 '; 4 "are assigned, which are parallel to the transistor gates.

Successive transistor gates 1 are each mirrored about the longitudinal axis of the active region 2 and placed so that each 3ine contacting 3 of two adjacent transistor gates 1 of the same wiring track 4; As a result, two transistor gates 1 of one or different functional cells can be connected to the same control signal using only one wiring track 4;

To adapt to different electrical requirements, the transistor size can be varied within the design phase by connecting two contact points 3 'in the relative widths 3: 5: 6 (FIG. 2). The designations A; B; C and G1; G 2; G3 correspond to those of the layout diagram of Fig. 1. The numbers 1; 2; 4 designate the relative width of the individual branches of a transistor gate 1; 1'; 1 ". The table gives an overview of the resulting transistor connections.

relativo connection transistor connections

Transistorgr. between gate drain / source

3 AundC G1, G2, G3 A / C-B

5 BundC G1, G2, G3 B / C-A

6 A and B G1, G2, G3 A / B-C

FIG. 3 shows the combination of two mutually symmetrically arranged columns of the CMOS gate array arrangement according to the invention, of which one contains n and the other p-channel transistors. The reference numerals correspond to those of FIG. 1. In the p-type active and active regions 2 are the more branched. Parts 1 "of the transistor gates 1 are arranged opposite each other.

On the basis of the circuit shown in Figure 4 a CMOS holding stage further uses of the CMOS gate array arrangement will be explained. The CMOS hold stage consists of the series connection of the drain-source paths of 2 η channel and 2 p-Kar.al transistors between ground and the operating voltage + UB. The gate of the grounded n-channel transistor is connected to the clock signal cp and the gate of the operating voltage + UB p-channel transistor is connected to the negated clock signal cp. The two interconnected gate terminals of the intervening n- and p-channel transistors form the data input D. and the connection point of the drain-source paths of both transistors is the data output A. CMOS holding stages for clock-controlled switching through a data signal according to the following table:

ep A

J "D

"0" hold state or tristate

They are used, for example, for realizing sequential circuits. Within an n-bit latch, η CMOS hold levels are arranged so that with a clock signal, the data applied to the inputs of the n-bi'c latch is synchronously transferred to the register internal memory circuits. Using the CMOS gate array arrangement according to the invention, a space-saving topological realization of such sequential subcircuits is possible by jointly using a branched transistor gate for two CMOS hold stages.

Fig. 5 shows the layout of four successively arranged CMOS holding levels with the data inputs D1 ... D4 and the data outputs A1 ... A4. In the longitudinal direction of the active regions, the interconnects for positive operating voltage + Ub and ground as well as for the negated and ungrounded clock lines cp and cp are arranged in a first interconnect plane Lei. The connection of these interconnects with the transistor terminals and the transistor connections with each other via a second Leitbahnebene Le 2. After each second of the juxtaposed CMOS holding stages is located for electrical isolation, a gate insulation Gi, by the gate of the n-channel transistor to the Maseleiibahn and the gate of the p-channel transistor are connected to the operating voltage bus. The arranged between two gate insulators CMOS holding stages each use a branched transistor gate together for the clock-controlled connection of the operating voltage and ground potential via the ground and Botriebsspannung transistors of Figure 4.

Claims (4)

1. A silicon gate CMOS gate array arrangement with juxtaposed stripe-shaped active regions of opposite conductivity and transistor gates arranged perpendicular thereto for the purpose of constructing integrated logic customer-desired circuits using gate insulation, characterized - That the transistor gates (1) within the active regions (2) are branched at least once, - That the branched parts (1 ") as the non-branched parts (1; V) of the transistor gates (1) are guided to contact points (3) which are located on both sides outside the active areas (2), - That within each by the transistor gate (1) divided active area (2 ') at least one contact point (3') is arranged and - That the contacting points (3) of all transistor gates (1) outside the active areas (2) individually or in pairs different, parallel to each other guided straight wiring tracks (4, 4 ', 4 ") are assigned. 2. Arrangement according to claim 1, characterized in that the branched parts (1 ") of the transistor gates (1) are arranged mutually on both sides of the active areas (2). 3. Arrangement according to claim 1 and 2, characterized in that in the η-conducting and pleitenden active areas, the branched parts (1 ") of the transistor gates (1) are each arranged opposite one another. 4. Arrangement according to claim 1, characterized in that the contacting points (3) of the branched parts (1 ") adjacent parts of the respective following transistor gates (1) in the direction of the branched parts (1") are arranged offset away.