DE3339985A1 - Circuit arrangement for counting 1 allocations in (0,1) vectors - Google Patents

Circuit arrangement for counting 1 allocations in (0,1) vectors

Info

Publication number
DE3339985A1
DE3339985A1 DE19833339985 DE3339985A DE3339985A1 DE 3339985 A1 DE3339985 A1 DE 3339985A1 DE 19833339985 DE19833339985 DE 19833339985 DE 3339985 A DE3339985 A DE 3339985A DE 3339985 A1 DE3339985 A1 DE 3339985A1
Authority
DE
Germany
Prior art keywords
outputs
transistors
basic
counting
connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19833339985
Other languages
German (de)
Inventor
Peter Fuchs
Klaus Mueller-Glaser
Dieter Schuett
Wolfgang Wach
Thomas Canzler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19833339985 priority Critical patent/DE3339985A1/en
Publication of DE3339985A1 publication Critical patent/DE3339985A1/en
Application status is Ceased legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices
    • H03K17/687Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices using field-effect transistors
    • H03K17/693Switching arrangements with several input- or output-terminals
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14Conversion to or from non-weighted codes
    • H03M7/20Conversion to or from n-out-of-m codes
    • H03M7/22Conversion to or from n-out-of-m codes to or from one-out-of-m codes

Abstract

The invention relates to a circuit arrangement which can be integrated and consists of MOS transistors for counting 1 allocations in (0,1) vectors having n components. The counting circuit contains a network of basic cells (Gix) which are arranged in the form of a branching tree structure having rows and columns, the first row having one basic cell (G11), the second cell having two basic cells (G21, G22) and so on. Each basic cell consists of two transistors (Tix1, Tix2) which are controlled in antiphase and whose drain electrodes are connected to one another and form a switch input. The source electrodes of the transistors (Tix1, Tix2) form separate switch outputs. The switch outputs of the basic cells (Gn1 to Gn,n) of the last row are connected to the outputs (A1 to An+1) of the counting circuit. Depending on the 1-allocation which is present in each case, the drain voltage (VDD) which is applied to the switch input of the basic cell (G11) of the first row via a load transistor (TL) is switched through to one of the outputs (A1 to An+1) as a logic "1". All the other outputs are unambiguously connected to the source voltage (VSS) with the aid of further transistors (Ti13, Ti, i+1) which are controlled corresponding to the 1 allocation. <IMAGE>
DE19833339985 1983-11-04 1983-11-04 Circuit arrangement for counting 1 allocations in (0,1) vectors Ceased DE3339985A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19833339985 DE3339985A1 (en) 1983-11-04 1983-11-04 Circuit arrangement for counting 1 allocations in (0,1) vectors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833339985 DE3339985A1 (en) 1983-11-04 1983-11-04 Circuit arrangement for counting 1 allocations in (0,1) vectors

Publications (1)

Publication Number Publication Date
DE3339985A1 true DE3339985A1 (en) 1985-05-23

Family

ID=6213508

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833339985 Ceased DE3339985A1 (en) 1983-11-04 1983-11-04 Circuit arrangement for counting 1 allocations in (0,1) vectors

Country Status (1)

Country Link
DE (1) DE3339985A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0264046A1 (en) * 1986-10-07 1988-04-20 Siemens Aktiengesellschaft Switching device for broad-band signals
US4944009A (en) * 1988-02-25 1990-07-24 Massachusetts Institute Of Technology Pseudo-random sequence generator
US5257282A (en) * 1984-06-28 1993-10-26 Unisys Corporation High speed code sequence generator
WO2012038736A1 (en) * 2010-09-20 2012-03-29 Novelda As Continuous time counter
US9030243B2 (en) 2010-09-20 2015-05-12 Novelda As Pulse generator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NICHTS-ERMITTELT *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5257282A (en) * 1984-06-28 1993-10-26 Unisys Corporation High speed code sequence generator
EP0264046A1 (en) * 1986-10-07 1988-04-20 Siemens Aktiengesellschaft Switching device for broad-band signals
US4944009A (en) * 1988-02-25 1990-07-24 Massachusetts Institute Of Technology Pseudo-random sequence generator
WO2012038736A1 (en) * 2010-09-20 2012-03-29 Novelda As Continuous time counter
US8941431B2 (en) 2010-09-20 2015-01-27 Novelda As Continuous time cross-correlator
US9030243B2 (en) 2010-09-20 2015-05-12 Novelda As Pulse generator
US9077326B2 (en) 2010-09-20 2015-07-07 Novelda As Continuous time counter
US9337819B2 (en) 2010-09-20 2016-05-10 Novelda As Programmable delay unit

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Legal Events

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OP8 Request for examination as to paragraph 44 patent law
8131 Rejection