DD266719A3 - PROGRAM CONTROL ARRANGEMENT FOR CONTROLLING MACHINES AND PROCESSES - Google Patents

Abstract

The invention includes a program control arrangement for controlling machines and processes and relates to the field of electrical control technology. The aim of the invention is to achieve a wide range of application for electrical program control arrangements with minimal effort. The invention solves the problem of providing a program control arrangement with a processing unit containing a plurality of processors, wherein each of these processors enables an optimal realization of control programs with different operations and different information width of the information to be processed. The essence of the invention is that a processing unit and a two-port memory group are connected via input / output channels to a special processor bus and a standard processor bus. The processing unit contains a standard processor used as a word processor and a special processor used as a bit processor. The Zweitorspeichergruppe is composed of a control program memory and a data and image memory. At the same time, peripheral and memory modules connected to the control object are connected to the standard processor via further input / output channels. The best illustrated in Fig. 1 invention can be suitably used for machine and process control arrangements. Fig. 1

Description

719

Title of the invention

Program control arrangement for controlling machines and processes

Field of application of the invention

The invention relates to the field of electrical control technology and its application is possible and expedient for machine and process control devices.

Characteristic of the known technical solutions

The control technology realization of complex control tasks usually requires the solution of different control functions or control algorithms characterized by typical operations. In addition to the acquisition, processing and provision of pure binary information, whereby the required binary algorithms are realized, is the

Acquisition and processing of multi-bit information / as well as converted to digital values analog information to perform by means of pre-oriented algorithms for many control problems.

An optimal implementation of the control algorithms in terms of time and storage space requirement is achieved when the implementation of these processing units used in their operation or command spectrum are adapted to the operating algorithm occurring in the algorithms, at least the dominant operations.

From DE-OS 25 22 343; G 05 D 19/00, an arrangement for controlling and / or regulating process flows is known, in which processors, which receive data of different information content from peripheral devices, process by means of a program and send to peripheral devices which are interconnected via a program memory are. In this program memory is stored the deficit associated with the processors existing program for the procedure to which a coordinator gives the processors sequential access. There is a clear separation between the two processors in terms of programming, and they can work largely independently of one another over time, whereby the two processors are coupled exclusively via the program memory. A particularly advantageous embodiment is provided by arranging a word processor and a bit processor, wherein the word processor only receives, processes and transmits data having a content information of several bits (words) from peripheral devices and the bit processor only data with an information content of 1 bit of peripheral devices receives, processes and transmits to peripheral devices. For both processors are in the program memory both word and

"Bit instructions may be accommodated either independently of the order of execution or in separate memory areas." "There may also be only tags for particular subroutines stored in other memories associated with each processor." Of the processors, there is always one access to the memory ,

A disadvantage of this arrangement is that the addressing of Steuerprogrammspeichera done exclusively with the help of the word processor and in this way the word processor can not be used for the realization of other program steps. The bit processor alone represents a processing unit for selected commands and has no direct access to the control program memory.

Furthermore, separate memories must be provided for each processor for storing the information processable by the processors, and the peripheral modules are processor-related and the respective processor busses to be connected. A special coordinator is required as a command folder.

Object of the invention

It is the object of the invention to achieve a broad field of application for electrical program control arrangements with minimal effort.

Explanation of the essence of the invention

The invention achieves the object, a program control device for controlling machines and processes of a processing unit containing a plurality of processors

Each of these processors allows optimal implementation of control programs with different operations and different information width of the information to be processed.

The essence of the invention is that, as a central processing unit, a processing unit and a two-port memory group are connected via input / output channel oils to a special processor bus and a standard processor bus. The processing unit used therein includes a standard processor used in tls word processor and a special processor used as a bit processor, and the two-port memory group is composed of a control program memory and a map and image memory. At the same time, peripheral modules and memory modules connected to the control object are connected to the standard processor bus via further input / output channels. From the special processor, which is coupled to the special processor bus through the second input / output channel, there is a connection * to the standard processor via a seventh input / output channel, a coupling unit, an eighth and a first input / output corner. The seventh input / output channel includes a data and control line, a control signal line and a call signal line, wherein a call unit is connected to the control signal line and on the call signal line. From this polling unit, a gated control signal line leads to word processor ports of the control program and data and image memories, both coupled via the third and fourth input / output channels to both the standard processor and the special processor bus.

An advantageous extension of the arrangement is by Einsat? reached a second Spezialprozeesors in the processing unit. Furthermore, via input / output channel oils, a first two-port memory group to a first special processor bus and a second two-port memory group to a second

C * ns

Special process orbital connected, both the two-port memory groups are also coupled via input / output channels to the standard processor. The two special processors have more than seventeenth input / output channels, a first and second coupling unit, eighth input / output channels as well as the first input / output channel, a connection to the standard processor,

At the outputs of the drive units, gate control signal lines lead to the word processor ports, to the data width switching units, and to the special processor ports of the control program and data and image memories connected to the standard processor bus via I / O channels.

A further favorable simplification of the arrangement results from the use of only a single unit bus instead of the bus allocated separately to each processor. A central processing unit is a processing unit with a standard and a special processor and a storage group with a control program and a data and image memory via input / output channels connected to the unit bus. From the special processor, which is coupled to the unit bus through an output unitary twin gate and an I / O cone, there is a connection to the standard processor via the seventh input / output channel, the coupling unit and the eighth input / output channel is also connected by an output side existing unit double gate and an input / output channel to the unit bus.

Further, from the calling unit, a gate control signal line leads directly to the unit twin gates, and via the unit line gn, the byte width switching units of the control program and the data and image memories both connected to the unit bus via input / output channels.

71 $ 6

Aueführungsbeispiel

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawing show:

Fig. 1: dns Dachachaltbild the central unit of the electrical program control arrangement

Fig. 2: a Dlockschaltbild the extension of the arrangement

3 shows an arrangement with a common bus

In Fig. 1, the Dlockschaltbild an electrical Programineteueranordnung is shown for controlling machines and processes, which includes a plurality of processors and interfaces. On a standard processor bus WSD and on a special processor bus DSD are via input / Ausoabekanäle EAK 1; EAK 2; EAK 3; EAK 4 a processing unit VE and a Zweitorspeichergruppe ZSG nngschlossen, the first input / output channel EAK 1 the standard processor bus WSD with a word processor used as the standard processor WSP, the second input / output channel EAK 2 the special processor bus DSD with a dedicated processor DSP used as üitprozessor, the third input / output channel EAK 3 the state processor bus WSB with a control program and a data and image memory PLC; DAS and the fourth input / output channel EAK 4 connect the special processor orbit DSD to the control program data and the data and image memory DAS, via fifth and sixth input / output channels EAK 5; EAKs 6 are connected to the state processor bank WSB with peripheral devices PD connected to the control object SO and additional memory board modules SB, to which only the standard processor WSP has access. In the processing unit VE the Sfjezialprozessor DSP via a seventh input / output channel EAK 7, a coupling unit · KE and an eighth input / output channel EAK 8, which may be identical to the standard processor bus WSD, connected to the standard processor WSP.

The seventh input / output channel EAK 7 consists of a Datenund control line DSL for access and Datontransport the standard processor WSP to Programiii cooler of the special processor BSP, a control signal STL to the state setting of the special processor OSP dbrch the Stanclardprozessor IVSP with respect to START / STOP and a call signalloituny ASL to call the standard processor IVSP, wherein the control signal and the call signal line STL; ASL a Aufrufeinhei I ARE is connected, to transfer the Torsteuersignales TSS performs a line TSp before the call to the unit ARE Standurdprozessorkoppeltoren WPT 1; WPT to Spczlol processor couplers DPT 1; f3PT 2 and to the data mixing units UES; DAS, which are connected via the third and fourth input / output channel EAK 3, EAK 4 both with i.em StondardprozessorbUB WSH and with the Spozialprozessorbus ÜSD. 'Jie Koppeleinhci t KE images, an addressable input / output port for the standard processor WSP and is also designed so that when calling the Starulardprozessors WSP on the call arbitration line ASK an Interruptanforderuncjssignal as part of the eighth input / output channel EAK 8 for the standard processor WSP generated.

FIG. 2 shows a block diagram of a possibility for expanding the program control arrangement. The processing unit VE contains for this purpose a first and second special purpose processor BSP 1; BSP 2, on the one hand via separate input / output channels EAK 21; EAK 22 with a first and a second Spe.iialprozessorbus BSB 1; BOD 2 and on the other hand via single-dose dispenser EAK 81; EAK 82 and a first and second coupling unit KE 1; KE 2 are connected to the first input / output channel EAK 1. To the control signal u.id the call lines ASL 1; ASL 2; STL 1; STL 2 are first and second calling units ARE 1; ARE 2 connected. Furthermore, in the expanded arrangement, a first and second Zwsitorspeichergruppe ZSG 1; ZSG 2 available, which via input / output channels EAK 31; EAK 32; EAK 41; EAK 42 with the standard

dardprozessorbua WSB and the first and second special procedure bus DSD 1; DSD 2 are coupled. Of the call units ARE 1; ARE 2 result in transmitting the gate control signals TSS 1; TSS 2 lines to the standard processor couplers WPT 11; IVPT 12; IVPT 21; WPT 22 to the special processor couplers BPT 11; DPT 12; I) PT 21; OPT 22 and data width conversion units UES 1; UED 1; UES 2; UED 2 of the first and second two-port memory group ZSG 1; ZSG 2.

Fig. 3 shows a solution variant in which only a single unit bus ED is used. Connected directly to this unit bus ED are the call unit ARE, the standard processor WSP and the special processor DSP, the connection of the processors to the dome via unit duplex gates EDT 1; EOT 2 takes place. Furthermore, a memory group SG is arranged, whose control program memory PLC and data and image memory DAS are connected to the unit bus ED, via the unit bus ED are in the control program and data and image memory PLC; THE contained data width switching units UES; UED connected to the call unit ARE.

The arrangement works in the following way:

With the connection or the start of the arrangement, a basic state of the arrangement is initialized via a switch-on of the standard processor WSP, which, among other things, the special processor DSP via the control signal line STL with STOP and thus determines the gate control signal TSS so that üb, he erete and second standard processor coupler WPT 1; WPT \ 2 and the first and second special processor ports DPT 1; DPT 2 the Zweitorspeichergruppe ZSG the standard processor WSP is assigned. The formation of the gate control signal TSS takes place simultaneously via the state of the call signals AS and the control signals ST. If, for example, the gate control ·

signal TSS goes high then the standard processor ports are WPT 1; WPT 2 switched to continuity and the special processor double ports DPT 1; BPT 2 high impedance. In this state, the standard processor WSP has access to the dual port memory group ZSG and the special purpose processor DSP is disconnected. If the gate control signal TSS is then in the "low" state, then the conditions at the coupling gates are reversed and the special purpose processor SP has access to the second gate storage group ZSG. In parallel with the help of the gate control signal TSS and the Datenbreiteumscheinheiten UES; UED in the Zweitorspeichergruppe ZSG driven and adjusted the memory organization of the Datonbreite of the processor, which has access to the Zweitorspeichergruppe ZSG in this time. After carrying out this switching of the central unit from word-oriented to bit-oriented by changing the access of the individual processors to the Zweitorspeichergruppe ZSG, the standard processor WSP in its data width the data and image memory DAS with current information of the control object SO filler ¹ and then on the data and control line TSL specify the special processor DSP an initial address for processing the Steuerprograinmes stored in the control program memory. With an ST ^A RT of the special processor DSP triggered via the control design line STL and the assignment of the control program and the data and image memory SPS associated therewith via the gate control signal TSS; THAT becomes the special processor, the special processor DSP begins with the implementation of the control program. In this state, at the same time the Stendardprozessor WSP in conjunction with its associated memory module SD and its associated peripheral modules PD parallel to the active special processor DSP even implement additional programs or tasks. With the decoding of a supplemental instruction which, as a result, in the control program memory PLC program displays programs or instructions which are effectively realizable by the standard processor WSP, the special purpose processor DSP goes into HALT and over

Call signal line ASL and the coupling unit KE is a call of Stan'dardprozessors WSP in terms of an interrupt request. In parallel, via the gate control line TSL, the state control of the standard processor couplers WPT 1; WPT 2 and the special processor double ports OPT I; BPT 2 and by means of the data width Unischalteinheiten UES; UED the switching of the memory organization of the Zweitorspeichergrupp-5 ZSG performed so that it is separated from the special processor bus BSD and thus from the special processor BSP and the standard processor WSP according to its data width access to the Zweitorspeichergruppe ZSG has. With the interrupt request via the polling line ASL, the standard processor WSP interrupts its own program, lifts the current address of the program control of the control program memory via the data and control DSL and adopts the processing of the program complexes assigned to it or instructions of the control program memory SPS until the next additional command , In this regime, the control routine dec control program memory SPSj containing both instructions for the standard processor WSP and instructions for the special processor BSP, according to the control problem to be solved, is interleaved and sequentially executed by the standard and special processors WSP; BSP implemented. After the complete execution of the program, which is characterized by an instruction such as program end or input / output routine assigned to the master processor WSP, the standard processor WSP makes an information exchange with the control object SO via the peripheral modules PB, and the cycle is now started. The peripheral modules may also include independent functional modules, such as counters, controller modules and connection controllers for coupling to computers and / or other automation devices. The communication of the standard processor WSP with the peripheral modules PB can be carried out both by cyclic polling and on an interrupt basis. Even more effectively, the functional sequence can be designed by the expansion option of this basic arrangement shown in FIG

Mis the combination of the standard processor WSP with two special processors DSP 1, DSP 2 consists. The special processors DSP I ₁ DSP 2 can be of the same type or designed for different algorithms. The special processors DSP 1, DSP 2 only the program complexes are removed, which are more effectively realized by the standard processor WSP, special processor DSP 1, DSP 2 are separated a Zweitorspeichergruppe ZSG 1, ZSG 2 with the associated control memories PLC 1, PLC 2 and data and Image memory DAS 2, associated with 2, to which both the standard processor WSP via the standard processor bus WSD and the special processors DSP 1, DSP 2 have access via the associated special processor busses DSD 1, DSD 2. The control of the memory allocation via the coupling ports IVPT 11, WPT 12, WPT 21, WPT 22 and DPT 11, DPT 12, DPT 21, DPT 22 and dns interaction of the standard processor WSP with special processors DSP 1, DSP 2 can analogously as for Basic arrangement can be performed described, wherein advantageously the call of the standard processor WSP on the call signal line ASL 1, ASL 2 should be made on an interrupt basis by priority control.

In the variant of the basic arrangement shown in FIG. 3, both the access of the standard processor WSP and of the special processor door DSP to the storage group SG are effected via a single unit bus ED. The control program memory PLC also contains such algorithm complexes which are processed alternately by the standard processor WSP and by the special processor DSP. The assignment of the memory group SG via the unit bus ED to the word and special processor WSP, DSP is controlled by the output side in the processors existing unit bus EDT 1, EDT 2. Parallel to this, the adjustment of the storage organizers to the width of the Dots WSP, DSP using the Torsteuersignalleitung TSL done via the unit bus ED.

By alternately executing the control program in a standard processor and a special processor, optimal implementation of different algorithms or instructions is possible. It is particularly advantageous that a joint storage of the process-image information and the intermediate and result information obtained in the course of the control program implementation is carried out and each processor has full access to this information, the information exchange being the peripheral modules with the data width of the standard processor and only this is done by knn. A subdivision and assignment of peripheral modules and thus the external information zti the individual processors is not required. Another significant advantage lies in the possible parallel work of both processors. Due to the autonomous, possible without assistance of the standard processor implementation of assigned Programmkoir.plexen in SPezialprozessor the standard processor can take over additional tasks in the form of background programs, with an interruption must be made only with necessary activities on jointly implemented control program.

Claims (3)

ZCC Ϊ13 invention claim 1, electrical program control arrangement for controlling multi-processor and multi-processor machines and processes, comprising as a basic equipment at least one bit-oriented and one word-processor coupled to a word memory, and binary input to a bus associated with the bit processor as a bin / - / Auegabeeinheiten and memory units and connected to a running as a digital interface to the word processor bus line via a coordinator of the bit processor, a program memory, a standard periphery, a process periphery and an additional computer are connected, characterized in that as a central unit one of a special processor used as a bit processor (BSP) and a standard processor (WSP) processing unit 'VE' used as a word processor and a two-port memory constructed of a control program memory (SPS) and a data and image memory (DAS) group (ZSG) via input / output channels (EAK 1; EAK 2; EAK 3; EAK 4) are connected to a special process sorbus (BSB) and a standard processor bus (WSB), wherein the standard processor bus (WSB) simultaneously has additional input / output channels (EAK 5, EAK 6) with peripheral assemblies and memory modules (SB) connected to the control object SO. are unconnected, and the special processor (BSP) connected by the second input / output channel (EAK 2) to the special processor bus (BSB) via one of a data and control line (DSL), a control signal line (STL) and a polling signal line (ASL) existing seventh input / output channel (EAK 7) on the one hand via a coupling unit (KE), an eighth input / output channel (EAK 8) and the first input / output channel (EAK 1) a connection to the standard processor (WSP) and on the other hand one with the control signal line (STL) and the ZCG Ψ19 14 Calling Unit (ASL) is controlled by an out-going Torsteuersignalleitting (TSL) to Word Processor Doors (WPT1; WPT2), Data Width Switching Units (UES) and Special Processor Couplers (BPT1; BPT2) the Control Program Memory (SPS) and the Data and image memories (DAS) are connected, both coupled via the third and fourth in / out channel (EAK3; EAK4) and also to the standard processor (WSB) as well as the special processor (BSB). 2. Electrical program control arrangement for controlling machines and processes according to item 1, characterized in that ale central unit one out of a Ereten Spezialprozeeeor (BSPL) and a second Spezialprozeeeor (BSP2) and a standard processor (WSP) existing processing unit (VE) and a first and Second ae jeweile a control program memory (SPSl; SPS?) And a data and image memory (DASl; DAS2) constructed two repository group (ZSGl; ZSG2) on in / outfeed channels (EAKl; EAK21; EAK22; EAK31; EAK32; EAK41; EAK42) with a first and second special processor (BSB1; BSB2) and a standard processor (WSB) are connected, whereby the first and second special processors (2) connected by the second input / output channels (EAK21; EAK22) to the first and second special processor buses (BSB1; BSB2) BSPL; BSP2) via a data and control line (DSL1; DSL2), a control line (STL1; STL2) and a polling signal line (ASL1; ASL2 ) existing seventh entry / exit channels (EAK71; EAK72) einereeite on a erete and second coupling unit (KEl; KE2), on eighth input / output duct oils (EAK81; EAK82) and the first input / output channel (EAKl) a connection to the standard processor (WSP) is present, as well as on the other hand first and second Calling unit (ARE 1; ARE 2) connected to the associated control signal lines (STL 1; STL 2) and call signal lines (ASL 1; AS 2) by output Torsteuerlagelteltung (TSL 1; TSL 2) to the word processor ports (WPT 11; WPT 12; WPT 21; WPT 22), the data width switch units (UES 1, UED 1, UES 2, UED 2), and the special processor doubles (BPT 11, BPT 12, BPT 21, BPT 22) the control program memories (PLC 1, PLC 2) and data and image memories (DAS 1, DAS 2) connected to both the standard processor bus (BSB 1, BS3 2) via third and fourth input / output channels (EAK 31; EAK 32; EAK 41; EAK 42). 3. Electrical Program Control Arrangement for Controlling Machines and Processes According to Items 1 and 2, characterized in that a central processing unit is a processing unit (VE) consisting of a special processor (BSP) and a standard processor (WSP) and one of a control program. and a data and image memory (PLC, DAS) constructed storage group (SG) via input / output channels (EAK 91, EAK 92, EAK 93, EAK 94) are connected to a unit bus (EB), of which by a Output channel (EAK 92) connected to the unit bus (EB) and equipped with a unit bus double gate (EBT 2) special processor (BSP) of the seventh input / output channel (EAK 7) on the one hand via the coupling unit (KE) and the eighth input / output channel (EAK 8) to the standard bit processor (EBT 1) provided standard processor (WSP), as well as on the other hand connected to the control signal line (STL) and the call signal line (ASL) call unit (ARE) by the output vorha NEN gate control signal line (TSL) directly to the Einheitsbuskoppeltore (EBT 1; EBT 2) and via the unit bus (EB) to the data width switching units (UES, UED) of the control unit to tr j Program memory (PLC) and the data and image memory (DAS) are connected, both via input / output ports (EAK 93, EAK 94;) are coupled to the unit bus (ED). - For this 3 sheet drawing -