DD239686A1 - PROCESS FOR EDGE METALLIZATION OF CHIP RESISTANT - Google Patents

Abstract

The invention relates to a method for edge metallization of chip resistors, which are used as a component in electrical engineering / electronics. The aim of the invention is to provide a method with which it is possible to provide in a rational way in addition to noble metal and low-precious and precious metal chip resistors in association with a galvanic and a chemically reductive deposited nickel layer as electrical Anschlußflaeche. The invention has for its object to realize a Kantenmetallisierung of Chipwiderstaenden in Duennschicht- or Dickschichtausfuehrung without a change in the characteristic properties of the resistive material used in the process occurs. The object is achieved according to the invention in that until the technological step edge metallization a sequence of specific layers is applied, which ensures both the later Funktionsfaehigkeit the chips, as well as a partial deposition of nickel on a galvanic and chemical-reductive way to the formation of terminal surfaces allows.

Description

For this 3 pages drawings

Field of application of the invention

The invention relates to the realization of solderable Anschlußfiächen chip resistors.

Chip resistors are needed in electrical engineering / electronics in order to be able to use significantly cheaper placement technologies in the production of electronic assemblies.

Characteristic of the known technical solutions

Chip resistors can be categorized into two categories according to the prior art regarding the resistive layer fabrication technology:

- Thin-film chip resistors

- thick-film chip resistors

In the manufacture of these two types of chip resistors, there is basically the complicated problem of realizing the electrical pads. These electrical pads must be suitably carried out so that they the automatic assembly and electrical Ankontaktierung e.g. Allow soldering on wiring substrates. In order to realize this need, different ways will be described according to the prior art. The vapor deposition of the contact layers, the application of foil and the use of pastes containing precious metals are known (DE 3023133, DE 3027159, DE 3027122, DE 3201434, DE 3104419, DE 3117973, DE 3148778, DE 3122612, DE 2645783).

From the prior art is further derivable that the realization of the electrical connections require high mechanical precision in the production of chip resistors in the individual process steps and often also a relatively high temperature effect, usually exceeds 500 ⁰ C when using paste systems for contacting is.

These extreme temperature loads influence the resistance structures in an uncontrolled and thus disadvantageous manner (DE 1471474, DE 3139750, WO 82/00233).

In the application WP DD 224993 a method is proposed, which has a wet chemical working technique for edge metallization, the chemical-reductive nickel plating.

The disadvantage here is that the intended areas for metallization of chip resistors defined pretreated, i.

must be germinated.

This method further has the disadvantage that it is only applicable for thick-film chip resistors.

Aim of the Foundation

The aim of the invention is to provide a method which is equally suitable for edge metallization of noble metal-containing, low-noble metal and noble metal-free thick and thin-film chip resistors.

At the same time, this method should provide more technologically more favorable conditions for mass production of chip resistors, in that the temperature load of the chips in the bond during the edge metallization process is as low as possible. This must be considered as a prerequisite that the individual chips can still be balanced in the association. In addition, the solubility of the individual chip resistors should be improved.

Explanation of the essence of the invention

The object of the invention is to provide a method for the realization of electrical pads on chip resistors by edge metallization, which is characterized in that it operates at temperatures below 30O ⁰ C and both precious metal, low precious metal and precious metal-free thin-film chip resistors as well as corresponding thick-film resistors is applicable.

In addition, the soldering safety of the individual chip resistors is to be improved by an appropriate layer structure of the metallized pads.

By creating more favorable procedural conditions, the thermal stress (T <300 ⁰ C) of the already applied to the dialectical substrates resistance layers should be kept so low that property changes of the resistance materials can be largely excluded by process influences.

The methods previously used for edge metallizing chip resistors have the following disadvantages.

The vapor deposition of the contact layers causes a relatively high thermal load of the already applied resistive layers. Likewise, the necessary thermal treatment works when using paste systems.

The use of foil impairs the soldering accuracy.

Erfir.dungsgemäß the Aisfgaba is achieved by the fact that up to the technological step edge metallization a 2ur production of Kanienmetallisierung the chip resistors needed Strulcturierte Leitbasisschicht and the material for the Widerstandsschichi the individual resistors in a programmed manner, be applied to a large, planar and dielectric substrate. In addition, the resistors prepared in this way can still be provided with a covering layer against possible environmental influences. Thus, the coated dielectric substrate, a carrier of many individual chip resistors, is to be regarded as a technologically conditioned intermediate result. The edge metallization is prepared by the dielectric substrate with the previously resulting layers by screen printing with a polymer-based temperature-resistant coating layer z. B. polyimide lacquer layer, as an additional protective lacquer layer and then provided on both sides with a Galvaaoiackschicht.

The Galvanolackschicht is applied only where no galvanic or chemical-reductive metallization should take place later.

Taking advantage of the specific properties of the conductive base layer, a per se known galvanic nickel plating of the exposed, d. H. parts of the conductive base layer not covered by the polyimide varnish layer are made. After the galvanic plating step, the dielectric substrates are separated into elongated strips. The next step is the side surface metallization as a chemically-reductive nickel plating. The chemically reductive nickel plating of all surfaces not covered with the galvanol lacquer layer thus ensures the total edge metallization of the chip resistors in the Stroifenverband either in frame technology or as a bulk material variant. The layer sequence of galvanically and chemically-reductively deposited nickel produces particularly compact, the Leitbasisschicht safely contacting electrical pads on the individual chips. These pads form the basis for being able to realize very good solderable chip resistances. After the edge metallization process, the galvanol lacquer layer is removed with suitable solvents in the bulk material process and the coated dielectric substrate strips are processed into solderable individual chip resistors.

Ausführungsbeispie!

The invention will be explained in more detail with reference to a drawing, which relates to the Katten metallization of thick-film chip resistors

 Show it:

Figure 1: Substrate

Figure 2: detail of Figure 1 with layers 1 to 4 Rgur 3: detail of Figure 1 with layers 1 to 6 Figure 4: substrate with layers 1 to 6 (longitudinal section) Figure 5: chip resistance

On a dielectric substrate! from Ai ₂ O ₃ ceramic in Plattenforrn an Ag / Pd paste is applied by screen printing and baked. This results in a strip-like structured trained Leitbasisschicht 2 on the dielectric substrate 1. On this firmly adhering Leitbasisschicht 2, the material for the resistive layer 3 in paste form also screen printed and baked, so that a technologically conditioned intermediate result according to Figure 1. The resistive layer 3 is provided with a covering layer 4, which later serves as the barge of the chips from environmental influences. The dielectric substrate 1 thus coated is thus the carrier of many "single-chip resistors", the conductive base layer 2 being the only layer having a complex electrical conductivity, which is necessary for the electroplating process which follows later. after the processing stage - apply cover layer 4 -. In order to protect the covering layer 4 during the later edge metallization process, a polyimide lacquer layer 5 is expediently applied, as shown in FIG. 3, which completely covers the covering layer 4 and thus supports it against acids and alkalis during the metallization process. For the edge metallization process, a layer 6 of physically drying galvanol lacquer is further applied to the front and rear sides of the dielectric substrate 1. This GalvanolackschichtG is applied so that the polyimide lacquer layer 5 is not completely overlapped in the x direction. In the following operation, the exposed part of the Leitbasisschicht 2 is galvanically coated with about 5 / in the nickel. Basically, after the galvanic coating, the requirement is to separate the electrical substrate 1 in the y direction according to FIG. 1 into strips as further preparation for edge metallization.

The chemical-reductive edge metallization presupposes that in any case a galvanol lacquer layer 6 according to FIGS. 3 and 4 is located on the individual dielectric substrate strips. In this process step of edge metallization, the strips are cleaned in an approximately 1% NaOH solution at a temperature of less than 70 ° C and rinsed extensively. For the chemical-reductive metallization of all not covered with the Galvanolackschicht 6 surfaces pre-treatment of the surface by sensitization and activation is required.

-3- 239 638

awareness;

ι emperatur: Time: Activate:

Temperature:

Time :

metallization

pH: T:

10 g / i ml / 1 SnC 2 COOH 30 ml / 1 g / i ^CH 3 COOH COOMa. 3 20 ml / 1 ml GH. _{T <} -CH-CH-. ⁰ C OH 920 ml :. 10 of t. H ₂ O 25 ⁰ C g / i O ₄ . 7H ₂ O ma> C 10 g / i min » -CH-COOH 0.5 g / l PdCl ₂ OH 15 g / l CH ₃ -CHp-COOH 15 g / i CH _{3 2} P0 ~. H ₂ O 921 - 5 H ₂ O NaOH 25 ° c Max , 10 min 20 NiS: 30 CH ₇ ό 3 CH ₃ . 15 MaH. 4.3 5 with 74 Max min

There is a brief rinse behind each working session. After this process of Kantenmetalüsierung the Galvonolackschicht 6 is washed off by means of carbon tetrachloride or trichlorethylene and dried the individual strips. In FIG. 5, such a chip resistance is shown schematically in section in the longitudinal direction, in which the applied galvanic nickel layer 7 and the chemically reductive nickel layer 8 are shown correspondingly.

In the further processing of the chip resistors, it proves to be particularly advantageous that the adhesion of the chemically reductively deposited nickel layer 8 with about SOO Ncrn " ^{2 is} extremely high.

Claims (1)

-1 - Ζ'όϋ ööb Claim: Process for the edge metallization of chip resistors in thin or thick film design, in which a conductive base layer (2), a resistance layer (3) and a cover layer (4) is applied as a structured layer sequence on a dielectric substrate (1), characterized in that the Covering layer (4) and the still exposed surfaces of the conductive base layer (2), which is the only one of the layers structured in stripes and has a complex electrical conductivity, by means of a printing process a precisely structured polyimide lacquer layer (E>) and on these and on the back the dielectric substrate (I) a likewise structured, physiüch-troeknende Galvanolackschich'c (6) is applied so that the Leitbasisschicht (2) partially electroplated and the resulting after a separation process Subs'eratstreifen are partially chemically-reductively nickel-plated, wherein the chemically Reductively deposited ene, on the galvanically deposited nickel layer overlaps.