DD211655A1 - CIRCUIT ARRANGEMENT FOR COMPARING SIMILAR SOURCE INFORMATION WITH FAULT EVALUATION AND TOLERANCE - Google Patents

Abstract

The invention relates to a circuit arrangement for comparing similar source information with error evaluation and tolerancing with the systems, especially for high reliability and safety requirements, can be realized. The aim of the circuit arrangement according to the invention is to ensure secure information processing and, moreover, to increase the reliability (availability) of the information processing. According to the invention, the signals of n sources are checked for agreement according to the "m of n" principle (2 <= m = <-n), errors occurring being localized and displayed and certain error classes being tolerated. In particular, this circuit arrangement is suitable for use in conjunction with computers.

Description

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Circuit arrangement for comparing similar source information with error evaluation and tolerance

Field of application of the invention

The invention relates to a circuit arrangement with the systems j can be realized especially for high reliability and Sicherheitaanforderungen »Such a circuit arrangement is everywhere · be used where similar measured values or other similar signals in digital form von- η different sources after the" m be checked for compliance by n ^! 'principle.

It is characterized by the known technical solutions

Known iat a circuit arrangement (DS-OS 22 02 231) for detecting and isolating faulty system units of a program-controlled processing system in which the individual system units to increase the reliability are multiple. »Each processing unit is associated with a comparator, each of the maximum of 2 possible input data checks for coincidence and outputs error signals corresponding to the two non-basic, transmitting processing units in its comparison. "The following majority logic circuit realizes the switching of the majority signal *

Such a comparator is unable to directly locate the erroneously sending processing unit.

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Only an additional device, which in turn is assigned to each processing unit, enables the display of the incorrectly transmitting processing unit via the evaluation of the incoming error signals. Coupling three times with dual system units requires another device within each processing unit that allowed for error localization within the triple system

Furthermore, a circuit arrangement for the comparison of the output data of two data processing systems (DS-AS 27 29 362) is known * If there is a difference in the data to be compared, the two-channel data processing arrangement is switched off and thus the output of erroneous information prevented, Such a circuit arrangement Although it ensures the desired safety, it has the disadvantage that the required availability for applications with extremely high requirements, eg for nuclear power plants, railway safety technology, is not achieved. In addition, when comparing information (addresses and data) in parallel, the cost of implementing the specified comparison is quite considerable.

Aim of the invention;

The aim of the circuit arrangement according to the invention is to ensure reliable information processing and, moreover, to increase the reliability (availability) of the information processing.

Explanation of the essence of the invention

The invention has for its object to develop a circuit arrangement, the signals from η sources according to "m of n" principle (2 ^ m ^ n) checks for conformity, locates occurring errors and displays and tolerates certain error classes * According to the invention the task

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in that the selection input S of a comparator, at whose respective inputs 11 to Iq the information of the sources Q1 to Qn to be compared is connected to the output of a first logical OR gate is at the inputs of the first logical OR gate the control signals SV for the comparator on »The ÜT output of the comparator is to the first input of an evaluation, the second input with a" k of η "selection unit and the first input of a second logical OR gate, s.der other Inputs Test signals TS applied, connected, connected The output of the second logical OR gate is linked to the test input T of the comparator * The Ü output of the comparator is connected to the third input of the evaluation unit «The error outputs P1 to Pn of the comparator are on connected to a register whose outputs are connected to the "k of η" selection unit (selection according to active level) u nd the evaluation unit are connected. The reset input R of the register is connected to the output of a third logical OR gate, at whose inputs the Fehlerrücksetzsignsle FR abut, combined »The output information AI of the comparator are applied to the outputs A1 to Aq»

In a further embodiment of the inventive solution, the comparator is formed as Pestwertspeicher, freely programmable logic array or as a multiplexer «The register consists of triggers, which logic gates are connected upstream and the" k of η "- selection unit (selection according to active level) is as an open-collector Gate trained *

The comparator has a test input T, with the help of the functionality of the circuit can be checked without v / eitere connected devices to influence *

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Ausführun ^ SExample:

The invention will be explained in more detail below using an exemplary embodiment.

The enclosed drawing shows:

Pig * 1: Circuit arrangement for comparison more similar

Source information with error evaluation and tolerance; Fig. 2: Circuit arrangement for comparison of 3 times 8-bit

Fdrtern with error evaluation and -tolerierung. At the inputs of the comparator 1 are each to be compared information II to Iq the sources Q1 to Qn (Fig _o 1), According to Fig _e 2, the comparator 1 consists of three read-only memories 1 "1, 1, 2 and 1 * 3 · The read-only memories are programmed so that they are compared according to the "2 out of 3" principle * For the evaluation of the comparison is a register 4, consisting of MBD gates 4.1, 4 * 2, 4 * 3 and D Triggers 4 * 4, 4 ₉ 5 and 4 * 6 provided "Furthermore, the 'evaluation using a' k of η 'selection unit 5> in the example of FIG. 2 from HMD gates 5 * 1, 5» 2, 5 * 3 ^un 3 is an open-collector resistor 5 »4 * the reset inputs R of the D-trigger 4" 4 to 4 »6 are connected to the output of an HMD gate 6 * 1, at whose inputs the error feedback sets signals FR issue*.

The read-only memories 1.1, 1 "2 and 1 * 3 used in FIG. 2 can each be used to compare 3 ^ 3 bits. If the read-only memories have a larger number of inputs, the number of comparable bits per read-only memory is increased accordingly in an 8-bit word of a source of one or more bits falsified _s so the right signals appear at the outputs of the comparator 1 AI yet (Mehrheitssignaie) *. The falsification of the 8-3 bit »word of a source is characterized as single error and tolerated« The single error signals F1, F2, F3 are stored in the D-triggers 4 * 4? 4 * 5 and 4 * 6 are stored and forwarded to an evaluation unit 3.

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- 5 - £ LI | O 4 given the error according to FIG. 2 by means of signal lamps 3 * 1 to 3e6 represents »The partial match signals UT and the match signals Ü are each to the inputs of the NOR gates 1 * 4 and 1« 5 out whose outputs for display with the Signal lamps 3 "1 and 3 * 2 of evaluation unit 3 are connected." Gates 1 * 4 and 1.5 are omitted if only one comparator module is needed for the comparison, in the example only a read-only memory is used. "With the aid of a logic gate 7 in FIG ₉ 2, the NAND gate 7 * 1 ₅ abut example of FIG at whose inputs the test signals TS, the test input T of the comparator 1 is activated. This causes a defined inactive signal to be generated at the outputs AI of the comparator 1, the signals F1 to Fn, Ü and ÜT being determined according to the input assignment. "This makes it possible to check the functionality of the entire circuit arrangement without influencing others connected to this circuit arrangement units * For controlling the read-only memory 1 * 1, 1 * 2 and 1 * 3 is a logical OR gate 2, in the example of FIG. 2, the NAND gate 2 _e 1, at whose inputs the control signals SV for the comparator ",

All output signals of the comparator 1, the register 4 and the "k of η" selection unit 5 can be used for further processing of external devices, Z ₁₉ B * a computer.

Claims (1)

invention claim 1β Circuit arrangement for comparing similar source information with error evaluation and tolerance characterized in that the selection input S of a comparator (1), at whose respective inputs 11 to Iq the information to be compared of the sources Q1 to Qn abut, with the output of a first logical OR Gate (2) is connected, wherein at the inputs of the first logical OR gate (2) the control signals SV for the comparator (1) are applied, the ÜT output of the comparator (1) to the first input of a Ausv / erteeinheit (3 ) Whose second input with a "k of η" selection unit (5) and the first input of a second logical OR gate (7)> at the other inputs test signals TS abut, is connected, connected and the output of the second logical ODBR gate (7) to the T input of the comparator (1) linked, the Ü output of the comparator (1) is connected to the third input of the evaluation unit (3) and di e fault outputs F1 to Pn of the comparator (1) are connected to a register (4) whose outputs are connected to the "k of η" selection unit (5) and the evaluation unit (3), wherein the reset input R of the register (4 ) is connected to the output of a third logical OR gate (6), at whose inputs the error reset signals FR are present, and the output information AI of the comparator (1) is present at the outputs Δ1 to Aq. " 2β Circuit arrangement for comparing similar source information with error evaluation and tolerance according to point 1, marked t .dad urc h ^ that the comparator (1) is designed as a read-only memory, freely programmable logic field or as a multiplexer * / 7 3 »Circuitry sura comparison of similar source information with error evaluation and -tolerierung according to item 1, characterized in that the register (4) consists of triggers, which logic gates are connected upstream» 4. Circuit arrangement for comparing similar Queliinformationen with error evaluation and tolerance according to item 1, characterized in that the "k of η" - selection unit (5) consisted of open-collector gate 5 _β Circuit arrangement for comparing similar source information with error evaluation and tolerance according to item 1, characterized in that a test input T is provided at the comparator (1) « Hierau 2 pages drawings