DD253312A1 - CIRCUIT ARRANGEMENT FOR CHECKING THE TYPE IDENTIFICATION OF ELECTRONIC MODULES - Google Patents

Abstract

The invention relates to a circuit arrangement for controlling the type identification of electronic modules, which can be used in particular everywhere where assemblies of computer configurations are constantly or in the start-up phase with respect to. The type identifier controlled and a blocking of the external access with the wrong module type is to take place. In addition to two decoders for evaluating an address bus split into two parts, the circuit arrangement according to the invention contains a diagnostic decoder, memory access logic for forming internal memory control signals and a memory unit for registering interference and status signals.

Description

Field of application of the invention

The circuit arrangement according to the invention can be used everywhere where assemblies of computer configurations are constantly or in the start-up phase with respect to. The type identifier controlled and a blocking of the external access to be done with the wrong module type.

Characteristic of the known state of the art

In the control of functional units in computational subassemblies, it is known to evaluate a split into two parts bundle of addresses by means of two decoders, only the proper decoding of the two address parts leads to the activation of one or more selection signals for structure-internal control. In this context, it is furthermore known that the one decoder of the first part of the address bundle can block the other decoder if an address identified as faulty is present. This also blocks the structure-internal control, so that no external effects via I / O channels are possible. It is also known that the time sequence of the output signals of both decoders is monitored.

A special circuit arrangement for detecting an assembly of a given computer configuration is not known. A disadvantage of the known arrangements for module diagnosis that in an incorrectly plugged module (type) external access is possible and thereby possibly fault switching operations can occur to the technological process. A detection of the wrong type and an access prevention is not guaranteed.

The object of the invention is to broaden the scope of diagnosis in electronic package configurations and to avoid potential deleterious effects on process control.

Explanation of the essence of the invention

The invention has for its object to develop a circuit arrangement with which the respectively provided type of card assemblies of a particular module configuration can be controlled and with the blocking of external access to card functions with incorrect module type or other present on the card interference is possible , In addition, it should be possible to read the module status even if the external access is blocked. According to the invention, this object is achieved by using two decoders for evaluating a split into two parts address bundle and a memory for the registration of interference and status signals in that a diagnostic decoder which is coupled to the low part of the address bus and generated by the first decoder Card selector signal is generated, a memory selection signal generated at the output, which is guided to a memory with external read / write signals memory access logic. The first output of the memory access logic, which carries a memory write signal, is connected to the reset input and to a first terminal of the data input of the memory unit. The second, a memory read signal leading output is linked to the output enable signal input of the memory unit. A decoder enable signal generated in response to the control of the type identifier in the memory unit is further connected to the enable input of the second decoder associated with the low part of the address bus. For this purpose, a first data signal of the data bus is connected to a second terminal of the data input of the memory unit. For resetting, a second data signal of the data bus is linked to the reset input of the memory unit. Likewise, the memory unit has both a data output representing the respective board status and an output for reporting and registering common failures. Another part of the solution according to the invention relates to the design of the storage unit. For the external control of the type identifier, the memory unit essentially comprises a resettable and decoder enable signal generating status register, a type register and data bus gate controllable by the memory read signal, an optional input gate associated with the status register, an OR Circuit for detecting interference and status signals received in the status register and a controllable gate for writing the first data signal of the data bus into the status register.

In the case of internal checking of the type code, the memory unit according to the invention contains a type comparator which is connected on the input side with data bus lines for inputting the type envisaged according to the configuration as well as lines for setting the type. A comparison signal present at the output of the type comparator is connected to a first information input of the resettable status register. The further structure of the memory unit is identical to that of the memory unit for the external control of the type identifier.

A significant advantage of the circuit arrangement according to the invention is the ability to control the type of card assemblies within a particular assembly configuration internal or external and at the same time to block the external access to card functions in case of wrong type or other, present on the module disturbances. In addition, the current module status can be read even if the external access is disabled.

embodiment

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings show:

1 shows the circuit arrangement according to the invention

2 shows the memory unit according to FIG. 1 for the external control of the type code

3 shows the memory unit according to FIG. 1 for the internal control of the type identifier

4 shows an embodiment of the memory access logic according to FIG. 1.

The circuit arrangement according to the invention for checking the type identification according to FIG. 1 can be part of a diagnostic concept for computer configurations. For this purpose, certain hardware functional units which can be supported by software measures must be provided on each module which is to be included in this control. The present invention relates to such functional units on assemblies. In the diagnostic concept, it is assumed that the type check for the respective module must also be functional during the execution of the user programs.

The circuit arrangement according to FIG. 1 consists of the decoders 1 and 2, the diagnostic decoder 3, the memory access logic 4 and the memory unit 5 and operates as follows:

In known manner, the functional units of a module are addressed, in which by the decoding of the high part H-AB of the address bus AB by means of the decoder 1, the card select signal KSEL for the decoder 2 of the low part L-AB of the address bus AB is formed , According to the invention, the diagnostic decoder 3 is provided, which is also released with the card select signal KSEL, as the decoder 2. The diagnostic decoder 3 decodes generally only a diagnostic address from the low-part L-AB, which are expediently the same for all modules of a system should and forms the memory selection signal CSM. In connection with the external control signals WR, RD, which are connected to the memory access logic 4, the write-read access to the memory unit 5 takes place. FIGS. 2 and 3 show the respective embodiments of the memory unit 5 for the external and internal control of the type identifier. The main elements of the external type control memory unit 5 (Fig. 2) are the type register 5.3 and the status register 5.4. In the type register 5.3 is a module-specific type identifier (via inputs of the register 5.3 type setting signals TE are entered) stored with the help of the memory selection signal CSM and the external read signal RD-linked in the memory access logic 4 to the memory read signal RDM - (see Figs. 1 and 4) is read out of the type register 5.3 and placed on lines of the data bus DB. In a central assembly, not shown here, z. B. ZVE module, the read type identifier is compared with a centrally stored target type identifier. In the case of a determined difference (the correct module type is not inserted), the decoder 2, which generates selection signals CS1... CS η for the internal control of functional units, is blocked to avoid external accesses to functional units of the module. This is achieved by the output of the diagnostic address (formation of the memory selection signal CSM) and the external write signal WR, which are linked in the memory access logic 4 (see FIGS. 1 and 4) to the memory write signal WRM. The memory write signal serves as a gate signal for the gate 5.1 for at least one data signal DATi (connected to the data bus DB) which is written in a cell of the status register 5.4. The data signal DATi can also be omitted if the cell of the status register 5.4 has the behavior of a D flip-flop and the information input is fixed to the 1-level. With this written information and the resulting output signal DCF (decoder enable signal) of the status register 5.4, the decoder 2 is disabled.

The status register 5.4 also serves to record further fault and status messages (S / ST), which are formed by monitoring or test devices, not shown here, and are written via the optional input port 5.2 into a respective memory cell of the status register 5.4. The content of the status register 5.4 thus represents the respective current status of the module, whose signals can be placed on some lines of the data bus DB and further processed by the central module with a diagnostic read access (formation of the memory read signal RDM memory access logic 4). Parallel to this bus output, which is realized via the data bus port 5.5 (memory read signal RDM to CS input of the gate 5.5), some signals of the status register 5.4 are combined via the OR circuit 5.6 to the collective fault signal SS of the module and, for example, brought to the display.

The resetting of the status register 5.4 (R input) takes place with the already described memory write signal WRM in conjunction with selected data signals DATj, which are connected via the reset gate 5.7. If a read-only memory is present on the module due to the function, the type register 5.3 can also be replaced by a memory location, so that in this case the reading of the type identifier is realized as a normal memory read operation. The memory unit 5 would thereby be reduced by the type register 5.3.

FIG. 3 shows the memory unit according to FIG. 1 for implementing the internal module-type control of the type code. For this variant, the functional sequence described below results. With the aid of the memory write signal WRM (formation as described above), the desired type code is switched from the central module to the type comparator 5.8 of the memory unit 5 via lines of the data bus DB. The type comparator 5.8 compares the desired type code with the type code (type setting TE) stored at its other inputs or comparatively stored, and from this forms the comparison signal VS, which is written into a cell of the status register 5.4. The output signal of this register cell is the above-described decoder enable signal DCF, which blocks the decoder 2 (comparison signal VS at the enable input) in case of inequality between the desired type identifier and the set type identifier. The further units shown in FIG. 3 and their combination are identical to those of FIG. 2. The type comparator 5.8 used here can be a known multi-bit comparison arrangement. For intelligent modules z. B. certain described sub-functions can be realized by the module firmware.

Claims (6)

Anspruch [en] A circuit for controlling the type identification of electronic assemblies using two decoders for evaluating a two-part addressable bus, wherein the output of the first decoder coupled to the high portion of the address bus is the second decoder associated with the low portion the address bus is applied and generates selection signals for the internal control of functional units, releases as well as using a memory for the registration of interference and status signals, characterized in that coupled to the low part of the address bus (L-AB) and by the first Decoder (1) generated card select signal (KSEL) controllable diagnostic decoder (3) generates a memory selection signal (CSM), which is connected to a external control signals (WR, RD) connected memory access logic (4), wherein the first, a memory write Signal (WRM) leading output to the reset input (R) and a first terminal de s data input (I) of the memory unit (5) and whose second, a memory read signal (RDM) leading output to the output enable signal input (OE) of the memory unit (5) is linked that a of the memory unit (5) generated Dekoderfreigabe- Signal (DCF) to the enable input (En) of the second, coupled to the low part of the address bus decoder (2) is connected and that a first data signal (DATi) of the data bus (DB) with the reset input (R) of the memory unit (5) is connected. 2. A circuit arrangement for controlling the type identifier according to claim 1, characterized in that the memory unit (5) is constructed such that - The first data signal (DATi) of the data bus (DB) via a memory write signal (WRM) controlled gate (5.1) is connected to a first register input of a status register (5.4), wherein at the associated register output the decoder enable signal (DCF) is due, The output of a reset gate (5.7), which is connected to the memory write signal (WRM) and the second data signal (DATi), is connected to the reset input (R) of the status register (5.4), - Interference and status signals (S / ST) via an optional input port (5.2) to further register inputs of the status register (5.4) are connected, wherein the corresponding register outputs via a memory read by means of signal (RDM) controllable data bus port 5.5 are coupled to lines of the data bus (DB), - A number of register outputs of the status register (5.4) continue on a, a Sammelstör signal (SS) forming OR circuit (5.6) are performed and that further - A by the memory read signal (RDM) releasable type register (5.3), at whose inputs signals for type setting (TE) applied, the output side is connected to other lines of the data bus (DB). 3. A circuit arrangement for the control of the type identifier according to claim 2, characterized in that the type register (5.3) is a function to be controlled on the module assembly available read only memory. 4. A circuit for checking the type identifier according to claim 1, characterized in that the memory unit (5) is constructed such that - A memory write signal (WRM) activatable type comparator (5.8), the input side with lines of the data bus (DB) and lines for inputting the type setting (TE) is coupled, the output side generates a comparison signal (VS), which on a first information input of a status register (5.4) is connected, wherein the decoder release signal (DCF) is present at the associated register output, - The output of a reset gate (5.7), which is the input side connected to the memory write signal (WRM) and the data signal (DATj) of the data bus (DB), with the reset input (R) of the status register (5.4) is linked . - Interference and status signals (S / ST) are connected via an optional input port (5.2) to further register inputs of the status register (5.4), wherein the corresponding register outputs via a memory read signal (RDM) controllable data bus port ( 5.5) are coupled to lines of the data bus (DB) and that further a number of register outputs of the status register (5.4) on a, a collective error signal (SS) forming OR circuit (5.6) are performed. 5. A circuit arrangement for controlling the type identifier according to claim 4, characterized in that the type comparator (5.8) is designed as a multi-bit comparison arrangement. 6. The circuit arrangement for controlling the type identifier according to claim 1, characterized in that the memory access logic (4) has two conjunctions 4.1 and 4.2, wherein the conjunction (4.1) with the external write signal (WR) and the memory selection signal (CSM) and the Conjunction (4.2) with the external read signal (RD) and the memory selection signal (CSM) is connected. For this 2 pages drawings