DD211437A1 - CIRCUIT ARRANGEMENT FOR DETECTING THE TIMELY FOLLOWING IMPULSES - Google Patents

Abstract

The invention relates to a circuit arrangement for detecting the time sequence of pulses in digital technology, in particular for PLL and synchronization circuits and z. ACQUIRE. the direction of movement b. incremental measurement by means of two-frame scanning. D. inventive solution provides, d. a latch circuit consisting of a. two RC triggers u. a gate d. Switching sequence d.Impulse per cycle stores, as well as d. Arrangement of two gate functions this Verriegelungsschaltg. becomes a phase detector or a direction discriminator by means of four gate functions and two RC timers.

Description

Circuit arrangement for detecting the chronological sequence of pulses

Field of application of the invention

The invention relates to a circuit arrangement for detecting the phase position of two pulse sequences in digital technology, in particular for PIiL and synchronization circuits and for detecting the direction of movement in incremental measurement by means of two-frame scanning.

Characteristic of the known technical solutions

Circuits for detecting the chronological sequence of pulses are differentiated into phase detectors and direction discriminators and are respectively integrated or constructed by means of standard circuits. Phase detectors are preferably implemented as gate configurations because of their independence from the repetition frequency and insensitivity to the harmonics of the repetition frequency. In US Pat. Nos. 3,530,242, 3,487,166 and 3,936,604, phase detectors and gate configurations have been found which require a very high level of logic gates, so that the runtime-dependent maximum operating frequency is considerably reduced.

-UOl 1982 * 045346

A built-in phase detector is described by A.W. Moore in the IBEB Spectrum 1973, April, pp 61-67 (Phaselocked loops formator - speed control), but in which the specified gate configuration produces interference-prone output signals, whereby the logical processing of the output signals additional effort.

Other known metering discriminators, such as by Winterberg, V /. in Elektronik, Munich, 1978, No. 5, p. 95 described (direction discriminator for incremental measurement by Doppelspaltabnähme), in addition to a high circuit complexity, the use of monostable Kippstuf en * -, conditional issues such as susceptibility and signal output at voltage connection.

Object of the invention

The aim of the invention is the generation of direction-dependent increments for the applied in length and angle measurements Zweischrankenabtastung and / or the detection of the phase difference of two pulse trains with minimal effort.

Essence of the invention

The invention has for its object to use an integrable or composable from standard circuits circuit arrangement in any IS technology, with the aid of the phase difference of two pulses is detected such that in each case an output that the positive and a second output that the negative phase or time difference provides corresponding output signals without glitches, wherein the duration of the output signals is set equal to either the phase difference or by a selectable RC circuit to a defined value.

According to the invention the object is achieved in that two known RS-trigger with priority reset inputs are coupled to a Gatterfünktion to form the Rückaetzsignals to a latch circuit of two input signals, the first active level leading signal sets the associated RS-trigger and at passive level of both signals reset.

To realize the phase detector, the Yerriegelungsschaltung is supplemented by two gate functions that link the outputs of the RS trigger in a known manner to form a phase signal, wherein a gate output of the positive phase difference and the second gate output generates the negative phase difference signal without the Outputs output time-related spikes.

To construct the direction discriminator, the latch circuit is extended by four gate functions and two RC-Z elements, with one gate output outputting the positive signal sequence signal and a second gate output outputting the negative signal sequence signal RC-Zextglieder set. The type of gate coupling prevents · together with the low-pass behavior of the RC elements output signals when power is turned on.

The detection of the input signal sequence by the direction discriminator in three successive Sehaltzustanden allows the processing of input signals whose active level is formed by switch contacts. The embodiment of the circuit arrangement as a gate configuration allows an integrated or implemented by standard IS design in any IS technology, taking into account the respective active signal level UAlID and! OR gates are exchanged according to the De-Morgan equations without changing the overall function against each other can.

The gate coupling implemented in the circuit arrangement ensures output signals without glitches, which are suitable for PLL applications as well as for logical processing, in particular for counter control.

embodiment

With reference to an embodiment, the invention will be described in more detail in their functions. The puncture of the circuit arrangement for detecting the chronological sequence of pulses as a phase detector is shown with reference to FIGS. 1 and 2, wherein the circuit design is adopted in CMOS technology. The latch circuit is composed of the RS triggers 1 and 3 and the gate 2, and the output signals u and d corresponding to the phase difference are output from the gates 4 and 5.

In the initial state, the inputs e 1 and e 2 carry as passive signal H. Due to gate 2, the trigger outputs q 1 = q 2 to H and S 1 = S 2 to L, resulting in the output signals u and d with an L level , If E 1 = L first, gate 2 releases both BS triggers 1 and 3 for setting, causing RS trigger 1 to switch to q 1 = L and S 1 = H, thus keeping trigger 3 in its initial position. With gate 4, the output u = H * is formed as a measure of the positive phase difference between the H / L edges of the input signals while signal d remains at L. For the following e 2 = L, S 2 = H is produced by alloy S and the output of the phase signal through gate 4 is terminated with u = L. If e 1 = H, the switching state remains unchanged. Only with e 1 = e 2 = H causes gate 2 by resetting trigger 1 the initial state.

With reversed signal sequence of e 1 and e 2 trigger 3 is switched according to the Sehaltungssymmetrie, signal d appears with Η level for the negative phase difference.

The puncture of the circuit for detecting the time poles of pulses as a direction discriminator is based on Pig. 3 and Pig. 4 explained assuming the structure in TTL technology.

The circuit arrangement comprises the latch circuit consisting of the RS triggers 1 and 3 and the gate 2, the Yerknüpfungsschaltung from the Hegatoren 6, 7, 10 and 11 and gates 8, 9, 16 and 17 and the timers 12 and 13 with the threshold Triggers 14 and 15.

The input signals e 1 and e 2 as well as the direction signals ν and r are active with L level and the output state is taken with e 1 = e 2 = H and ν = r = H. The first switching state with e 1 = L and e 2 = H causes q 1 = L, the gate 16 blocks. The level change of e 1 due to contact bounce does not change the output signal g 1 of gate. With e 1 = e "= L, the second switching state is reached, the latched changeover switch of e 2 remains ineffective because the gates 16 and 17 remain inhibited In the following third switching state e 1 = H and e" = L, gate 8 forms the signal g 1 = L, whereby the trigger signal t 1 appears after the caused by the RC element 12 delay with Η level. In the following initial state with e 1 = e 2 = H trigger 1 is reset, and gate, 16 outputs the directional output signal ν = L, until by discharging in the timer 12, the trigger signal t 1 = L is.

In the opposite polarity of the singing signals, the corresponding direction signal ν = L at the output of the gate 17, while gate 16 unchanged ν = H maintains «If the supply voltage at any but unveran-- changed input signals switched, because of the required switching sequence in any of the two timers 12 and 13 a charging process take place.

Claims (4)

invention claims 1. A circuit arrangement for detecting the time sequence of pulses, characterized in that a Yerriegelungsschaltung consisting of two RC triggers (1; 3) and a gate (2) stores the switching sequence of the pulses per cycle, and by the arrangement of two gate functions this Yerriegelungsschaltung to a phase detector or by means of four gate functions and two RC timers (12; 13) to a direction discriminator. 2. A circuit arrangement for detecting the time sequence of pulses as a phase detector according to item 1, characterized in that the Yerriegelungsschaltung is supplemented by two gate functions that link the outputs of the RS trigger to form a phase signal in a known manner, wherein a gate output that of a positive Phase difference and the second gate output outputs the signal corresponding to a negative phase difference. 3. Circuitry for detecting the time sequence of pulses as a phase detector according to the points 1 and 2, characterized in that the output signals are free of glitches, and the entire circuit arrangement is implemented in integrated technology in any circuit technology. 4. A circuit arrangement for detecting the time sequence of pulses ala direction discriminator according to item 1, characterized in that the Yerriegelungsschaltung four gate functions and two RC timers are arranged, wherein a gate output the signal for the positive signal sequence and a second gate output outputs the signal for the negative signal sequence, the length of the output signals being determined by the RC timers. Circuitry for detecting the time sequence of pulses as Riehtungsdiskriminator according to the points 1 and 4 »characterized in that except the two time-determining RC elements, the circuit arrangement is implemented in integrated technology in any circuit technology. For this 3 sheets of drawings