DD158300A1 - CONTROLLER FOR COUNTERS WITH COUNTER AND DISPLAY MEMORY - Google Patents

Abstract

The invention is applied in electronic counting circuits, in particular in time measuring devices. The invention achieves the improvement of the control circuit according to the main patent with regard to reducing the effectiveness of interference pulses pretending to be a stop signal, the task being to control the interference of the control To reduce disturbed start signal and thus to achieve a fault-free display of the counter reading. According to the invention, the return input of the known trigger, which generates the reset signal of the control as well as the counting lock, a circuit arrangement of AND gate, pulse shaper. RS-trigger and OR gate connected upstream, which ensures that a complete interference against disturbances that are shorter than half the period of the frequency to be counted succeeds. Laenger pending disturbances are only effective if they rest during a certain clock edge. Advantageously, the automatic rounding of Zaehlerstandes after exceeding half the period of the Zaehlfrequenz.

Description

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Inventor: Dipl.-Ing. Wolfgang Fritzsche Berlin, 30.3.198 '

Zustellungsbevollm .: Institute for

Control technology in Kombinat PU ¹ B EAV / Berlin-Treptow "Friedrich Ebert" ^c Patent-Ing. Jürgen Holtfoth

Control circuit for counters with counter and display memory O H 03 K 21/30

Field of application of the invention

The invention is used in electronic counter circuits in which the interaction between count memory and a second, eg display memory, is regulated. In this case, the counter reading is to be maintained until the counter is restarted in order to enable the storage of two counting results, the first in the display memory and the second in the counter memory. Particularly advantageous is the use in Zeitmeßeinrichtungen for longer time intervals, in electronic stop watches. The given solution can be integrated into the counter f ") circuit.

Characteristic of the known technical solutions

In the control circuit for counters with counting and display memory according to patent WP H 03 K / 224 447 only start pulses from a length of one quarter of the period of the pulse sequence to be counted become effective. In contrast, the interference immunity against stop prone interference is lower. In the worst case, it can be equal to zero, namely when the stop signal occurs simultaneously with the triggering edge, which generates the control signal cd reset, counter lock. This disadvantage can at a

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Fault that simulates stop will lead to completely wrong count result, since the departure of the disturbance corresponds to a new start signal. The count reached so far is deleted after it has been transferred to the display server.

Object of the invention

With the invention, the improvement of the control circuit according to the main patent with respect to the further reduction of the effectiveness of glitches, which simulate a stop signal, achieved.

Explanation of the essence of the invention

The present invention further refinement of the control circuit for counters with counter and display memory according to the main patent, the task is based on the Störbeeinflussungsmöglichkeit the control circuit by a faulty start signal to reduce and thus to achieve a fault-free display of the count.

According to the invention this is achieved in that an additional circuit consisting of an AND gate, a Impulsformerstufe, an RS trigger and an ODEE gate to the dominantly acting reset input of the known RS trigger, the signal for resetting the control and counter lock supplies, is connected. Furthermore, this known RS trigger is driven at its clock input from the negated output of the known divider with twice the pulse frequency to be counted.

The additional circuit according to the invention is realized in such a way that at the inputs of the AND gate, the pulse frequency to be counted and, secondly, the start-stop signal are present. The output of the AND gate is followed by a pulse shaper circuit, e.g. Differentiating or monostable element that forms short pulses that reach the dominant acting reset input of an RS trigger. The dominant setting input of this RS trigger is connected to the control signal "Reset control and counter lock". The only acting during the clock edge setting input of this RS trigger is as well as a

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Input of the OR gate connected to the start-stop signal, while the equivalent reset input is set to a fixed potential, that at the clock input arriving pulses cause a single level change at the trigger output, in the presence of the stop signal. The clock input of this RS-Trigger is controlled with the negated, double pulse frequency to be counted. The negated output of this RS trigger is followed by the OR gate whose output is connected to the dominant acting reset input of the known RS trigger which forms the reset signal for the control.

This circuit ensures that the stop signal only becomes effective when, for the second time after the start of the stop signal, the switching edge of the double frequency pulse sequence to be counted appears. If the stop signal does not exist during the second switching edge, the control continues to operate as if there were no stop signal. With this solution, the security of the Speieherinhalte of counter and display against malfunction of the controller due to disturbances of the start-stop signal is substantially increased. As a further favorable effect is thus an automatic rounding of the count after reaching half the period of the pulse train to be counted connected. Like the circuit according to the main patent, this additional circuit also has the advantage of simple implementation in integrated circuits.

embodiment

The invention will be explained below using an exemplary embodiment. In the drawing show:.

Fig. 1: Control circuit according to the invention for MOS counter U 121 D.

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FIG. 2: Pulse sequences in the circuit arrangement according to FIG.

The Prinzipsehaltung shown in Fig. 1 with the controller according to the invention is an electronic stopwatch. This consists, as is known, of a frequency-stable generator 1, whose pulse period is divided down by the divider 2 on the time base to be provided. At the negated output

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of the trigger 4 of the divider 2, the time base is available as a clock for the counter circuits or 8 available. The counter circuit U 121 D contains a 4 bit binary counter with separate counting and display memory. In order for the storage of two outcomes is possible: a result is in the counting part, the other in the display _memory;

The control circuit according to the invention shown in Fig. 1 consists of AND gate 13, pulse shaper 14, RS trigger 15 and an OR gate 16, wherein the AND gate 13 connected to the start-stop means 10 and the negated output of the trigger 4 is. Its output is connected to the reset input R of the RS trigger 15 via the pulse shaping stage. The negated output of the RS trigger 15 and the start-stop signal reach the OR gate 16, the output of which is connected to the known RS trigger 7 »input R ,. The clock inputs C, the RS trigger 7 tmd 15 are driven by the negated output of the trigger 3. The input S of the trigger 15 is connected to the output of the trigger 7.

The function of the circuit is based on the Pig. 2 will be explained. The H / L edge should be the trigger edge, as well as negative logic. In the assumed initial state t ^ t _Q is the stop signal, which corresponds to H potential in pulse train 1 of FIG. 2, at the input of the AND gate 13, at the input S "of the RS trigger 15 and the OR gate 16. The output of the OR gate 16 has Η potential, since the output of the RS trigger 15 also has H potential - pulse train 5 - because of the L signal present at the set input S from the output of the RS trigger 7. At the time t = t is a start signal output from the start-stop device 10, which corresponds to L potential in pulse train 1. The RS trigger 7 is set via the OR gate 16 to H potential at its output (signal cd) and the frequency divider 2 and Counter 8 are released - pulse sequences 2, 3, 5, 6. Since the inputs of the AND gate 13 have also received L potential - pulse sequences 1,3- »reaches L-level to the pulse shaper 14, the input R

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of the trigger 15 supplies a pulse - pulse train 4 -. The negated output of the RS trigger 15 is thereby brought to L potential - pulse train 5 -, which comes at the OR gate 16 to the effect. This state of the circuit according to the invention remains until the delivery of a stop signal at the time t = t ,,.

In the circuit arrangement according to the main patent, the control would already be reset at the time t = tp, in that the RS trigger 7 switches the control signal cd to the L potential with the occurrence of the switching edge at the non-negated output of the trigger 3. In the solution according to the invention, this does not happen at the time tp, since the OR gate 16, despite the stop signal, continues to output an L signal because of the negated output of RS trigger 15 which is at L potential. With the first switching edge at the clock input of the RS trigger 15 after txj - pulse train 2 - its negated output is brought to H level - pulse train 5 - and thus the output of the OR gate 16 also. The RS trigger 15 can not be reset because of the lack of L potential from the start-stop device on the AND gate 1j - pulse train 4 -. The second switching edge after t ^ at the time t = t ^ at the clock input of the RS trigger 7 causes the switching of the trigger output to the signal cd = L and thereby the provision of the divider 2, the sub-controller 17 and the lock of the counter 8. The control the set input s of the trigger 15 by this control signal cc is not necessary for the function of the circuit arrangement, it would satisfy the connection to Η potential · However, the connection of the input S of the RS trigger 15 shown in Fig. 1 with the output of Triggers 7 the advantage of increasing the noise immunity to internal interference pulses.

As can be seen from the pulse sequence 3, an additional count pulse has been delivered to the counters after t 1. Since at the time of the stop signal tx | If more than half of the count period has elapsed, this additional count, which causes the rounding, is delivered. A stop signal at time t = t ^ does not round up, since at t ^, the return signal would be output.

For this purpose, a condition must be observed: the count pulse edge at the counter input must be simultaneously or later with the switching of the control signal cd, i. Counter lock, appear on L, otherwise it can also come here to round up.

Should an interfering signal occur which simulates a stop signal, e.g. at the time t = t ^ with a length of less than t-g, - t ^, there are no changes compared to the illustrated pulse sequences 2-6 in Pig. 1 until the end of the interference pulse. If the glitch is completed shortly before fr ™, i. it is again the start signal - corresponds to L level - at the OR gate 16, the AND gate 13 and the input S of the RS trigger 15 on, the Η level at the negated output of the RS trigger 15 until the next Switching edge of the count remain intact. With the switching edge of the count is over the AND gate 13 j pulse shaper 14 of the RS trigger 15 is put back into the start state.

With this solution according to the invention a complete interference immunity against disturbances is achieved up to a total duration of ^. In addition pending interference pulses are only effective if they are pending for the RS trigger 7 »15 during the second switching edge after the start of the interference pulse. This high interference immunity guaran- tees;!;., E.safe measurement and display of time accumulation, even with heavily disturbed input signals.

Claims (1)

  _ 9 - invention claim Control circuit for counter with counting and display memory, which generates the control signals, storage from the count memory in the display memory with deletion of the old display memory contents, reset the count memory and counter enable and reset the control, according to patent WP H 03 K / 224 447, characterized in that in that an AND gate (I3) is used to form the control signal (cd), which is connected to an input as well as the input (S) of a trigger (I5) to a start-stop device (10) and to the _r ---- s other input to the negated output of the trigger (4) is connected, that the AND gate (I3) sine pulse shaper circuit (14) follows, which with the input to the output of the AND gate (I3) and connected with the output to the input (R) of the trigger (15) is that the Impulsformerschaitung (14) of the trigger follows (I5) whose input (c), as well as the input (c) of the trigger (7) to the negated output of the trigger (3) and the input (S) is connected to the output of the trigger (7), while the input (R) is at a fixed potential that further the trigger (I5) is followed by an OR gate (16) whose inputs are connected once to the output of the start-stop device (10) and to the negated output of the trigger (15) and that the input (R) of the ( } knew triggers (7) is connected downstream of the output of the OR gate (16). Rer2ü_2_.Seiten Drawings