DD153457A1 - MULTISTABILITY STATE MEMORY - Google Patents

Abstract

The invention is applicable in industrial controls of any size and pursues the goal of excluding high ambush resistance with little effort ambiguous Speicherzustaende. The task of realizing any number of memory states in any order is achieved with interconnectable memory blocks, which preferably contain 4 to 8 memory levels. Each memory level consists of a master and a slave memory. The conditional setting of a master memory is only then adopted as a new state in the slave memory when the previous memory state was deleted by resetting all slave memory with certainty. This is done by time-delayed logical links between all slave and master memories. -Fig. 1-

Description

Inventor: Dipl.-Ing. Hartmut Bunzel .Berlin, 3 Oct. 80. Dipl.-Ing. Günther Döring P 1164 Dipl.-Ing. Matthias Gulbins rer, nat. Peter Hummitzsch Dipl.-Math. Rainer König Heinz Krüger Dr.-Ing. Roland Mushroom Dr.-Ing. Lothar Quack

Ing. Manfred Schäfer

Zustellungsbevollra. ί Institute of Control Engineering

in the combine VEB Elektro-Äpparate-Werke Berlin 1055 Berlin, Storkower Str. 101 Pat.-Ing. Günther Scheufeie

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Multistable state memory

Field of application of the invention

The invention is applicable to industrial control systems of any size in which an active logic state must always be available for executing a control function, and after which another logic state causes the execution of another control function, which is particularly suitable for such control systems. where there is a demand that at no point in time do two active logic states overlap in time, and in particular that the invention can be used for the control interpretation of Petri nets.

Characteristic of the known technical solutions

Some circuit arrangements for multistable state memories or multistable switches have already been proposed.

In DE-AS 10 64 IO5 an arrangement is described in which

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each storage stage is formed by a transistor, wherein each of the base terminal forms the storage stage input and the collector forms the storage stage output. The base terminal of each transistor is about Entkopplungswider- _t stands or * decoupling diode to the collector of each transistor with the exception of the collector of the own storage stage ally »Regarded as a logic module thus, each memory stage of a NOR gate in resistor-transistor logic or in diode-transistor logic. If a transistor is driven in such an arrangement, it keeps the other transistors in the opposite conducting state by the mutual wiring, even if the drive disappears, whereby an active state is stored »

This circuit has the disadvantages that a memory having a larger number of memory stages requires a plurality of connection lines and resistors for realizing the OR function. Overall, the number of storage stages can not be made very large anyway, especially if the circuit is implemented in bipolar technology, because the activated storage stage must supply the current j with which all other storage stages must be kept in the non-activated state »A projecting-friendly distribution into individual memory blocks is not possible with the specified solution. "Far more serious, however, is the disadvantage that this arrangement can not be used for industrial controls because the existing active state of a memory stage only disappears due to the fact that another active state already exists in another memory stage that is, temporal overlaps of the active states occur at the memory stage outputs.

A circuit-technical improvement of this solution is specified in DE-AS 12 82 077. The described disadvantages, however, remain unchanged. "

A multi-stable switching control arrangement is known from DE-AS 22 52 903, in the clock-controlled ^ li

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Flops are used as storage levels. A signal change at any input results in the generation of two consecutive single clock pulses. The first pulse causes the transfer of all input information to the master memory and the second pulse causes the master contents to be transferred to the slave memory. A newly activated input thus leads to an activated slave memory and the previously activated slave memory now adopts the. , non-active state from the input of its master memory.

With this arrangement, although a multistable state memory for a relatively large number of states can be constructed, the more extensive the arrangement becomes, the more connecting lines and the more complex gate circuits are required. One way to divide into memory blocks, this arrangement does not. The transition zv; ischen two states takes place in the time in which the slave memory with the second clock pulse are controlled. Thus, it is not excluded that temporal overlaps can occur during the transition. With the clock control there is also the danger that due to disturbing unwanted clock pulses are triggered, which cause a faulty state change.

In DD-PS I30 298 a multi-stable memory module is described, which eliminates part of the defect described. As memory elements clock-controlled flip-flops are used j wherein the information transfer takes place in each case by a Takteinze limpuls, which is generated from each signal change that occurs at any input. By means of a blocking device is achieved _s that never two outputs can be activated simultaneously.

By interconnecting a plurality of such memory blocks could control any scope can be built _$ the single memory chip but requires a high expenditure of logic gates to ensure the operation. The disadvantage of this solution is the high susceptibility to interference from ...

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Object of the invention

The invention 'pursues the. _Target} in "to achieve a multi-stable state memory ensures high reliability, temporal overlaps of Speieherzustände during transitions

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Low component requirement *

Essence of the invention

 Object of the invention

The invention has for its object to provide a multistable state memory / with the arbitrary many memory states are feasible and in which the order and the direction of the transitions between the memory states une- 'limited are freely selectable, with the one complete state graph is feasible. An active memory state must invariably only occur at a single output, during the transitions between the states there must be a defined pause, and each transition may only be triggered by the fulfillment of the set condition at a new memory level input. Runs must also be executable with the multistable state memory. It should be able to be assembled from memory blocks in a simple way to construct large control systems of any structure. "

Features of the invention

The object is achieved by a multistable state memory consisting of any number of memory blocks, each memory block preferably containing 4 to 8 memory stages, each consisting of a master memory and a slave memory. has the following features of the invention. A memory stage input leads to the set input of each master memory and, in conjunc- tion with it, a prepare input The output of each slave memory is connected to a memory stage output, to the reset input of its own master memory and to one input of a conditional gate. Its output leads to a conditional connection and to the input of a

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Inverter. The output of the inverter is connected via a timer to both the inverse input of a reset gate and to the condition input of each slave memory. The output of each master memory is connected both to the enable input of each slave memory and to one input of a request gate, the output of which is connected both to a request terminal and to the direct input of the reset gate whose output is connected to the reset input of each slave memory · Of all the memory blocks that make up the multistable state memory, the request connections are interconnected and also the conditional connections.

All master and all slave memories are static RS memory flip-flops, with the master memories having a set delay.

To prepare the order of the transitions, each memory stage output is connected to the preparation input by means of preparatory pulses, whose memory stage input is activated next depending on the operating procedure.

Within the course of operation, the setting of a cycle is requested by setting a master memory, with which the transition to a new state is to take place. The previously set slave slave is reset via the request gate and the reset gate. Its output signal change causes after a delay in the timer the disappearance of the reset signal at all slave memories and the release at their condition inputs * Thus, the signal is taken over by the requesting master memory in the associated slave memory, this active. Returns state to its memory level output and resets its master memory immediately *

embodiment

The invention will be explained in more detail below with reference to an embodiment. In the accompanying drawing show

Fig. 1 j shows a memory block for setting up multistable Zu

memory 2, the interconnection of several memory blocks.

Controllers of any size can be constructed with the memory block SB in Fig. 1. Depending on the size of the controller, a corresponding number of such memory blocks SB are interconnected "The circuit-specific details of an interconnection will be discussed in greater detail below the explanations of the circuit arrangement on a single memory block SB _e

The memory block SB includes a number of memory stages, each of which is stored in a master memory, e.g. B, MS 1, and a slave memory, z «, B * SS1 composed Each master and each slave memory is designed as a static RS memory with dominant erase behavior. All set inputs S each have two equivalent and conjunctively linked input terminals * Basically, the number of memory levels within the individual memory block SB can be set arbitrarily _{e However,} for practical applications, a structure with 4 to 8 memory levels is appropriate »For the selected example was in Fig Since a memory stage can in each case implement a memory state, this memory block SB represents a multistable state memory for 4 states.

At the storage stage inputs E1 to E4, the process signals are turned on. So that short-term disturbances on the lines that lead to the storage stage inputs E1 to E4- .j have no influence on the memory state, it is expedient to equip the master memory MS1 to MS4 with a set delay. Then only those signals that overcome the set delay time are considered correct. Within a memory block SB, the logical operations are carried out by means of a request gate AG and a condition gate BG, both of which are designed as OR gates. A bin negator NE, a timer ZG and a reset gate RG, which is designed as a blocking AND, ensure that the requirements for the

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certainty between the states. At the memory stage outputs A1 to A4, the memory states occur, with which the process flow is controlled.

If, at a memory block SB, the setting condition at the input of one of its 4 memory stages is fulfilled, then the associated output assumes the active state. It keeps it on until at the input of any other memory level the setting condition is met again, whereby a transition of the active state takes place on the output of this other memory level. "The order of the transitions can be set arbitrarily. This means that a complete 4-state graph can be achieved with the memory block SB. An unconditional requirement for the individual memory block SB as well as the interconnection of any number of memory blocks SB to a multistable state memory with any number of states is that the active state is too high no time at two outputs at the same time, but always may occur only at the output of a single memory stage and that the transition of the active state to another output a defined break must be maintained

Considering the operation of the memory block SB in Fig. 1, it is assumed that the idle state has no memory set. Each master memory MS 1 to MS 4 and each slave memory SS 1 to SS 4 then carry an O signal at its output Q. Since the output Q of each Slavespe.ichers SS1 to SS4 is fed back to the reset input R of the associated master memory MS1 to MS4, there is also O signal. Also O-signal lead the output of the request gate AG and thus the direct input of the reset gate RG and the output of the conditional gate .BG. Because of the inverter ITE is present at the inverse input i of the reset gate RG and at the condition input Eb of each slave memory SSI to SS 4 1 signal. The delay time t of the timer ZG is only a few milliseconds and therefore ^ ₁ rest state can be disregarded. From the available signals it can be seen that at the reset input R

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an O-signal is present in each slave memory SS1 to SS4, so that an arbitrary slave memory SS1 to SS4 can be "set" by a 1-signal at the activation input Ea.

The practical operating case now requires a specific memory state. "For example, the memory stage output A3 is activated. For this, a 1-signal is applied to the memory stage input E3." For the time being, it is assumed that a 1-signal is already present at the preparation input Ev3. "How this signal is generated , will be explained below. The master memory MS3 is set as -o and provides at its output Q a 1-signal, with which it requests the expiration of a cycle in which the associated slave memory SS3 must be set, which also happens directly in this Pail via its activation input Ea, because the condition input Eb already carries a 1-signal. At the output Q, of the slave memory SS3 there then arises a 1-signal which is available at the memory stage output A3 as an active state for the control tasks of the respective operating case.

The 1-signal from the output Q of the slave memory SS3 immediately resets its master memory MS3 and keeps it in the reset state until the slave memory SS3 is reset by the operation itself. In addition, this 1-signal passes through the conditional gate BG and the negator KE after the delay time T via the timer ZG as an O signal both in the inverse input i of the reset gate RG and in the condition input Eb all slave memory SS1 to SS4, causing them are locked against an unwanted setting by a fault. At the beginning of the sequence described, a 1-signal briefly appeared at the direct input d of the reset gate RG, which lasted as long as the master memory MS3 was set and not yet reset by its slave memory SS3. The delay time T of the timer ZG in this case prevents the O signal at the inverse input i already arrives when the short-term occurring 1 signal at the direct input d

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not disappeared again. It should therefore be dimensioned so that the master memory MS3 is safely reset. As a result, an O signal remains continuously active at the reset input R of all read-only memories SS1 to SS4.

The active state at the memory stage output A3 now remains until the setting condition is met, depending on the operating sequence at another master memory MS1 or MS2 or MS4. This is to apply, for example, to the master memory MS1. Again, it is assumed again that at the preparation input Ev1 already a 1-signal is present, so that is set with a 1-signal at the memory stage input E1 of the master memory MS1. With its 1-signal at the output Q, the master memory MS1 requests the execution of a new cycle and thus, the setting of the associated slave memory SSI. However, this can not be set yet, because its condition input Eb still carries an O signal. As a result, the master MS1 is not yet reset for the time being, but its 1-signal is at the direct input d of the reset gate RG- effective at the inverse input i still an O ~ signal, namely the negated output of the still set slave memory SS3 is present , Thus, the reset gate RG outputs a 1-signal to the reset input R of all slave memories SS1 to SS4-. The slave memory SS3 is reset and the active state at the memory stage output A3 is completed.

All slave memories SS1 to SS4 now output an O signal at their output Q. After this has passed through the conditional gate BG and the negator NE, it occurs after the expiry of the delay time Z at the output of Zoitgliedes ZG as a 1-signal. Each slave memory SS1 to SS4- is thus supplied to its condition input Eb with a 1-signal, and at its reset input R the 1- changes to an O-signal. Now, the set condition at the slave memory SS1 is satisfied, and the request of the master memory MS1 can take effect. The slave memory SSI is set, and at the memory stage output A1 is a 1-signal as a new state for external

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Tax tasks available «

From the sequence is su seen that the transition of the active state of a memory stage output to the other, in the example of A3 to A1, a compulsory break occurs whose length corresponds to the delay time,, or «due to the Umschaltze.iten the memory and gate yet is a little bit longer. The signals which occur as a result of the state change are similar to those already described, so they should only be briefly mentioned once more. The master memory .MS1 · is reset, and an O signal reappears at the direct input d of the reset gate EG »After the delay time V has elapsed, an O signal is again present at the inverse input i and at each condition input Eb.

The order of transitions between the states to be assumed is entirely arbitrary. In practical use, however, the order can be set in such a way that between the memory stages between which transitions should take place, preparation lines VL are inserted in such a way that the memory stage output, in the example A3 _S. from which the transition originates, is connected to the preparation input, in the example Ev1, to whose memory stage the transition leads. In FIG. 1, this is indicated by a dashed preparation line VL. If these preparation lines VL are established for all transitions, it is ensured that only at that master memory the setting condition can be met, which finds at its preparation input a 1-signal, which results from the active state of the in front of him memory output. This also clarifies the origin of the previously assumed 1-signal at the preparation input Ev3 or * Ev1 "Of course, in an interconnection of many memory blocks, each preparation line VL can be inserted between any memory stage output and any preparation input of different memory blocks."

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Of course, the preparation inputs Ev1 to Ev4 need not necessarily be used in this way. They can also serve other purposes or remain completely unused by constantly having a 1-signal applied to them. However, if the order of the transitions is determined by means of preparation lines VL, then the realization of passes is easily possible. For example, at the desired time of the transition from one state to the next, it is possible to simultaneously apply a pulse-shaped 1 signal to all memory stage inputs E1 to E4-. The pulse duration must be shorter than the delay time Z. It is also possible to continuously apply a 1-signal to all memory stage inputs E1 to E4. The transitions then take place from one state to the next at intervals which correspond approximately to the delay time ΐ . Of course, these passages can also be implemented in interconnections over all the memory blocks SB involved.

It should be noted that for the first-time start of a preparation lines VL.durchseit connected multistable state memory, an additional device, not shown, is required, which briefly feeds a 1-signal, for example, via an OR gate in the preparation input to be started.

The interconnection of any number of memory blocks SB to multistable state memory with any number of states is done in a simple manner by means of a conditional connection BA and a request connection AA, which are designed as bidirectional connections. For this purpose, as shown in Fig. 2, of all the memory blocks SB a connection between each conditional connection BA and between springs request connection AA prepared .. Of course, it should be noted that the load capacity of the conditional gate BG and the request gate AG on the number of to be connected memory blocks SB is tuned.

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For the single memory block SB, it does not matter where the logic signals at the input of the inverter NE and at the direct input d of the reset gate RG originate, the reaction of each memory block SB on it is as already described with reference to Pig, FIG. For this reason, each memory block with one cycle request can affect all the remaining memory blocks.

Claims (3)

224396 -13- Er. 1, multi-stable state memory for any number of memory states »which consists of any number of memory blocks, each memory block preferably contains 4 to 8 memory levels, each consisting of a master memory and a -Slavespeicher, characterized in that the set input (S) of a each master memory CMSI to MS4) a memory stage input (E1 to E4) and, conjunctively associated with this, a preparation input (Ev1 to EvA-) leads that the output (Q) of each slave memory (SS1 to SS4) each with a memory stage output (A1 to A4-), to the reset input (R) of the associated master memory (MS1 to MS4 ·) and to each one input of a condition gate (BG) whose output leads to a conditional connection (BA) and to the input of an inverter (NE) whose output is connected via a timer (ZG) to both the inverse input (i) of a reset gate (RG) and to the condition In each slave memory (SSI to SS4) is connected, that the output (Q) of each master memory (MS1 to MS4) both with the activation input (Ea) of each slave memory (SS1 to SS4) and with one Input of a request gate (AG) whose output leads both to a request terminal (AA) and to the direct input (d) of the reset gate (RG) that its output to the reset input (R) of each slave memory (SS1 to SS4) is connected, and that of all the memory blocks (SB) the Ahforderungsanschlüsse (AA) with each other and also the conditional connections (BA) are interconnected. Multistable state memory according to item 1, characterized in that all master memories (MS1 to MS4) and all slave memories (SS1 to SS4) are designed as static RS memory flip-i'lops and in that the master memories (MS1 to MS4) have a set delay respectively. 2 2 4 3 9 6 3 * Multi-stable conditioner according to points 1 and 2, characterized in that each feed output (eg A3) is connected to the respective preparation input (eg Ev1) through preparation lines (VL) whose storage stage input '(z * B E1) is activated next depending on the operating sequence. For this purpose see the drawings