DE2724032A1 - DIGITAL STORAGE CELL - Google Patents

Description

Dipl.-Phys. OE Weber τ ds yonchen 71

Patent attorney Hofbrunnstrasse 47

Telephone: (089) 7915050

Telegram: monopoly weaver mOnchen

M 538

MOTOROLA, Inc.

East Algonquin Road
Schaumburg, 111. 60196
United States

Digital memory cell

709849/1112

The invention relates generally to digital memory cells and more particularly relates to a static MOSFET memory cell, which is suitable for monolithic integrated circuits.

In digital systems it is expedient to use bistable memory elements or memory cells, which change their state or status in response to a binary input signal. A great variety of different Types of memory cells are known which are also referred to as flip-flops or trigger stages. Complicated modern digital systems require large numbers of memory cells which are so arranged are that they store and exchange digital information together. Such memory cells often form the largest share of the total components that are required for such a system. This is true especially for digital systems such as microprocessors, which use MOSFET devices in a monolithic integrated circuit. These integrated circuits from microprocessors usually contain large numbers of memory cells that function as data registers which contain digital information exchange with each other via corresponding data channels. So it would be extremely desirable to have a simple MOSFET memory cell available which uses only a minimal number of components and which only takes up a particularly small area on a semiconductor wafer. Because of the large number of memory cells that are required and because of problems in designing related circuit connections between individual cells the use of a more simply structured memory cell, which only requires fewer components and which requires simpler connections, lead to the Total area requirement on a semiconductor wafer or a semiconductor chip is greatly reduced, so that the

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Manufacturing costs of a corresponding monolith integrated circuit can be reduced accordingly.

, In the bistable memory cells of the stored binary state is defined by the conduction state of the cross-coupled elements, which are arranged such that the transmissive state of an element guarantees the locked state of the other element. In making a system in which digital information is exchanged between areas of identical memory cells of this type, the operation of the individual memory cells must ensure that an applied input signal dominates the internal elements of the cell to determine the final memory status. In integrated circuits which use MOSFET elements, memory cells have additional switching or transmission elements which are controlled by clock signals in order to ensure that the above-mentioned condition is met. These additional devices together with the correspondingly complicated wiring to the associated clock signal devices and to devices within the cell have resulted in the required area on a semiconductor wafer or a semiconductor chip being correspondingly large and thus having the manufacturing costs for the production of such cells increased in the integrated circuits.

The invention is based on the object of a MOSFET memory cell to create the type explained in more detail, which with an extremely low Number of line connections and a particularly small one Area on a semiconductor wafer. The im Patent application laid down features.

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According to the basic idea of the invention, a static MOSFET memory cell is thus created, which is formed from cross-coupled inverters in which a resistance feedback device continuously connects the memory cell input and output with one another, with an isolation of the Memory cell output against the memory cell input is guaranteed to enable a momentary applied input signal changes the stored status of the cell and the permeable status of the Cell is retained when the currently applied input signal is switched off.

The invention is described below, for example, with reference to the drawing; in this shows the only one Fig. A schematic representation of a circuit which a particularly preferred embodiment of the Subject of the invention represented.

In the drawing, a representative section of a digital system is illustrated, which a having static MOSFET memory cell 10 according to the invention. Regarding the terminology, it should be noted that the Abbreviation MOSPET all field effect transistors and logic gates with an isolated Gate are addressed. It should be known that a MOSFET can be used either as a P-channel element or as a N-channel element can be formed. In the description The operation of the circuit discussed here assumes that N-channel MOSFET elements may be used, although basically P-channel MOSFET elements as well could be used. It is also known per se that a MOSFET is a bilateral device which has two main electrodes that work interchangeably as source or brain electrodes, which depends on which electrode the

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stronger positive potential. For the present description it is agreed that the main electrode referred to as either a source or a drain, although basically during the operation of the circuit an electrode called the source can temporarily also function as a drain. MOSFET devices can also be designed as enriched facilities or as depleted facilities. Although at the arrangement described here enriched facilities are preferred, can also be impoverished Facilities and in particular those facilities are used in which a connection between Gate and source serve to generate a self-bias.

As shown in the drawing, a first data channel 12 is connected to the drain of the transmission MOSFET 14, the source of which is connected to the input of the memory cell 10 via the line 16. The gate of the MOSFET 14 is connected to a control line 18, which supplies the digital signals which are required to transmit data from the data channel 12 to the input of the memory cell 10. A second data channel 20 is connected to the drain of the transmission MOSFET 22, the source of which is connected to the input of the memory cell 10 via the line 16. The gate of the transmission MOSFET 22 is connected to the control line 24, which supplies the digital signals which are required for the data transmission from the second data channel 20 to the input of the memory cell 10. The line 26, which represents the output of the memory cell 10, is connected to the source of the transmission MOSFET 28, the drain of which is connected to the first data channel 12. The gate of the transmission MOSFET 28 is connected to the control line 30, which supplies the digital signals necessary for the transmission of digital information from the memory cell 10 to the

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first data channel 12 are required. The line 26 also connects the output of the memory cell 10 the drain of the transmission MOSFET 32, the source of which is connected to the second data channel 20. The gate of transmission MOSFET 32 is connected to line 34, which supplies the digital control signals necessary for a transfer of information from the memory cell 10 to the second data channel 20 are required.

As shown in the drawing, the memory cell 10 has a first MOSFET inverter, which is formed by the MOSFET elements 36 and 38, and it also has a second MOSFET inverter, which is formed by the MOSFET elements AO and 42 , and finally it has a resistance feedback which is formed by the MOSFET 44. The input line 16 of the memory cell 10 connects to the gate of the MOSFET 36 and to the source of the MOSFET 44. The source of the MOSFET 36 is connected to a first power supply line which is the ground potential in this particular embodiment. The drain of MOSFET 36 is connected to line 46, which is connected to the source of MOSFET 38 and is connected to the gate of MOSFET 40. The drain of the MOSFET 38 is connected to a second power supply line 48, which in this preferred embodiment is at the potential V _DD . The gate of MOSFET 38 is also connected to V _DD so that MOSFET 38 is a self-biased load device for this first MOSFET inverter. The source of the MOSFET 40 is connected to the first power supply line (ground), and the drain of the MOSFET 40 is connected to the line 26, which is connected to the drain of the MOSFET 44 and to the source of the MOSFET 42 and which is the output of the Represents memory cell 10. The gate and drain of MOSFET 42 are connected to line 48 labeled _{V DD,}

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so that the MOSFET 42 represents a self - biased load device for the second MOSFETV inverter. The gate of MOSFET 44 is connected to a reference voltage. connected, which is the line 48 labeled V _DD for the preferred embodiment shown in the drawing. It should be noted that despite the fact that the MOSFET elements 38, 42 and 44 are enriched elements, the MOSFET 38 and / or the MOSFET 42 could also be implemented as depleted load devices (with a connection between gate and source for self-biasing could serve), and the MOSFET 44 could also be designed as a depleted device .

The operation of the static MOSFET memory cell will be explained with reference to the drawing, assuming that the MOSFET 40 is permeable . It is also assumed that the control lines 18, 24, 30 and 34 are initially all at a logic level 0, so that the transmission MOSFET elements 14, 22, 28 and 32 are all blocked. Since the gate of the MOSFET 44 has a reference voltage applied to it (V _DD ), the MOSFET is always permeable and thus connects the logic level 0 on the line 26 with the other components in such a way that on the line 60 and at the gate of the MOSFET 36 a logic level 0 is present. Characterized because the MOSFET 36 is blocked, there is a possibility that the MOSFET 38 brings the line 46 to a logic level 1, so that the MOSFET remains permeable 40 and the cell is maintained in a stable state 10 (where it is a logical ¹¹ O "stores). in order to keep the MOSFET 36 locked, it is only required that through the MOSFET 44, a sufficiently star ker current flows, a voltage build-up at the gate of MOSFET 36 due to leakage currents or due to prevent interference currents. This condition can be fulfilled in that the MOSFET 44 as a back

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sufficiently small element is formed, which has a relatively high impedance in the permeable state . It is also assumed that the memory state of cell 10 is to be changed from a logical 0 to a logical 1 . This change is triggered by the fact that a logic level 1 is applied to the input of the memory cell 10 via the line 16. This logic level 1 can come from the first channel 12 or from the second channel 20, and it is fed to the input of the memory cell 10 via the transfer MOSFET elements 14 and 22, respectively, in response to control signals having a logical 1 on the control lines 18 or 24 are present. As explained above, the previous status of cell 10 (with a logic 0 stored) is retained by virtue of the logic 0 being present on line 26 which is connected to the gate of MOSFET 36 via MOSFET 44. In order to bring about a change in the status of the cell 10 , a newly applied logic 1, which appears on the line 16, must dominate the logic 0, which is present on the line 26 , so that the MOSFET 36 from the blocked state to the permeable state can be transferred. In known MOSFET memory cells , switching elements which are controlled by clock signals have been used to interrupt the internal feedback of the memory cell in order to provide an applied input signal with the possibility of changing the memory state of the cell. The gist of the present invention resides mainly in the fact that a resistor device is built into the internal return path of the memory cell, which can achieve such a result in a much simpler manner, requiring a smaller number of MOSFET elements and also those with use circuit problems associated with clock control devices are avoided. In other words, the essence of the invention

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by referring to the fact that a simple static MOSFET memory cell is achieved by using a resistor device to perform both a cooperation and an uncoupling function. From the preferred embodiment explained with reference to the drawing, it can be seen that a logic level "1", which is ^{fed to the gate of the MOSFET 7} via the input lines 16, causes the MOSFET 6 to go into the conductive state because the relatively high impedance of the MOSFET 44 decouples the logic level “1” on the input line 16 from the logic level “0” on the line 26. The conductive state of the MOSFET 36 causes the line 46 to change from a logic 1 to a logic 0, so that a logic 0 is fed to the gate of the MOSFET 40. This logic 0 at the gate of MOSFET 40 enables the drain of MOSFET 40 (line 26) to transition from logic 0 to logic 1. In normal operation, the logic 1, which is fed to the input of the memory cell 10 via the transfer MOSFET 14 or via the transfer MOSFET 22, occurs only momentarily, and with a duration which is determined by the time sequence of the control signals on the lines 18 or 24 is set. When the transfer MOSFET elements are turned off, the logic 1 must be maintained on the line 16 if the memory cell 10 is to remain in a stable state in which it stores a logic 1. This condition is fulfilled by the MOSFET 44, which now takes on a coupling function in the transmission of the logic 1 on the line 26 to the gate of the MOSFET 36. Thus, it can be seen that a resistive device, as represented by MOSFET 44 in the preferred embodiment of the drawing, is both decoupling and decoupling

can exercise a coupling function and thereby the 70 9 8 U 9/1112

Creates the possibility of creating a static MOSFET memory cell with a much simpler structure, which only requires a minimal number of components. For monolithic integrated circuits, it is a Extremely great advantage when there is no need to have connecting lines to clock control devices to use, because in the technical implementation of a corresponding circuit, the entire Arrangement due to the simplified cable routing becomes much smaller and simpler. The corresponding savings in cell area can be a significant factor be in the process of reducing the total area of a corresponding semiconductor chip and thereby reducing the Manufacturing costs of a monolithic circuit for complex systems such as microprocessor systems are considerable to reduce, since very large numbers of memory cells are required for the formation of registers.

In a preferred embodiment of the subject matter of the invention, that illustrated in the drawing Configuration of the circuit used for register memory cells in a microprocessor. In this application the first channel 12 is an address channel and the second channel 20 is a data channel. With a corresponding In terms of device technology, the MOSFET devices of the memory cell 10 had the following values for the ratio of channel width to channel length (W / L):

W / L ratio

(1.4 / 0.25 mils) (0.4 / 0.88 mils) (4.8 / 0.25 mils) (0.4 / 0.6 mils) (0.4 / 1.32 mils)

7 0 98 4 9/1 112

Component 0.036 / 0.006 mm 36 0.010 / 0.022 mm 38 0.122 / 0.006 mm 40 0.010 / 0.152 mm 42 0.010 / 0.034 mm 44

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Using · these ratios will allow a much more compact arrangement, because the Leitunpsverbindungen are not needed for clock control, so that compared to a conventional memory cell which had a footprint of about 1, ^ ^r mm ² // square mils), according to the invention only about 0.76 mm (30 square mils) was required. Since a total of 72 register cells were required with a corresponding device set up by a microprocessor, the total area required for the register section could be reduced to almost 5096.

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BATH ORIGINAL

Claims (7)

Claims Static MOSFET memory line with an input and an output, characterized in that a first inverter (36, 38) is provided which has an input which is connected to the input of the memory cell and which has an output (46), that there is also a second inverter (40, 42) which has an input which is connected to the output (46) of the first inverter and which has an output which is connected to the output (26) of the memory cell, that Furthermore, a resistance ^feedback device 1 (44) is provided which continuously connects the input (16) of the memory cell and the output (26) of the memory cell to one another in order to isolate the output (26) of the memory cell from the input (16) of the memory cell, thus a momentarily applied egg η pranks signal can change the permeable state of the first inverter and can maintain the permeable state of the first inverter when the currently supplied signal a b is switched. 2. Memory cell according to claim 1, characterized in that the Wirierstandsrückführeinrichtung comprises a MOSFET feedback device (44) which has a drain which is connected to the output of the second inverter, wherein there is also a source that is connected to the input? of the first inverter, and there is a gate connected to the reference voltage ¹ (4R). 3. Memory cell according to claim 2, characterized in that the first and the second inverter , are each connected to a first (ground) and a second (48) power supply line. 709849/1 1 12 ORIGINAL INSPECTED 4. Memory cell according to claim 3 » characterized in that the gate of the MOSFET feedback device (44) is connected to the second power supply line (48). 5. Static MOSFET memory cell, which consists of a cross coupling of a first and a second inverter, characterized in that the cross coupling is formed in that the output (46) of the first inverter (36,38) directly to the input of the second inverter (40,42) is connected and that the output of the second inverter is connected to the input of the first inverter via a resistance feedback device (44). 6. A memory cell according to claim 5, characterized in that the resistance return device has a MOSFET return device (44) which has a drain which is connected to the output of the second inverter , which further has a source connected to the input of the first inverter is connected and which has a gate which is connected to the reference voltage (48) . 7. Digital memory cell, characterized in that a first power supply line is provided, that a second power supply line (48) is also present , that a first MOSFET (36) is provided which has a gate which is connected to the input terminal (16) of the Memory cell is connected, which further has a source which is connected to the first power supply line, and which has a drain that further a second MOSFET (38) is present which has a source which is connected to the drain of the first MOSFET (36) tied together 7 Q 9 8 4 9/1 1 1 2 and which has a drain connected to the second power supply line that further a third MOSFET (40) is provided which has a gate which connects to the drain of the first MOSFET (36), which further has a source connected to the first power supply transistor and which has a drain connected to the output terminal (26) of the memory cell is that there is also a fourth MOSFET (42) which has a source which is connected to the drain of the third MOSFET (40) is connected, and which has a drain connected to the second power supply line is connected, and that a fifth MOSFET (44) is provided which has a gate which is connected to the second Power supply line (48) is connected, which has a drain which is connected to the drain of the third MOSFET (40) is connected, and which has a source connected to the gate of the third MOSFET (36) is. 709849/1112