DD152886B1 - DIGITAL FREQUENCY AND PHASE COMPARATOR - Google Patents

Description

Both D-trigger necessary high level at the output of the relevant D-trigger, which may theoretically only be set at the opposite sign of the phase difference.

It is obvious to supplement the described known phase comparator to a frequency and phase comparator by their D input is connected to the respective associated output for the negated signal in both D-triggers, making them work as a T-trigger. In addition, two additional clock-edge-controlled D-triggers are required. The D inputs of these two other D triggers are always low. The output of the NAND gate is additionally connected to the set inputs of both D-triggers. The set inputs have a higher priority than the corresponding clock inputs. The output of the one T-trigger for the negated signal is connected to the clock input of the other D-trigger and the corresponding output of the other D-trigger is connected to the clock input of the other other D-trigger. In the basic state these two D-triggers are set. The principle of the frequency comparison is based on the fact that at frequency equality of the two input frequencies at the clock input of one of the two other D-trigger always a low-high edge appears when just the set input is activated and thus makes this clock edge ineffective. For this purpose, however, it is necessary that the mentioned, occurring when resetting the two T-trigger low-high edge has subsided, as long as the set input is still activated. The two T-triggers and the NAND gate of the phase comparator must therefore always meet the appropriate switching time conditions, taking into account temperature influences and aging processes.

If the frequencies of the first and second input signals are in the ratio 2: 1 with respect to one another, for example, the first low-high edge of the first input signal activates the third output signal. The second low-high edge of the first input signal inactivates the third output signal and the now following low-high edge of the second input signal activates the fourth output signal, so that a false sign of the phase difference of both input signals is simulated.

Object of the invention

The object of the invention is to provide a digital frequency and phase comparator whose phase comparison output signals are not superimposed with interfering signals and are not faulty even with unequal frequencies of the input signals and which does not impose any particular switching time conditions on the stages of use used.

Explanation of the essence of the invention

The invention is based on the object by additional switching means to prevent the transmission of interference to the phase comparison outputs to reset the reset by the second active edge of the higher frequency input signal T-trigger before the first active edge of the input signal of lower frequency arrives and the activation The set inputs of the D-Triggers must be secured until the two T-triggers have been reset independently of the switching times of all the construction stages used.

The invention relates to a digital frequency and phase comparator having a first T-trigger triggered by a first input signal and a second T-trigger triggered by a second input signal having a first NAND gate, both of which Inputs are connected to the outputs of the two T-triggers for the non-negated signal and whose output is connected to a connection point which is connected to the reset inputs of the two T-triggers and to a frequency comparator having a first and a second output. At the first output, a first output signal, which represents a logical 1, if the frequency of the first input signal is greater than the frequency of the second input signal. Accordingly, at the second output, a second output signal occurs, representing a logical 1 if the frequency of the first input signal is less than the frequency of the second input signal. In this case, the frequency comparator preferably consists of two clock edge triggered D-triggers whose D inputs are at a potential corresponding to a logic 0 whose clock inputs are each connected to one of the outputs of the T-trigger for the negated signal and their set inputs with said Connection point are connected. The phase comparator has a third and fourth output and is formed from a second and from a third NAND gate. The first input of the second NAND gate is connected to the output of the first T-trigger for the ungated signal, the second input of the second NAND gate to the output of the second T-trigger for the negated signal and the third input of the second NAND gate. Gates led to the said connection point. The inputs of the third NAND gate are interconnected as follows: the first input is at the output of the second T-trigger for the ungated signal, the second input is at the output of the first T-trigger for the negated signal and the third input is at said one Connection point connected. The outputs of the second and the third NAND gate, the negated third and fourth output signal for the phase comparison can be removed.

According to the invention, a fourth NAND gate is provided, whose one input is connected to the first output of the frequency comparator, whose other input is connected to the output of the first T-trigger for the negated signal and whose output is connected to the set input of the first T-trigger. Furthermore, the invention provides a fifth NAND gate whose one input to the second output of the frequency comparator whose other input is connected to the output of the second T-trigger for the negated signal and whose output to the set input of the second T-trigger.

An expedient embodiment of the invention provides for an inserted between the output of the first NAND gate and said connection point RS trigger whose output for the negated signal to the connection point whose set input to the output of the first NAND gate and its reset input to the Output of a sixth NAND gate is connected, which links the outputs of the two T-trigger for the negated signal. All of the triggers listed above are bistable multivibrators. Their set and reset inputs become active when a logical 0 is applied, their other inputs at logical 1, or at transition from a logical 0 to a logical 1. All set and reset inputs have a higher priority than the other inputs of the same trigger.

In the default state, the T-triggers and the RS-triggers are reset, the D-triggers are set and both input signals are inactive. The first active input signal sets the respective T-trigger, activates the corresponding third or fourth output signal and blocks the fourth or third output signal. The first and second output signals remain inactive. For example, if the first input signal first arrives, then the first T-trigger is set, the third output signal is active, and the fourth output signal is blocked. For the further course of time there are now two cases:

- It enters the second input signal and sets a second T-trigger. The consequence of this is the inactivation of the third output signal and the formation of the set signal for the RS trigger, whose output for the negated signal now takes over the blocking of the outputs of the second and the third NAND gate and the T triggers back to their ground state brings. Only by the resetting of the T-triggers the reset signal for the RS-trigger arises and the entire frequency and phase comparator is back in the ground state or

- It re-enters the first input signal and resets the first T-trigger itself. The result is activation of the first output signal, resulting in the formation of the set signal for the first T-trigger to render the third output signal active again, thus bringing the functional unit phase comparator back to the state it was in before the first input signal reappeared. The process just described is repeated until at some point the second input signal arrives.

The frequency and phase comparator according to the invention provides interference-free third and fourth output signals, since these signals are connected together by means of the second and the third NAND gate. Even with unequal frequencies of the input signals, the third and the fourth output signal are error-free, since the T-trigger reset by the higher-frequency input signal is reset immediately by means of the fourth or fifth NAND gate. Another advantage of the invention is that the sowing stages used for their realization do not have to meet any special switching time conditions, which has been achieved by using the RS trigger. Since this is only reset by resetting both T-triggers themselves, an output for the negated signal inevitably leads to the required logical 0 until the T-triggers have been completely reset.

embodiment

The invention will be explained in more detail below on an Agsführungsbeispiei. In the accompanying drawing show:

Fig. 1: the schematic diagram

Fig. 2: associated signal waveforms for input signals of the same frequency

3: associated signal waveforms for input signals of different frequency.

The following explanation of the exemplary embodiment relates to FIG. 1. The output 1 of the non-negated signal D trigger 2 connected as a T trigger is connected to an input of the NAND gate 3 and to an input of the NAND gate 4. From the output of the same D-trigger 2 for the negated signal, a connection leads to one input of each of the NAND gates 5; 6; 7 and the clock input of the D-trigger 8.

Analogously, the output 9 of the non-negated signal connected as a T-trigger D-trigger 10 is connected to one input of the NAND gates 3 and 7. The output of the same O-trigger 10 for the negated signal is each with an input of the NAND gate 4; 6; 11 and connected to the clock input of the D-trigger 12. The D inputs of the D-triggers 8 and 12 are at zero potential. The output 13 of the NAND gate 3 is connected to an input of the NAND gate 14 and the output 15 of the NAND gate 6 is connected to an input of the NAND gate 16. The NAND gates 14 and 16 are interconnected to an RS trigger, and the output 17 of the NAND gate 16, which is the output of the RS trigger for the negated signal, connects to one input of the NAND gates 7 and 4, respectively to the reset inputs of the D-triggers 2 and 10 and to the set inputs of the D-triggers 8 and 12. The output 18 of the NAND gate 5 is at the set input of the D-trigger 2 and the output 19 of the NAND gate 11 is connected to the set input of the D-trigger 10. The output of the negated signal D-trigger 8 is connected to an input of the NAND gate 5, and the output of the negated signal D-trigger 12 is connected to an input of the NAND gate 11. The frequency and phase comparator supplied two input signals 20,21 are applied to the clock input of the D-trigger 2 and the D-trigger 10 at. The first output signal in negated form is at the output 22 of the D-trigger 8, the second output signal in negated form is at the output 23 of the D-trigger 12, the third output signal in negated form is at the output 24 of the NAND gate 4 and the fourth Output signal in negated form can be tapped at the output 25 of the NAND gate 7. All set and reset inputs of the D-triggers have a higher priority than the corresponding clock inputs.

In the exemplary embodiment, a positive logic and the usual assignment are assumed, d. h., high level corresponds to a logical 1 and low level to a logical 0. All set and reset inputs are low active. All D-triggers are edge-triggered with respect to the low-high edge of the clock. In the ground state, the D-triggers are 2; 10 and the NAND gate 14; 16 reset RS triggers are reset and the D triggers 8 and 12 set, whereby all negated output signals are high and thus inactive.

The dynamic operation of the frequency and phase comparator is illustrated in FIGS. 2 and 3. The following statements relate first to FIGS. 1 and 2:

If, for example, the low-high edge of the second input signal 21 arrives, then this sets the D-trigger 10. The signal 26 at its output 9 assumes high level, whereby the negated fourth output signal 27 at the output 25 of the NAND gate 7 active is, ie, goes to low level. If equality between the input signals 20 and 21 is present, the low-high edge of the first input signal 20 must appear before the next low-high edge of the second input signal 21 and set the D-trigger 2, the signal 28 at its output. 1 High level. The consequence of this is a high level at the output 25 of the NAND gate 7, d. The above-mentioned transition of the signal 28 to high-level further results in the signal 29 at the output 13 of the NAND gate 3 transitioning to low level, whereby the signal output from the NAND gates 14; 16 established RS trigger is set, the signal 30 at the output 17 of the NAND gate 16 thus assumes low level. The signal 30 sets by its low level, the D-trigger 2; 10 back, with the signals 26 and 28

switch back to low level. Signal 30 continues to block the outputs 24; 25 of the NAND gate 4; 7, so that the negated third output signal 31 at the output 24 and the negated fourth output signal 27 at the output 25 continue to lead high level. During the resetting of the D-triggers 2 and 10, a low-high edge occurs at the clock inputs of the D-triggers 8 and 12 each time. Since, however, at this time at the set inputs of the D-triggers 8 and 12, the low level of the signal 30 is applied, the said low-high edges do not lead to the writing of a logical zero in the two D-triggers 8 and 12. The output, frequency equality After the resetting of the D-triggers 2 and 10, the signal 32 at the output 15 of the NAN D-gate 6 leads to low level, whereby the RS-T trigger consisting of the NAND-gates 14, 16 is reset the ground state of the frequency and phase comparator is restored.

The following statements relate to FIGS. 1 and 3: If two low-high edges, for example, of the second input signal 21 appear in succession, the first sets the D-trigger 10 and the second sets it back again, as a result of which the course of the Signal 26 at its output 9 results. The said reset of the D-trigger 10 is thus carried out without a reset signal, d. H. a low level signal 30, to its reset input. The resulting during the resetting of D-trigger 10 low-high edge at the clock input of the D-trigger 12 in this writes a logical zero (transition of the negated second output signal 34 to low level at the output 23) and thus allows the formation of a signal 33rd at the output 19 of the NAND gate 11, which leads to the setting of the D-trigger 10. The setting of D trigger 10 reverses the signal 33 itself. If this feedback was missing from the D trigger 12 via the NAND gate 11 to the D trigger 10, then the D trigger 10 would remain reset. A now arriving low-high edge of the first input signal 20, which sets the D-trigger 2, would activate the negated third output signal 31 at the output 24 of the NAND gate 4 and thus an incorrect phase relationship between the two input signals 20; 21 pretend.

Claims (4)

1. Digital frequency and phase comparator with a first and a second T-trigger, with a first NAND gate whose two inputs are connected to the outputs of the two T-triggers for the ungated signal and whose output is connected to a connection point which is connected to the reset inputs of the T-triggers, and to a frequency comparator having a first and a second output and preferably consisting of two D-triggers whose D inputs are at a potential corresponding to a logic 0 whose Clock inputs are each connected to one of the outputs of the T-trigger for the negated signal and whose set inputs are connected to said connection point, the phase comparator having a third and fourth output and a second NAND gate whose first input to the output of first T-trigger for the non-negated signal, whose second input is connected to the output of the second T-trigger gers for the negated signal and whose third input is led to said connection point and from a third NAND gate, whose first input to the output of the second T-trigger for the ungated signal, whose second input to the output of the first T-trigger is formed for the negated signal and whose third input is connected to said connection point, characterized in that a fourth NAND gate (5) whose one input to the first output of the frequency comparator (8; 12) whose other input is connected to the output of the first T-trigger (2) for the negated signal and whose output (18) is connected to the set input of the first T-trigger (2), and a fifth NAND gate (11 ), whose one input to the second output of the frequency comparator (8; 12), whose other output to the output of the second T-trigger (10) for the negated signal and whose output (19) to the set input of the second T-trigger ( 10) is turned on, are provided. 2. Digital frequency and phase comparator according to item 1, characterized in that between the output (13) of the first NAND gate (3) and said connection point, an RS trigger (14; 16) is inserted, whose output (17) for the negated signal to the connection point, the set input to the output (13) of the first NAND gate (3) and the reset input to the output (15) of a sixth NAND gate (6) is guided, which outputs the two T -Trigger (2; 10) for the negated signal linked together. For this 2 pages drawings Field of application of the invention The invention relates to a digital frequency and phase comparator, which can be used as an indicator circuit, in frequency and Phasenmeßgeräten or as an integral part of a phase locked loop (phase-locked-Ioop, phase-locked oscillator). The use of a phase-locked loop is possible in many fields of technology, for example as frequency modulator, as tracking and phase-synchronous filter, as frequency multiplier and as synchronization circuit, as used in television technology for synchronizing the line frequency generator with the line sync pulses. Characteristic of the known technical solutions Known technical solutions generate four periodic output signals from the two periodic input signals. The first output signal is associated with the functional unit frequency comparator and indicates that the frequency of the first input signal is greater than the frequency of the second input signal. The second output signal also assigned to the functional unit frequency comparator signals the inverse frequency relationships between the two input signals. The third and the fourth output signal are assigned to the functional unit phase comparator and result from the implementation of the phase relationship of the two input signals in a proportional pulse length. Depending on the sign of the phase relationship between the two input signals, either only the third and the first or only the fourth and the second output signal may be active. Known technical solutions do not fulfill this research in principle at any time. If the frequencies of the input signals are unequal, this is recognized by a prior art frequency and phase comparator only with the disadvantage of the false formation of the third and fourth output signals, or it provides third and fourth output signals which are noisy. The following statements assume a positive logic and the usual assignment, i. h., high level corresponds to a logical 1 and low level corresponds to a logical 0. Known is a phase comparator (Federal Republic of Germany Offenlegungsschrift No. 2707130, described in the prior art), consisting of two clock edge-controlled D-triggers with reset input and a NAND gate with two inputs. The outputs of the two D-triggers for the non-neglected signals provide the third and fourth output signals, respectively. The output of each non-negated signal D-trigger is connected to one input of the NAND gate each. The level of the output of the NAND gate is applied to the reset input of both D-Triggers. The reset input has a higher priority than the clock input. For both D-triggers the D-input is set to high level. In the basic state, both D-triggers are reset. If the frequency equality exists between the two input signals, then the first incoming low-high edge of an input signal sets the corresponding D-trigger and one of the two output signals is thereby activated. The low-high edge of the other input signal, which arrives later by a certain phase difference, now also sets the other D trigger, but thus causes a low level at the output of the NAND gate, which leads to the resetting of both D triggers. The phase difference of the two input signals was thus converted into a corresponding pulse duration, and the sign of the phase difference can be seen at the number of the output of the phase comparator. Inadmissible, however, is the reset (Nl CN CSI CSI. FIG. 21 20 26th 28th 32 27 H L H L H L H L H L H L H L H L Fig. 2 21 28H
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