CZ712489A3 - Quick-acting analog-to-digital converter - Google Patents

Description

BACKGROUND OF THE INVENTION The present invention relates to an instantaneous analog-to-digital converter which is useful in integrated circuits for the rapid conversion of analog to digital quantities, in particular in image technology.

With the current possibilities of fast digital data processing, there is a great need for analog-to-digital converters operating at extremely high speeds.

Flash analog-to-digital converters are described in a number of literary sources. For very high transmission speeds, circuits with exclusively bipolar transistors are used, but have the disadvantage of very high power dissipation and high space consumption. This leads to low substrate yields and hence high production costs. An example of such a transducer is described in German Patent No. 30 09 434.

CMOS converters for this purpose, which can be produced with higher yields, do not have the disadvantages mentioned, but do not achieve as high transfer rates as instantaneous converters with bipolar transistors. The reason for the slower conversion rate is the delay times due to decoding, which are relatively high in MOS circuits due to the used N-channel NOR matrices. The capacity of the bit lines, which is itself large, is further increased by the parasitic capacities of the necessarily large N-channel transistors. This leads to an additional dynamic power loss at high transmission speeds. Using large N-channel transistors is for decode

The benefit of the space-saving MOS technology is greatly limited by logic logic. Instantaneous transducers of this type are described in IEEE JSSČ No. B, 1986, page 436 et seq., And No. 6, 1986, page 976 et seq.

Recently, technological development has become known which gives the possibility to integrate bipolar and unipolar structures into a monolithic circuit and thus combine the advantages of both structures. However, for the instantaneous converters, no circuits have yet been developed in BICMOS technology that would effectively take advantage of known CMOS circuits to reduce dynamic power dissipation while increasing conversion speed. This issue is pointed out in IEEE JSSC δ. 1, 1988, p. 5 et seq.

Fčeíea invention embodies t - via flash-great-cuýí _CI ^ y nizkoztráto instantaneous analogue or sITcbvý / převOdiríkj krtery ^ | it needs space in the dark, allowing for P-kenniai production.

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An analog-to-digital converter providing high speed analogue or slice conversion at low power loss and having small encoders.

According to the invention, two N-channel transistors from the two phases are excited after the processing of the signals from the comparators and the pM-GMOS signal. The base of transistor tranaiotory -ovládaji ^- typuC-Ί mg >>

The purpose of the invention to provide an analog to digital converter to ^T b3 ensure a high speed analog-to-digital conversion with low dynamic power dissipation and yet have small dimensions.

The subject of the invention is a instantaneous analog to digital converter consisting of komoarators, reference voltage dividers, a clock, a decoding logic and a product circuit. SUMMARY OF THE INVENTION The CMOS inverter input and the gate electrode of the first K-channel transistor, whose emitter is grounded and whose collector is connected to the base of the first HPN transistor and to the emitter lead, are connected to the output of the successive comparator circuit. a second N-channel transistor; the gate electrode of the second / io M-channel transistor is connected to the CMOS inverter output and the collector of the second N-channel transistor is connected to the collector of the first NPN-transistor whose emitter is grounded and to the emitter of the second NPN-transistor whose collector is connected operating voltage. The clock is connected to the clock input of the product circuit and the input of the input inverter whose output is connected to the base of the second NPN transistor.

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The resolution of the instantaneous transducer determines the number of elements described, whereby the delay inverter and its controlled filtering is spelled for / the entire column of the installation: ”Also circuit ^: the clock power is only one. With the arrangement according to the invention, it is achieved that during the decoding phase of the cooparator signals, the parasitic loading capacity of the bit conductor discharges very quickly. Due to the current amplification of NPK transistors, N-channel transistors have to supply only very small control currents and can therefore be minimized in area. At the same time, the parasitic capacity can be reduced by using relatively small bit conductor discharge MPN transistors, which leads to a decrease in the dynamic power loss. The reduced surface area of the NFN transistors is possible due to the higher surface slope compared to the transistor / KOS. In addition, in the arrangement according to the invention, the control current for discharging the capacity of the bit conductor is directly available from that capacity and does not require any additional base current generation. By this, the static and dynamic power losses are further reduced.

Another advantage of the solution according to the invention is that the use of a delay inverter, which again controls the KRK transistor, allows optimum clocked operation to reduce static power loss at the same time with a very short charging time of the bit conductor capacity and a very small required area. These measures increase the conversion speed.

In Figure 1, one row and one column of the total matrix circuit of the instantaneous analog-to-digital front is indicated

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The outputs of the three comparators K, which by their first input are connected to an input voltage IN ε of the second input with voltage reference dividers R, lead to a power supply circuit 1, whose inputs are additionally connected to a clock 8 and a delayed inverter input 6. 1 is connected to the input of the CMOS inverter 2, the output of which leads to the gate of the second Ν-channel transistor 3, the emitter of which, together with the collector of the first N-kennel transistor 4, is connected to the base of the first NPN-trenzistor. the channel transistor 4 is coupled to the input of the CMOS inverter 2 while its emitter is grounded.

The collector of the second N-transistor 1, the collector of the first NPN-transistor 5, whose emitter is grounded, and the load capacitor C is fertilized with the emitter of the second NPH-transistor 7, whose collector is connected to operating voltage, and its base is connected to the output delay inverter 6.

Comparators K are comparative circuits, which in one step compare the input voltage ns of the input

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IN with reference values generated by the -R reference voltage divider. The number of 'comparators'K depends on the resolution of the converter. The thermometer code generated by the comparators is unsuitable for digital processing and must therefore be converted to another code form. This transmission is realized in the indicated design by a matrix circuit. The connection of three consecutive comparators to the clock is performed by the product circuit 1. This is controlled by the inverter 2

- ¢ COS, which provides a negated signal. Output: SKOS inverter 2 controls the second N-channel transistor 3, while the first N-channel transistor 4 is controlled by the product circuit 1. During the decoding phase, the clock signal from clock 8 via delay inverter 6 disconnects the second BPP-transistor 7. First PPN-transistor 5 in this phase, it receives a base current through the second P-channel transistor 3, which is only taken from the capacitor C and discharges the capacitor 1 with its collector current. Due to the high current gain of the first MPI1 transistor 5 ^, · very short decoding time. Static current is not generated because the second NPK transistor 7 is disconnected.

When the clock signal is switched, the new read value is decoded. In this case, the load capacitor C is quickly charged via the inverter 6, and the first M-channel transistor 4 closes at this instant the first NPM transistor 5, so that no static current is generated again. The delay of the inverter 6 is set so that the shutdown of the first NPP transistor 5 occurs before the second PPI 'transistor 7 is turned on, so that the dynamic power loss is minimized.

Claims (2)

A snap-in analog-to-digital converter consisting of comparators, reference voltage dividers, clock, decoding logic, and a product circuit, characterized in that an inverter input is connected to the output of the product circuit (1) of successive comparators (K). (2) CMOS and gate electrode of the first N-channel transistor (4), whose emitter is grounded and whose collector is connected to the base of the first NPN transistor (5) and the emitter supply of the second N-channel transistor (3); a second N-channel transistor (3) is coupled to the inverter output (2) The CMOS ..... and the insulator of the N- N -aluminated iris (3) is connected to the collector of the first NPN-transistor (5) whose emitter is grounded and to the emitter of the second NPN-transistor (7) whose collector is The clock (8) is connected to the input of the product circuit (1) and to the input of the delay inverter (6), the output of which is connected to the base of the second NPN transistor (7).