CZ349699A3 - Expansible telecommunication system - Google Patents

Abstract

An open, high speed, high bandwidth digital communication network for connecting multiple programmable telecommunications switches to form a large capacity, non-blocking switching system. Each network switching node includes circuitry for transmitting and receiving variable-length, packetized information over the network, thus enabling each node to receive information from or transmit information to all other nodes. The network may carry any type of information present in the system including voice, data, video, multimedia, control, configuration and maintenance, and the bandwidth of the network may be divided or shared across various information types. Devices such as voice processing resources may also interface with the network, thereby gaining direct access to all information passing through the network. Also provided are methods and packet structures for communicating information over the network. Multiple networks may be interconnected to provide even greater switching capacity or voice processing capacity.

Description

Extensible telecommunication system

Field of technology

The invention relates generally to the field of telecommunications, in particular to the construction of a connection system capable of connecting a plurality of programmable exchanges, thereby creating an expandable connection system and direct access for various connection applications.

Prior art

The main consideration when designing any telecommunication system is its interconnection capacity. The connection capacity must be analyzed in terms of current requirements and projected needs in order to find a solution that would be cost-effective for both current and future use. Consider, for example, a developing country that is building a basic telecommunications system and wants to provide services to the majority of the current population. At the same time, this population is probably geographically divided into small, high-density areas (cities) and larger, low-density areas (small towns and countryside). In addition, the population is growing, but at different speeds in different areas. This requires the telecommunication system designer to design sufficient interconnection capacity to provide sufficient service for most or all of the population, and in addition, the designer must take into account the likely increase in requirements in the future due to economic expansion.

Another example of difficulty in designing adequate connection capacity involves wireless or personal communication network (PCN) applications. These types of applications are based on a microcellular architecture, which requires many base stations located at a distance, physically close to each other within the urban development, with different interconnection capacities that are grouped into large capacities.

The second basic consideration in the design of a telecommunications system is «♦ i i 4» '1 <«i <« 1 consideration of the possibility of using new technical elements for the services provided in the future. Telecommunication equipment and services are evolving very fast, thanks to digital technology. A lot. more dramatic progress is likely to be expected in the future, given the integrating services of formerly local cable TV and telephone companies. Once again, there is a need to create a system that economically serves today's needs, while being able to flexibly and cost-effectively integrate new features and services that will be available in the future.

The usual approach to this dual problem, ie the provision of> · adequate interconnection capacity, with the current possibility to include new elements and services, has two main disadvantages: 1) the system does not have enough bandwidth to process video or multimedia information (except voice and give); 2) there is no direct and easy access to all the information entering or leaving the system, which means that there is no way to capture all the information and distribute it to other interconnection systems or devices; 3) access to some types of higher services requires a very large exchange.

One common approach concerns, in short, the so-called extended bus (node) access. ”In many conventional telecommunication exchanges, one internal bus (or more internal buses) is equipped to transmit information, including voice signal, data or control information. between different parts of the control panel. Busses are very suitable for such information transmission because, by definition, multiple devices (i.e., circuit boards or cards) can interface with the buses and share them in accordance with a defined connection protocol. In telecommunication exchanges, one or more buses can be found, which interconnect a series of cards that physically terminate telephone lines or trunks with other cards that perform switching, control or other functions.

As the term in quotation marks indicates, it has expanded

0

0 00 "0 · 0 · 0000 bus to connect additional cards, which provide additional switching capacity ^Λ or other functions with the existing buses.

Along with the previously mentioned main disadvantages, there are still - other disadvantages. First, there are physical limitations on the number of cards that can physically connect (or share) the bus without degrading system performance. Second, in order to ensure the future expansion of the system, the bus and other parts of the system must be designed primarily to handle much more traffic than existed before the expansion of the system. These * limitations relate to the electrical and mechanical characteristics of the buses (or at least one particular bus) and their * effective operating speeds. Attempts to overcome these limitations (by consuming an excessive number of bus connections) lead to increased costs and complexity of the base, or to a non-extensible system, where this system would be considered too expensive for some applications. Another limitation concerns the operating power, for the actual provision of the switching functions, as well as the control of the operation on the buses.

Third, the bus structure, which can be found in many, if not most, conventional connection systems, is designed only to perform basic talk, operation, and switching functions and does not provide easy and direct access to ports to integrate new features and services. .

Fourth, bus structures are not capable of transmitting packetized connection data or other types of information.

The second approach may refer to the modular approach for short. According to the modular approach, the idea is to provide a connection system that is constructed from a series of substantially identical modules. Each module

I provides a finite number of connection capacities that can be added to an existing system (one or more at a time) to increase the overall capacity of that system.

In addition to the main disadvantages already mentioned, the modular approach has other shortcomings. In order to provide fully non-blocking operations, each and all modules thus manufactured must have • 4 • 4 · • 44 44

444 • 4 4 44 «• 4 ♦ · 44 the ability to receive circuit switching data from each additional module, up to the maximum number that can occur. In hardware terms, this means that each module must have a large enough memory to store the maximum amount of circuit connection data that can be received with the maximum number of interconnected modules. For example, if each module is able to connect (close) 64 ports and a maximum of 8 modules can be connected to each other, then each module must contain a memory that will be able to store circuit connection data for 8 x 4 = 32 ports. According to the modular approach, it is the maximum connection capacity of a fully extended system that determines the amount of memory that each module must have. In larger systems (on the order of several thousand ports or larger), the creation of such memories is impractical, both due to the high number of physical network / interface lines and also due to the need to have additional memory control circuits.

Second, in order to maintain a true modular system, it is not possible to change the capacity of the individual modules.

Third, as with the extended bus approach, the modular approach is focused on performing basic switching operations and generally does not offer direct access to all ports or the ability to process packetized connection data or other types of information.

The essence of the invention

Briefly, the present invention provides an open, fast, broadband, digital communications network for connecting multiple, programmable telecommunication exchanges to form a high-capacity non-blocking interconnection system. In a preferred embodiment, the network is implemented by using one or more circuits that form a medium for transmitting information in the network, as well as a plurality of programmable exchanges (switches), each of which acts as a network node and serves a group of ports. They can join the network

add additional exchanges (nodes) if we are considering increasing the connection capacity.

Each node includes a remote transmission circuit for transmitting and receiving packetized information of variable length within the network, each node being able to receive information from all other nodes as well as send information to them. The network can transmit any type of information contained in the system, including voice signals, data, video, multimedia information, control information, network configuration and maintenance information, and the network can be divided into or share different types of information.

In addition, devices and resources other than programmable exchanges can act as nodes in the network, giving them direct access to all the information that passes through the network. More specifically, voice processing resources, such as a voice mail system or other higher service, can become nodes with direct access to the ports of that system without the need for a large PBX. The ability of the present invention to transmit information of any type in an easy-to-use form and at a high data rate in a network allows any service, shape or source of voice signal processing on a given node to be connected to any port of that or another node.

The present invention also provides methods and packet structures for communication information in a network. In general, it provides various packet structures for circuit communication, data and maintenance information. All packets contain a header control part, which usually contains addresses, status and other control information, and a part of paid data services. The combination of direct access to all ports and the ability to transmit information in the form of a packet is highly compatible with ATM asynchronous transfer mode operations in the SONET (synchronous optical network).

In accordance with one method of transmitting information between nodes, each node uses a network to transmit one or more packets, each having an empty portion of paid services, the information of which is first received by a neighboring node. The neighboring node determines the source of the received packet and its status, using the information contained in the control part of the packet. If a neighboring node has information to send to the node transmitting the packet, the neighboring node inserts such information into the payload portion of the packet, allowing the packet to pass to the next neighboring node in the network. If the neighboring node does not have information for the node with the packet, the packet simply passes to the next neighboring node in the network. This process is repeated for each node until the packet traverses the entire network and returns with the full payload to the node from which it originally originated. At this point, the information inserted into the packet by other nodes is captured by the node in which the packet originated. Alternately, each node transmits an empty packet that has passed through the network and returns with information from other nodes. In this way, information of any kind, generated on any port served by any other node, can be transmitted to another port of the same or another node in the system.

In accordance with an alternative method of transmitting information between nodes, each node uses a network to transmit one or more packets, each of which has a full payload portion that contains information generated at that node. Each such packet is first received by a neighboring node, which determines the origin of the packet and whether any information contained therein is needed for the neighboring node. If it is not needed, the packet simply passes to the nearest neighboring node. This process is repeated until each node in the network has transmitted one or more full payload packets, and each such packet has passed through the entire network, allowing each node to access the information generated by each other node.

Using each of the information transmission methods of the present invention, the information transmission capacity of each node is determined independently of the other nodes. The given node only has to contain a sufficiently large memory that could accept the connection capacity (voice signal processing) and not the whole ··· 999

9 9 ·· 99

9

9 »· system capacity.

In another embodiment of the present invention, a second circuit is used to interconnect all nodes, thereby forming a second network. This second network effectively doubles the maximum connection capacity of the system and also provides fault protection in the event of a first network failure.

In another embodiment, according to the invention, there are additional networks added to the existing nodes, which again increases the maximum connection capacity of the system.

In another embodiment, in accordance with the present invention, one or more nodes may be used to bridge one network with another. Network bridging is common to both networks and is capable of exchanging information in both directions between these networks. Node bridging can also be used to connect networks that operate at different speeds.

Overview of pictures in the drawing

The features of the invention are emphasized in the appended claims. These and other advantages will become more apparent from the description and accompanying drawings, in which;

Figures 1A and 1B show a flow diagram of an extensible circuit-type telecommunications system that uses a network of interconnected nodes to transmit information between programmable interconnection nodes; Figures 1E shows various types of packets that may be used to transmit information in the networks of Figure 1A. to 1D, FIG. 2A shows a flow diagram of a programmable connection node that may be used in the systems of FIGS. 1A to 1D, FIGS. 2b and 2C show a flow diagram of a second type of programmable connection node that may be used in the systems of FIG. to ID, Figs. 3A, 3B, 3C, 3D and 3E show a flowchart of the connecting node shown in Figs. 2A to 2C, * φ · «* φ · ΦΦ · • φ • Φ φφ φφ

Fig. 3F is a more detailed diagram of the transmit and receive memories shown in Figs. 3B and 3C, Fig. 4A is a flowchart illustrating receive and transmit functions included in one method of transmitting information in a network with interconnected nodes of Figs. 1A to 1D; Fig. 4B is a circuit diagram showing more detailed steps of transmitting circuit connection information in accordance with the method shown in Fig. 4A; Figs. 4C and 4D are a circuit diagram showing more detailed steps of transmitting both circuit connection and packet data. of connection data, in accordance with the method shown in Fig. 4A, Fig. 4E is a time diagram showing a time relationship between nodes in transmitting both circuit connection data and packet connection data, Fig. 5A is a flowchart showing a second method The transmission of information in a network with interconnected nodes according to Figs. 1A to 1D, Figs. SB and 5C show a circuit diagram showing more detailed transmission steps as a connector. Both circuit data and packet connection data according to the method shown in Figs. 5A, Figs. 6A and 6B show a flow diagram of an extensible telecommunication system showing how a connection can be maintained in the event of a fault on one, programmable node or part of a network. with interconnected nodes, Fig. 7 shows a flow diagram of another embodiment according to the invention, which uses two two-circuit networks with interconnected nodes, one as a backup for information transfer between programmable connection nodes, Figs. 5A and 8B show a flow diagram of another embodiment according to this invention. of the invention, which uses a network of interconnected nodes to transmit information to one or more programmable nodes and one or more source nodes that process voice signals; ·· «Φ · ··· * ·» • φφφφ • · φφφ ΦΦ · • φ « φφ φφ Fig. 8C shows a flowchart of a source node processing voice signals according to Figs. 8A and 8B, Figs. 9A and 9B show a flowchart of another an embodiment according to the invention which uses a programmable connection node as a bridge between two networks with interconnected nodes, Fig. 9c shows a flow chart of the node serving as a bridge according to Figs. 9A and 9b, Fig. 10A shows a flow chart of another embodiment according to the invention, which uses eight circuits to transmit information between programmable interconnection nodes, thereby demonstrating further extensibility of the interconnection system, Figs. 10B and 10C show a flow diagram of one interconnection node of Fig. 10A.

Examples of embodiments of the invention

Figures 1a and 1B show a large capacity, expandable, fully programmable telecommunication connection system 2- System 2 comprises a HOST (host Computer) 4 and a series of programmable connection nodes 6a-6h. Each of the connection nodes has a master computer interface (hereinafter HOST), which is connected to HOST 4 via a local area network (LAN), such as Ethernet, or via asynchronous multiple connection lines 2 (RS-232). Of course, other HOST / node interfaces can be used instead of (or as an option) 8 LAN / RS-232 lines. Although only one HOST is shown, using LAN 8 for a HOST / node connection allows multiple HOSTs to be used to control System 2 (or part thereof), in an arrangement where each HOST is a client and each node is a server. To improve the intelligibility of the drawing, the HOST interface of nodes 6a and 6f-6h is grouped into a bus.

Each of the nodes 6a-6h includes a digital network / line interface for connection to the public switched telephone network (PSTN) or to the private network 10. The term private network in the broadest sense refers to any network

4 *

4

4 ·· 444

444

4 4

4 4 ·

4 «• 44 44

or a line or interface other than the PSTN. Again, for the sake of clarity, the network / line interfaces of nodes 6b-6e are grouped into a bus. As shown by representative node 6g. the network / line interface can terminate either a digital network or analog buses / lines, or a combination of both. The network / line interface of a given node may include suitable interfaces for the operation of communications using ATM (address converter memory), signaling system 7 (SS7), ISDN (Integrated Services Digital Network), Tl / robbed bit, El / CAS, or other communication protocols.

Node 6g is the named master node A (active master node) and the node 6h is the named master node B (backup master node). A synchronization line (ref 1 .... ref n) extends from the active master node 6g to each connection node, although some such lines are grouped into a bus for clarity. As will be explained in more detail below in connection with Figs. 3A to 3E, any of the nodes 6a-6h may be arranged as an active master node or as a backup master node. There can be one and only one active master node at a time.

Nodes 6a-6h are interconnected by a network of interconnected nodes 12, which provides a digital connection between the nodes, a high speed, high bandwidth connection. As shown, the network 12 may be implemented using circuits that allow each of the nodes 6a-6h to exchange packet information with another node within the network 12. The network 12 may also be implemented using various other types of communication networks. including Ethernet and other types of LAN, using wireless communication networks and PSTN (ATM / SONET). The use of a PSTN on network 12 allows nodes to be geographically distributed over a large area.

The main packet structure 14 for exchanging information over the network 12 consists of a control portion, a payload portion 18, and a status and control portion 19. In more detail, various packet structures for transmitting various types of information are described below using FIG.

If network 12 is used, the port of the given node can be connected to * * 9 9 * 999 9 * 9

9 «9 99 • 99 94« ·· 999 «|| , * to any other port on the same node, in a completely non-blocking manner. In the preferred embodiment, a total of eight connection nodes 6a-6h are interconnected by a network 12, and if all bandwidths of the network 12 are used to transmit circuit connection data (circuit switching data), the system 2 is able to connect (close). (8 x 2048) = 16384 ports, which is equal to 8192 simultaneous two-way calls.

It is clear that each of the nodes 6a-6h operates independently with respect to the network / line interface that terminates on them. That is, each node can be removed from or added to the network 12 without compromising the operations or network / line interfaces of the other nodes. The interconnection capacity of each node can be set up independently of the interconnection capacity of the other nodes (i.e. small exchanges can be combined with large exchanges, in the same network 12) - Thus the total interconnection capacity of system 2 can be increased simply by adding another node, which has its limitations regarding the data rate in the network or networks 12, as will be described below.

The overall operation of the system 2 is controlled by the main computer 4 (HOST 4), which is implemented by means of a PC, a workstation, a fault-tolerant computer and another computer running the user's application software. HOST 4 and each of nodes 5a-6h exchange messages over LAN / RS-232 lines 8. These messages are used to configure nodes and direct call processing functions, such as establishing a connection and providing connection services (tone detection, tone generation, and conference connection).

Figures 1C and 1D show an expandable communication system 17 * which is similar to the system 2 in Figures 1A and 1B, except that two circuits are used to form the network 12 connecting the nodes 6a-6h. The PSTN / private network is omitted for clarity. The same reference numbers are used to identify the same components or steps in the other figures. Conceptually, each of these circuits can be considered as a separate network (or alternatively as separate channels within one network), as • 4

4 • 4 4 4 4 4 4

4 4 4 444 444

4 * * ·

444 44 4 * 44

4 «4 4 * 4 444 information transfer between nodes can be realized by using on each other. independent circuits, effectively doubling the maximum interconnection capacity compared to system 2. The use of two circuits also isolates faults in system 12. This means that if one circuit fails (which for single circuit system 2 means that becomes inoperative), the second circuit can continue to transmit information between nodes, which means that the system remains at least partially operational.

Fig. 1E shows an embodiment of several packets that can be used to transmit information in the network 12. The data packet of the link circuit 2 and the voice signal processing packet 5 are constructed in a similar way and each comprises a control part which includes a busy tone indicator (BI). busy indicator), followed by address information and control information. The indicator can be used, as will be described in more detail, to indicate the current status of a given packet, where busy means that the node cannot use the packet to transmit information, or that it is possible to use it freely.

The address information includes the address of the source node (SRC) where the packet originated, or the destination node (DEST) for which the packet is intended, or both. Each address (source or destination) includes a network address that uniquely identifies a particular network. Such identification is necessary because, as will be described later, multiple networks with interconnected nodes can be used to interconnect the same or different groups of nodes. Each address (source or destination) also includes a node address that uniquely identifies a particular node on a particular network. Additional address information may include

L explicit port address, for unique identification

Even a specific port or groups of ports.

I In general, packets 1 and 5, which carry circuit connection data, require port addresses, as such data is dependent on distribution across multiple nodes and / or ports. As an alternative to an explicit port address (which in the context of large connection systems would represent thousands apartments

0 • · • · · »0 0 • 0 00 * β» 0,000 additional information carried by the packet), the Default Port Address can be determined by maintaining a predetermined order of circuit connection data within the payload. For example, packets 1 and 5 are described as having sufficient payload capacity to carry a total of 2048 bytes of circuit connection data. After placing these bytes in the paid part, they are arranged in an order that exactly corresponds to the sequence of time slots at a given node. The byte of the connection data of the circuit, which corresponds to the first time interval (time interval (TS) 0) of the given node, is placed first in the paid part and is followed by the remaining bytes in sequential order.

In this arrangement, any node can insert or remove circuit connection data from the payload by simply calculating the position of a particular byte relative to the first byte in the payload, knowing exactly the time slot to which the byte corresponds.

Conversely, packets 7 and 9 generally do not require a port address, as the information transmitted by these types of packets is not circuit connection information.

Additional information may be included in the control section 16 to specify the packet type, packet length, packet sequence number, and other information.

The length, or capacity, of the payload portion of each type of packet may vary depending on which node is transmitting the packet. For example, the capacity of the payload portion of packets 2 and 6 may vary as long as it provides sufficient circuit link data transmission capacity to the maximum number of ports that are connected or processed by a given node. Thus, if a particular node is able to connect or process a maximum of 2048 ports, then that node transmits packets 3 and 5 with a payload having a capacity for circuit connection data, up to 2048 bytes. Similarly, if another node is able to connect only 512 ports, then that node transmits packets 2 and 5 with a payload capacity to 512 bytes of circuit connection data.

Paid portions of all packet types are followed by status and control information, which may include a checksum

”·· · · 9 · 9 9 • 9 9 9 9999 • * · 9 9« 999999 • · 9 9 · «··· 999 99 99« 9 or other information for errors and corrections.

Packet connection data of packet 7 and maintenance packet data 9 are constructed similarly (their length and capacity of the paid part are variable), but with the exception that these types of packets do not transmit circuit connection data, but (as will be described later) transmit packet connection data , which originate in one place (source) and are intended for transmission to another place (destination) or to more places (voice transmission).

The status and control portions of packets 7 and 9 may contain information that determines whether the destination node is able to receive the packet or is currently busy and cannot receive the packet.

Fig. 2A shows the main functional components of one preferred embodiment of a programmable node that can be used with the systems of Figs. 1A to 1D. The digital network / line interfaces are terminated on a series of I / line I / O connection cards (10) 20. In the preferred I embodiment, the network / line interfaces representing a total of I

2048 ports, can be terminated by connection cards 10 20. If it is | desirable, backup connection cards ΙΟ I and backup buses 10 24 can be optionally included, which would ensure the operation I of the connection node in case of failure of one connection card 10 of cards I

2Ů · I series of digital networks Tl. El. The JI, or the analog link I card 26 of the main line, communicates with the link card 10 of the cards 20 via the link card (LC) 10 of the lines. The link cards I are also interfaced to the backup link I buses 30a and 30b. Again, if desired, a backup connection card 32 may be included, which communicates with the backup connection card 10 of the card 22 via the backup LC 10 of the line 34. Other types of network / line interfaces may also be used, e.g. DS3, SONET and other. AND

Various communication services, such as tone detection and I tone generation, conference operation, recorded voice I notifications, signal progress analysis, voice identification, I ADPCM (adaptive differential pulse code modulation) compression, and many I • · · Other services are provided by one or more multifunction digital signal processing cards (MFDSPs). Backup MFDSP cards 36 and ISDN-24 backup cards 38 may also be used. Details of the design and operation of MFDSP cards 36 and ISDN-24 cards 38, buses 30a and 30b. are disclosed in application 08 / 001,113, filed January 5, 1993, in newly issued U.S. Pat. No. 5,349,579 issued to the same application in that application. It is assumed that the system is equipped with one or more cards 36 or 38 and a particular node can operate independently of the other nodes under conditions where it provides various communication services. Alternatively, as will be described below, only one node (or a portion of all nodes) may be equipped with cards 36 or 38, and network 12 may be used to provide communication services to other nodes that are not so equipped.

the circuit (network) card 40 serves as an interface between a pair of circuits (designated set A, circuit 1 and 2), which are collectively referred to as network 12a and node switch 44a designated as local master bus, will be described later. the connection between the host computer 4 and the node according to FIG. 2a.

The second backup circuit board 40b serves as an interface between the backup pair of circuits (designated set B, circuit 3 and 4), which together form the second network 12b, and the backup node 44b, which has the same construction as the node switch 44a. The second main interface 42b provides a connection to the main computer 4. Line 44 is used for the connection between the nodal switches 44a and 44b. Line 46 is used only to connect a node switch that functions as a local master bus to another node switch that also functions as a local master bus.

In the preferred embodiment, the connection cards 26 implement in real time the connection functions required by the network / line interface, including converting the analog function to digital if necessary. Link cards 26 transmit and receive time division multiplex link data (TDM ·· · ·· *

«9 99

- time division multiplex) via link buses 30a and 30b. Each of the node switches 44a and 44b, as well as the MFDSP card 36 and the ISDN-24 card 38, receive node connection data via buses 30a and 3b, transmitted at all time intervals from all line cards 26. Each of the node switches 44a and 44b, MFDSP card 36 and ISDN-24 cards 38 have the ability, under the control of a local master bus (i.e., node switch 44a), to transmit node connection data to link card 26 over buses 30a and 30b. during a predetermined time interval. In addition, each bus 30a and 30b includes a higher data link control (HDLC) bus, through which the CPU in the node switches 44a and 44b. cards 36 MFDSP and cards 38 ISDN-24, exchange control instructions.

For convenience, the term local port, throughout the remainder of the description for a particular node, will refer to the time interval containing connection data transmitted from link card 26 to all node switches 44, MFDSP cards 36, and ISDN-24 cards 38 (if any). ), or will refer to a time interval containing data transmitted from any node switch 44, MFDSP card 36, or ISDN-24 card 38 to link card 26. The term remote port will refer, for a particular node, to the local port of another node.

In a preferred embodiment, each node 6a-6h is able to connect up to 2048 local ports in time. In this embodiment, each node switch 44a and 44b has a time switch capable of switching 2048 time intervals. In accordance with one aspect of the present invention, the memory of each switching node 44a and 44b must be large enough to accommodate only the maximum number of local ports and not the interconnect capacity of the entire system. A significant advantage, according to this aspect, will be appreciated with reference to Figures 1A and 1B. The preferred embodiment of system 2 is capable of connecting a total of 16384 ports. The switch (node switch 44a) within each node 6a-6h only needs to contain enough memory to connect 2048 local ports and not 16384 ports of the whole system 2 · How to

·· · · · · · · • · · · · · • · · · · ·· ··· • · * · · ··· ·· ·· ·· will be described below, it is a novelty of the network arrangement 12 and its ability to transmit circuit connection data from one node to any other node, where this novelty provides a second stage of connection that benefits from the total capacity of system 2.

Figures 2B and 2C show an embodiment of a second type of programmable node. This type of node is based on a serial PC-486 (or equivalent) with peripherals 48, with an ISA (AT) bus 50, with mass storage 52. The PC-486 48 uses application user software and works successfully as host computer 4. Alternatively, may, for connecting the external host and for controlling the node, use the master interface 42a (host 4 of Figs. 1A to 1D). In addition to the components that have already been identified in connection with the previous list, many other components are additionally provided to this embodiment. Voice source processing bus interface 54 provides bidirectional communication between bus 30a and two voice processing buses, PEB 60 and / or MVIP 52. PEB 60 and MVIP 52 are well-known standard interfaces for communication with commercially available, widely used sources. voice processing 56 and 58. For example, Dialogic Corporation of New Jersey manufactures a variety of panels, or cards, for voice processing sources that plug directly into the PEB 60. and can be used in a variety of applications, including voice mail. fax mail, interactive voice responses and elsewhere.

A detailed construction of a preferred embodiment of a node switch is shown in Figures 3A to 3E. A central processing unit (CPU) with allocated RAM / ROM 64 is connected to the address bus of the CPU 114 and to the data bus of the CPU 116. The CPU 64 is also connected to the HDLC bus (parts of buses 3Qa and 30b) and may be, depending on to the node switch arrangement 44a. also connected to the host computer 4.

The data transmitter 66 is connected to the address and data buses

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114 and 116 of the CPU and to the two packet processing circuits 78a and 78b. Transmitter 66 is also connected to receive circuit connection data for local ports via bus 30a (backup bus 30b is omitted for clarity). As will be discussed below, depending on the mode of operation, transmitter 66 may receive and time connection data flowing in the direction from the connection card to the exchange (LSDATA), or alternatively may receive and time data flowing in the direction from the exchange to the connection card. (SLDATA). Transmitter 66 includes two circuit maps 96, 98, corresponding to circuits 1 and 2, respectively, a local sequence counter / map 100, and a four-port memory for local carrier 102.

The data receiver 68 is connected to the data and address buses of the CPUs 114 and 116 and to the spatial connection control circuit 112, the output of which is transmitted via the bus 30a. The receiver 68 may, in conjunction with the spatial control circuit 112 and depending on the mode of operation, discharge circuit link data that flows in a direction to either SLDATA or LSDATA (i.e., any direction opposite to the direction of data input to transmitter 66).

Receiver 68 includes a sequence counter / map 104, a local time interval map 106, a three-port local memory of the receiver, a registration lookup memory 110, a local memory of the dual port packet data receiver, and a sequence map / control 120.

The fast data receiver 70a is physically connected to circuits 1 for receiving packet-shaped information from this circuit. Receiver 70a is realized by chip HDMP-1014 from spol. Hewlett-Packard Company, which is a current coupled circuit (ECL). The conversion circuit 72a is connected so as to be able to receive the output signals of the receiver 70a and generate output signals that are compatible with TTL (transistor-transistor logic) logic.

The output of the conversion circuit 72a is applied to the multiplexers 74a, which convert the 16-bit data received from the receiver 74a to a 32-bit format. The output of the multiplexers 74a is applied to the first in-first out (FXFO) 76a, the packet control circuit 92a, and the circuit selection circuit 94. The transmission flag (XF) circuit is connected to the packet control circuit 92a. The output of the FIFO 76a is connected to the packet processing circuit 78a.

Demultiplexer circuit 80a. the conversion circuit 82a and the fast data transmitter 84a perform functions that are implementations of the multiplexer 74a, the conversion circuit 72a, and the data receiver 70a. The transmitter 84a is realized by the transmission chip HDMP-1012 spol. Hawlett- Packard.

Separately but identically, circuits are created for connecting the interface and for transmitting information to and / or from the components of circuit 2. The corresponding components have the same reference numbers.

As will be further explained in connection with Figs. 6a and 6b, the output of the transmitter 84b is connected to the input of the receiver 70a _f as indicated by the phantom and the reference number 71a during the time periods when the node switch 44a operates in the loopback mode. Similarly, the input of the receiver 70b is connected to the output of the transmitter 84a, as shown by reference numeral 71b.

Node switch 44a includes other components for timing and synchronization functions that are grouped into main node selections 65 and local bus main selections 71. Main node selections include inter-node synchronization circuit 67 and main circuit oscillator 69. Synchronization circuit 67 generates reference signals. refn ,, when each is sent to one different node switch (see Figs. 1a to 1d).

Synchronization circuit 67 also generates a node frame synchronization signal and a main circuit clock, both of which are sent to packet control circuits 92a and 92b. The main options of local bus 71 include HDLC local bus control 73 and local synchronization circuit 75. HDLC local bus control 73 is connected to the CPU address and data buses 114 and 116 and generates a series of signals l ... n, which are sent to all other cards (i.e. to other node switches, link cards, MFDSP cards and ISDN-24 cards) associated with the given node for controlled access to the HDLC bus.

The local synchronization circuit 75 receives two input signals, one input signal being either one of the signals refl..refn, ··· • ·· * · · · · • · · · · • · «· ··· • · · · · ·· (if another node switch is configured as a master node), or it is a loop timing source (if the node switch of Figs. 3A to 3D is itself configured as a master node). The frame synchronization signal (pulse) to circuit 25 is obtained from the inter-node network (circuit) 12 or from one of the signals ref l..refn (if another node switch is configured as the master node. Circuit 75 will generate the frame synchronization signal itself if it is configured itself as the master node.

Further details regarding the construction of the receiver memory 108 and the transmitter memory 102 are shown in FIG. 3F. The memory of the transmitter 102 is organized into a dual database connection circuit 122 and 126, and dual constant regions 132 and 136. The dual database connection circuit of each memory is capable of operating in connecting their respective maps and counters to the timing circuit connection data. That is, during a given time interval, a byte of circuit connection data is sequentially written to a memory location in one of the circuit databases, while connection data stored in another circuit database is read selectively. The term selective is used in this description to process the use of addresses that are provided by a map. During alternating time periods of 125x <, s, the role of the databases of the interconnection circuit is reversed, thus changing the time intervals for performing the time switching.

The constant regions of each memory are generally capable of storing packet connection data by the CPU 64, with the CPU having access to any location in each memory.

Configuration. synchronization, initialization

Before proceeding with an overview of the operation of the node switch 44a, it will be good to understand how each switch should be configured to operate and what its responsibilities are in terms of synchronization and initialization. With reference to Figs. 1A, 1B and 3A to 3E, it should be clear that each programmable connection node 6a to 6h must contain at least one, but may also contain φ φ • φ φ • φ φ ♦ • φ φ φφ φφφ • φφ • φ φ φ φ φ φφφ φ • Φ ·· more than one, node switch 44a. It should also be clear that two types of synchronization must be considered in general: inter-node network synchronization and PSTN (or private network) synchronization.

Each node switch 44a can be configured by software to operate as 1) a combination of master node and local master bus, 2) local master bus only, or 3) neither master node nor local master bus, but only a standard switch . The configuration rules are as follows. For each inter-node network 12, there must be one and only one node switch at a time, which acts as the main switch. Each node switch that acts as a master node can also act as a local master bus for its node. In one particular node, there must be one and only one node switch at a time that works for that node as a local master bus. There may be one or more node switches at a given node at any given time that operate as standard switches.

The duty of the node switch acting as the main node is: 1) to connect the PSTN interface for the loop timing source (via circuit 75). for bit synchronization to digital PSTN networks, 2) generate packets of the remote maintenance system generated by the main node for frame synchronization to digital PSTN networks, 3) communicate with the main computer, 4) communicate with all other cards in the node (other node switches, connection cards, MFDSP cards and ISDN-24 cards) via the HDLC bus (controlled by control signals l ... nz control HDLC 73), 5) generate node clocks and frames for all other cards in the node (local bus clocks and local bus synchronization signals from circuit 75).

The duty of the node switch, which works as a standard switch, is: to receive the synchronization signals of the local bus clock and the local bus frame from the local main bus.

The master node is responsible for initializing and configuring the system, which includes verifying the integrity and operability of φ

φφφφ φ φφφ φ ·· • φφ • φ · φφ ·· network 12 and optionally either assign a node address to each node and send prompts to the nodes to determine their previously assigned addresses. Once a node address is assigned or determined, the master node can investigate the node (using maintenance packets over network 12) to obtain configuration information, such as node type, PSTN interface types and / or protocols, connection capacity, and other information. The master node may also be responsible for performing maintenance and administrative functions. In addition, if multiple circuits are used to implement any inter-node network, the master node may assign a specific packet transmission and reception circuit to each node switch.

Overview of operations

Referring to Figs. 1C, 1D and 3A to 3F, we present an overview of the operation of system 17. We will first pay attention to how the circuit connection data is processed. Assume that the system is already initialized.

The LSDATA (or SLDATA) that is input to the transmitter memory 102. represents the link circuit data bytes for the local ports served by the node. These bytes are written sequentially to the database of the interconnection circuit 122 and 126. Accordingly, the capacities of these databases effectively determine the maximum number of time intervals that can be timed by the node switch 44a. For the purposes of this overview, we assume that each databank has a capacity of 2048 bytes, which means that the maximum of 2048 local ports can be timed by the transmitter memory. In order to make the link circuit data (stored in the memory 102) available to each other node served by the inter-node network 12, one of two methods may be used. According to the first method, the transmitter 66 and the packet processing circuit 78a (assuming that circuit 1 is the circuit allocated to this packet node) formulates a packet whose payload is empty ”(meaning that the payload does not contain any

3sou • 4 4

4 4

4 4

- 23 - ** ··· circuit connection data, except for data from local ports that are connected to other local ports), but has sufficient capacity to store up to 2048 bytes of connection circuit data.

Transmitter 84a then transmits an empty packet. For example, if we assume that an empty packet is being transmitted by node 6d. then node 6d will be the first node to receive this packet (i.e., the first downstream node in the circuit to receive an empty packet).

At node 6d, an empty packet is received by receiver 70a and may eventually be sent to circuit 78a, which processes the packet. Circuit 78a receives the processed circuit data, which is read selectively from the circuit database 122 and 126 in response to the addresses provided by the map (circuit 1) 96. In other words, based on the addresses and controls they provide, the circuit map 96 causes the respective the bytes (or possibly all bytes or no byte) of the local link data stored in banks 122 and 126 will be read selectively and sent to packet processing circuit 78a. A similar process takes place in parallel with the map (circuit 1) 98, the memory 102 and the packet processing circuit 78b.

The packet processing circuit 78a inserts the local link circuit data it receives (if any) into the paid portion of the received empty packet at the time the packet is transmitted to the transmitter 84a for transmission to the next network node 12. This process is repeated so that each the next node in the sequence has the opportunity to insert its local link data into the paid part of the packet that came out of node 6c. If the respective node does not have the local circuit data to insert into the paid part, the received packet passes in the unaltered state to the next node. Finally, a packet that has been sent empty passes through the entire circuit through which it was transmitted and returns full to the node from which it was originally sent, at node (6c) the link circuit data from the paid part of the full packet passes through the circuit selection circuit 94, written sequentially into the memory of the receiver 108 and then time-switched as LSDATA or LSDATA. This method is called the empty sent / full received method, or in short - the method

4 «4 • 4 4 4 · • 4 4 4 · • * 444 444

4

44

0

0

0 • * · ♦ · 0 0 0 0 0 • · 0 »000 ♦ 0 0 0 0 * 0 * 00 • 0 0 0 *

000 00 j · 00

ESFR.

The ESFR method is repeated so that each node alternately sends an empty packet and receives a full returning packet (a circuit assigned to the node), allowing the local circuit connection data generated on any port of any node to be transmitted to any other port of the same or another node. All circuit connection data can be transmitted in a time that is less than 125As, thus preventing sample loss.

As will be explained later, it should be noted that the ESFR method can be used to send or transmit information coming from one port to more than one other port.

In the second method, there is an idea for each node to alternately send a packet whose paid portion is full when it is sent, but is empty when it returns. This method is abbreviated as full sent / empty returns, or FSER method. In the FSER method, all local circuit data stored in the link circuit database 122 and 126 of the transmitter memory 102 is read sequentially and provided to the packet processing circuit 78a. A full packet is generated, the paid part of which includes all connection data of the local circuit of the given node. The full packet is sent by transmitter 84a and is received by the first neighboring node. The data in the payload is selectively extracted and sent via the circuit selection circuit 94 to the receiver ££. This data is then selectively written to the memory database 130 and 134 of the receiver 108. This process is repeated until the full packet transmitted by each node is received by each other node, thus achieving the same result as the local circuit data on any port and allow any node to transfer to any other port of the same or another node. In addition to transmitting circuit link data between nodes, network 12 may also be used to transmit packet link data. Examples of packet connection data are data or maintenance information that is needed to control the connection system itself, such as X.25 packets, LAPBs, or LAPD packets. The packet connection data is • 9 4 • · 9 9

9 «

999 • «9

9 9

9 9

999 99

9 ·

9 9

999 999

9

9-99 appear at the output of the circuit selection circuit 94, but are written to the memory of the packet receiver 118 as opposed to the memory 108. Once the data is stored in the memory 118, they are accessed by the CPU 64 via the CPU 116 data bus.

ESFR method

Referring to Figures 3A to 3E, 4A to 4B, further details of the ESFR method follow. it should be appreciated that the flowchart in Fig. 4B represents the steps that are performed in parallel at each node using packet control circuits (92a, 92b), packet processing circuits 78a. 78b and corresponding circuitry. Everyone should realize that when using the ESFR method, empty packets are transmitted by only one circuit and also received by one circuit (assigned at initialization).

In this example, the node 6i in Fig. 4A is preparing to send an empty packet over the network in order to collect circuit connection data from other nodes, including the node 6j.

The process begins at the beginning of the setup step, which is the state in which the node waits for a transport frame (which contains a packet) to arrive at the network 12. In step 140, it is determined whether the start of the transmission frame has been detected. If not detected, the process returns to start 138. Alternatively, if a start is detected, meaning that the packet has been received by node 6i, then the contents of the packet control portion are checked to determine if the packet is in step 142 occupied. The status of the packet busy or free is indicated by the busy indicator (BI) in the control part of the packet (Fig. 1E). If the packet is not busy, which means that it is free to use node 6i. the process proceeds to step 144, in which a determination is made as to whether the circuit link data (CSD) window for node 6i is open. The CSD window refers to a tent time slot that is allocated to all nodes to transmit an empty circuit connection data packet.

If the CSD window is not open, which means that it is not yet time to transmit an empty packet by the 6i connection node • 9 9 9 9 · 9 9 9 9 * 9 9 «Β 9 Β Β Β · Β · 9 Β · β Β Β 9 9 «• 9 ΒΒΒ β9 *» 9 99 99 circuit data, the process returns to the beginning 138. If the CSD window is open, the process proceeds to step 146, where the node 6i starts sending a packet by sending a control word occupied by the network 12, thereby taking control of the packet. In step 150, the node 6i continues to send an empty packet over the network 12. Note that in step 148, the node must insert local connection data (if any) into the paid part of the empty packet while the transmission continues. The term local connection data refers to circuit connection data that is both generated on and intended for one or more local ports of a given node that sends an empty packet. In other words, local connection data is circuit connection data that must be connected by network 12 from one local port to another local port of the same node. In this case, if the node 6i has any local ports connected to each other, then the circuit connection data belonging to these ports will be inserted in step 148 into the paid part of the empty packet. In practice, this means that node 6i (or any other node, transmits local link data to itself. Subsequently, in step 152, transmission flag (XF) 90a (Fig. 3A) is determined as a reminder from node 6i that it has sent an empty packet to network 12. , and that it will later receive back the full packet.

The process further returns to start 138, where it expects to receive another frame. Once the reception of the next frame is detected and it is determined that the packet in this frame is busy (not free), the process proceeds to step 154, where it is determined whether the transmission flag is set. If XF is not set, which means that the packet that has just been received originates from another node, the process proceeds to step 162. where the address information contained in the packet control portion is checked to determine the (node) source of the packet. In this example, when the node 6j has actually received an empty packet transmitted by the node 6i, the process will proceed to step 162. Since the transmission flag of the node 6i has not been set.

At this point, the node 6i must insert the appropriate circuit connection data into the paid part of the packet. In this example, the relevant circuit connection data is data that belongs to any of the • 4

4

4 ·· · 4 • 44 »4 4

4 4

44

4 of the local ports of node 6j, which are already (or will be) connected to any port of node 6i. As shown in Fig. 4A, this is achieved by the CPU 64a at the node 6j of written addresses and control data to one of the address maps 96, 98. such that the respective circuit connection data is written selectively to the paid part of the received packet in step

164. This step represents the beginning of the second stage of the connection (node-node) performed by the system 17. The error status information is then placed in the status and control part of the packet in step

165

Subsequently, and under normal circumstances, the full returning packet is now received by node 6i. If so, the process proceeds through steps 138, 140, and 142 to step 154, where a determination is again made (at this point by node 6i) as to the status of the transmission flag. Since node 6i has previously set its transmission flag (in step 152 when an empty packet was transmitted), this node determines if the flag has actually been set.

In step 156, the busy indicator in the control part of the packet is changed so that if the packet passes to another node, it is free and can be used by another node. The circuit connection data contained in the payload portion, which consists of any connection data that was inserted in step 148 together with all circuit connection data entered by each other node (including node 6j), is written sequentially to the receiver memory 108. Finally, the flag the transmission is cleared in step 160, and error condition information is checked in step 161 before the process returns to start 138. When the circuit link data is finally turned off from memory 108 in time, which is done by the auxiliary search circuit 110; which works, in the usual way, on the legal conversion of A to & (or similar).

Figures 4C and 4D show an embodiment of the ESFR method in which both circuit connection data and packet connection data are transmitted between nodes, the initial steps being the same as those shown in Figure 4B. But note that in step 144, if a particular node detects that the CSD window is not open, it means that its circuit connection data has already been sent (during frame 125 ^ 5), the process proceeds to step 155 instead of returning immediately to the beginning 138. in step 155 it is determined whether an empty data packet to be used for collecting packet connection information from other nodes , is ready for transmission, and whether the receiver 's memory is also ready. If the data packet is not ready, or if the receiver's memory is full (not ready), the process returns to beginning 138. Otherwise, the process proceeds to step 157, where the information in the packet control section changes to determine if the packet is empty. . The empty packet is then sent in step 159. The transmit flag is set in step 161 and the process returns to start 138.

Upon receipt of the next frame, the process proceeds to steps 138, 140, and 142. Assuming that the received packet is (in-frame) determined to be busy, the process proceeds to step 154, in which the status of the transmission flag is checked. If the transmission flag is set, which means that the node receiving the packet that was previously transmitted is either empty to collect the packet connection data (in step 159, 161). or as an empty packet for collecting circuit connection data (in steps 148-152), then the process proceeds to step 166. where it is determined what type of packet has just been received, again using the information in the control part of the packet. The packet type may determine whether the paid portion of the packet contains circuit connection data, packet connection data, or other types of data (voice signal processing data or maintenance data). If the packet is of a type that carries circuit connection data, the process proceeds to steps 158 and 160, as described in connection with FIG. 4B. If the packet is of a type that carries packet concatenation data, the process proceeds to step 168, where it is determined whether the packet is full. If it is not full, it means that no node has any packet connection data to send (at least during the time it takes for the packet to pass through the network) to the node that originally transmitted (and just received) the packet. In this case, the transmission flag is cleared in step 171, and the process returns to start 138.

0 ·· · 0 * 0 · 0 0

00 · 0 · »000 000« · 0 000 0 0

000 000 00 00 00

On the other hand, if the packet is found to be full in step 168, the process proceeds to step 170, where the buffer is increased. Subsequently, the packet is copied into the memory of the packet data receiver 118 (Fig. 3C), where it is temporarily stored and waiting for further processing. The transmission flag is then cleared in step 174. Finally, the CPU 64b is notified of the arrival of the packet concatenation data by interrupting in step 176.

Referring to step 154. if detected. If the transmission flag is not set, meaning that the packet that was just received came from another node, the process proceeds to step 182, where the packet type is determined as in step 166. If the packet is of a type that carries circuit connection data, the process proceeds to steps 162, 164 and 165 as in FIG. 4B. If the packet is of a type that carries packet concatenation data, the process proceeds to step 188, where it is determined whether the packet is empty. If it is not empty, which means that another node has already filled the paid part, the packet proceeds to the next node and the process returns to start 138.

Alternatively, if the packet is empty, meaning that it was originally transmitted as empty by another node to collect packet connection data, and no other node has already filled the payload, the process then proceeds to step 190. where the node which packet received determines whether the packet has connection data to be sent to the node that originally sent the packet. If not, an empty packet is sent to the next node and the process returns to start 138. If so, the packet is marked as full in step 192, the packet connection data is placed in the payload section in step 194, and the full packet is in step 194 transmitted to the next node.

Fig. 4E is a timing diagram illustrating a preferred embodiment for allocating network bandwidth 12 that would allow both circuit link data and packet link data to be transmitted to all nodes. In this embodiment, network data transmissions are performed in frame windows, each lasting 125 s. The 125s time is preferred because it corresponds to ··· 9 · · * 9 9 • · · »9 · * 9 ··· ·· · 9 9» • 9 ··· 99 «·· 99 sampling rate (8 kHz ) of all the most common network protocols, which means that the values of the circuit connection data can change every 125, <- s. In order to require that all inter-node transmissions of circuit connection data take place in an interval shorter than 125 / A.s, the network 12 ensures that all such data is transmitted before any value changes.

This also allows network 12 to operate asynchronously with respect to the PSTN (or private network) IQ.

In each frame window, approximately one-half of the available time (62.5 .mu.s) is allocated to all nodes in a cyclic manner, in order to transmit circuit connection data to the other nodes. Such transmissions may be performed using either the ESFR or FSER method, or both, and may include any type of packet data packet (or even circuit connection data packets used for other purposes), including packets 5, 7 of FIG. lE. The remaining time between each window is allocated to the nodes to transmit the packet connection data (if any) to other nodes. Circuit connection data is preferred because all such data from all nodes is transmitted before any packet connection data can be transmitted.

The ESFR method can also be used to transmit circuit connection data to multiple ports of the same node or across multiple nodes. For example, if there is local circuit connection data to be transmitted to multiple local ports, multiple copies are pasted into the paid portion of the empty packet in step 148 (Figs. 4B and 4C). In other words, multiple copies of the bytes of data to be transmitted are placed selectively in the payload at locations corresponding to the local ports to receive them. Likewise, if the connection data of the remote port circuit is intended for transmission, multiple copies of this data are inserted in step 164 at the locations in the payloads (one packet / payload is required for each node that has a port assumed that it will receive broadcast • 99 ♦ · · · · · 9 • »· 9 9 9 · · 9 ·· 9 ·· • 99 9 · ·« 9 • 9 ··· ··· ·· · · 99 corresponding to these ports.

In summary, according to FIG. 4A, when the ESFR method is used for data transmission, each node transmits, by the cyclic service method, an empty packet to collect data from all other nodes served by the network 12. After receiving an empty packet transmitted by another node, each node operates by selectively reading data from one of its memories and storing it in the paid part of the empty packet. When a full packet is now returned to the node sending it, the data in the payload is written sequentially to one of the node's receiver memories. This step indicates the completion of the second stage of the connection (one-way node-node) performed by the system.

FSER method and combination of ESFR / FSER methods

Referring to Figures 5A-5C, further details of the FSER method will be described in the context of a preferred embodiment, a combined method in which it is used to transmit connection data of an FSER packet, and an EFSR method for transmission of circuit connection data. For the sake of clarity, the parts of Figs. SB and 5C, which represent the FSER method, are shown by a broken line.

The parts in Figs. SB and 5C which represent the EFSR method lie outside the dashed line and are identical to the steps in Figs. 4C and 4D, which are denoted by the same reference numerals.

In step 144, after determining that the CSD window is not open, which means that the appropriate time to collect circuit link data from other nodes has not yet occurred, the process proceeds to step 196, where it is determined if the full data packet (containing the packet link data) is ready to send to other nodes. If not, the process returns to the beginning 138, where it waits for the next frame to arrive. If the data packet is ready, which means that the paid part of the packet is filled with packet connection data and the corresponding (node) destination address is located in the control part of the packet, the packet is marked as full in step 198.

The full data packet is sent in step 2QQ. Subsequently, in step 222, a transmission flag is set and the process returns to start 138.

··· · · · · · · · «· · ···· ··· ··· • · ·« «· · ·« · «·· ···« · · ·· where the next one is waiting framework.

Now consider what happens when a full packet sent by one node is received by another node. The process proceeds to steps 138, 140, and 142 to node 154, where it is determined whether the transmit flag of the receiving node is set. If the flag is not set, indicating that the packet originated at another node, the process proceeds to step 182, where it is determined, in this example, that the packet contains packet connection data as opposed to circuit connection data. Subsequently, in step 214, the destination node address is checked to determine if the receiving node is the intended recipient of the packet. If not, the process returns to start 138. If so, the receiving node checks to see if its receiver memory 118 (Fig. 3A) is ready to receive the packet in step 216. If the memory is not ready. (because the memory is full), the process proceeds to step 220. where packet information is inserted into the status and control sections to indicate that the node is busy and unable to receive the packet. The process then returns to start 138.

Alternatively, if in step 216 the memory 118 is ready to receive the packet, the process proceeds to step 21, where the packet is copied to the memory. Subsequently, in step 222, the CPU 64b is notified of the arrival of the packet connection data packet by an interrupt.

Finally, we consider a situation where a full data packet is returned to the node that sent it. In this case, the process proceeds from step 138 to step 154, where it is determined whether the transmit flag of the receiving node is actually set. In step 156, the busy indicator is changed to free, ”followed in step 166 by determining what type of data the packet contains. In this example, the packet contains packet concatenation data, so the process proceeds to step 204, where the transmission flag is cleared. Subsequently, in step 206, it is determined, based on the information contained in the status and control portion of the packet, whether the node to which the packet was addressed is occupied. If so, which means that the packet was not received by the destination node • 44 444 444 * • * · 4 44 * 4 444 * 44 •• 4 4 * 4 4 * «4 444 44 * 44 * 4 44, the process returns to start 138. where it will try again »to deliver the packet to the destination. If not, the memory of the packet transmitter in step 208 (area of constants 124 and 128 in Fig. 3F) is marked as empty. Next, in step 210, it is determined whether the packet was received by the destination node to which it was addressed. If so, the process returns to start 138. If not received, errors are written in step 212 before returning to start 138.

It should be appreciated that the FSER method can be used for both circuit link data transmission and packet connection data transmission. If circuit connection data is to be transmitted, each node alternately transmits a full packet, the paid part of which is filled with circuit connection data (for all local ports), which is read sequentially from the transmitter 102. When the node alternately receives the full packet sent by each node, the node receives the appropriate data from the payload portion of each such packet and selectively writes the data to the memory of the receiver 108 in response to the addresses provided by the sequence counter / map 104.

Note that the addresses provided by the counter / map 104 are global addresses (a combination of default port addresses and node source addresses), which means that each can represent. any port of any node in the whole system. Because the circuit link data corresponding to these global addresses is written to locations in memory 108 (which correspond to local ports), address translation must be performed so that such data can finally be read from memory in the correct order. The address map translation circuit 105 obtains as inputs the addresses that are produced by the sequence counter / map 104 of the memory 108 in which the data is stored. The addresses produced by the local address map 107 * are used to select constant regions in memory 108 and padding values from search memory 110.

"Like the ESFR method, the FSER method can be used to send circuit link data to multiple ports. For a given node, this is accomplished by making numerous copies of the data to be transmitted from the payload portion of the full packet

• · · • Φ • • * * »· * e • » ··· • • * • Φ ·· ··· «» « ·· e *

and to selectively write this data to the numerous memory locations of the node receiver. Similarly, different nodes may be instructed to copy the same data from the payload portion of the full packet and to selectively write that data to one or more memory areas of the receiver of those nodes, thereby effecting transmission across multiple nodes.

spQjQting calls between nodes

Having presented various alternatives for transmitting information between the inter-node network 12, we will describe a specific example of a call connection between ports that are physically connected to different nodes. Referring to Figures 1A, 1B, 2A and 3A to 3E, it should be appreciated that each node 6a-6h must include at least one node switch 44a. We will assume that the calling party whose line is interfaced to node 6h hangs up and dials a number that corresponds to the number of the called party whose line is interfaced to node 6g. The host computer receives a service request (which may include dialed digits) from CPU 64 at node 6h. The computer determines that a connection must be established between nodes 6h and 6e, and in response sends a connection message (port address information) to both CPUs of the 64 nodes in order for the connection to occur.

Now consider for a moment what happens at node 6h. The circuit connection data from the calling party line first passes through the bus 30a from one of the connection cards 20 to the node switch 44a. For the purposes of this example, we will further assume that this data is stored in the memory of transmitter 102. Subsequently, if the ESFR method is used, in which an empty packet transmitted by node 6e of network 12 is received by node 6h, the circuit connection data is from the calling side. disconnected from the memory 102 and inserted into the paid part of the packet, which eventually returns to the node 6e.

At this point, there is a one-way connection between the calling party (node 6h) and node 6e, and a time portion formed by the memory of transmitter 102 and a second status portion formed by network 12. It follows that the receiver 68 of node 6e receives its returning

• · « • · * Φ · · a • * • · • · · · · * · M < • · • • · · • ft ·· Jr. Ml «· ·· ··

a full packet that contains connection data from the calling party. The data is timed via the memory of the receiver 108 and sent via the bus 30a to the connection card 20, to which the called party is connected by an interface. At this point, there is a complete one-way connection between the calling party (node 6h) and the called party (node 6e). The same process is repeated in the opposite direction to form the second half of the considered bidirectional connection.

Alternatively, the FSER method can be used to connect the same call. In this case, the transmitter 102 in node 6h temporarily switches the connection data of the calling party circuit to a full packet which is transmitted by the network 12. Node 6e, after receiving the full packet, pulls the connection data of the caller circuit, stores it in the receiver memory 10Q and switches it to the connection card , to which the called party is connected by an interface. Again, the process is performed in the opposite direction to establish the second half of the bi-directional connection.

Figures 6A and 6B show an extensible telecommunications system 17 (Figures 1C and 1D) modified to illustrate the effect of a failure of a programmable link node or portion of an inter-node network 12. In this example, a node 6 or portion of network 12 has failed. (or a malfunction was detected and the node was disconnected by the host computer 4). Nodes 6e and 6q. which are adjacent to the fault node 6f have started operating in loopback mode, in loopback mode the circuit system in the node normally used to receive information from one circuit is connected to the circuitry normally used to transmit information to the other circuit, as indicated by reference numerals 71a and 71b in Figs. 3A, 6A and 6B. When a node operates in loopback mode, all information received by one circuit is sent to the other circuit. A particular node may be instructed by computer A to operate in loopback mode, or alternatively, the operation may begin automatically in response to the termination of the watchdog timer.

Due to loopback mode and the fact that they are used

• * • 9 9 9 9 9 9 · 9 · • 9 • 9 9 9 • 99 999 9 9 9 9 9 9 9 9 and 9 9 «99 • 99 99 99 99

two circuits instead of one, in order to create an inter-node network 12. the error created by the failure of node 6f is successfully isolated from the rest of the system 17. only the local port of node ££ suffers a loss of service due to the node error.

Fig. 7 shows another alternative embodiment of the invention, in which four programmable connection nodes 6k-6n are connected to each other by means of an inter-node network 12, which consists of one circuit pair, pair A, and one backup circuit pair, pair B. This embodiment is not limited only on four connecting nodes, but allows you to add one or more nodes. In this embodiment, the bandwidth of the pair Λ is large enough so that under normal operating conditions, data (circuit connection data and packet connection data) can be transmitted only by this pair. Pair B has a comparable bandwidth to pair A and remains in standby mode under normal operating conditions. In the event of a fault on one of the circuits A, pair B enters normal operating mode and assumes responsibility for the transmission of all data.

It is also advantageous that only one pair of circuits is active, but also the fact that both pairs actually transmit information between the nodes in parallel. This ensures the need that in the event of a fault on the active circuit, the already established connection (call) is maintained and it is not interrupted.

Figures 5A and 8B show another alternative embodiment of the present invention in which a two-circuit inter-node network 12 is used to connect a plurality of voice processing sources 224a-224e to a plurality of programmable connection nodes 6p and 6g to form a voice processing system. 226. A single circuit network may also be used.

The voice processing sources 224a-224e may be the same or different call processing and telecommunications services, including voice mail, interactive voice response, fax mail, voice messaging, and other services, such as data processing. Since the voice processing sources 224a-224e do not include any network / line interfaces (and therefore do not require any frame

9 · · • 9 9 9 9 9 9 « 9 9 9 9 9 9 * • 9 • · • 9 9 9 9 · * 999 999 99 99

information), resources may operate in an asynchronous manner with respect to the PSTN (or private network) 10. In addition, resources 224a-224e may be configured to act as servers relative to each client's host computer.

Fig. 8C shows a preferred embodiment of the voice signal processing source 224a. Note that the components of the source 224a are substantially the same as the components of the connection node 6 shown in Figs. 2B and 2C, except that the source 224a does not require and also has no connection card or other cards (i.e., MFDSP and ISDN-24). that are needed for network / line interfaces.

All of the voice signal processing sources 224a-224e act as nodes in the network 12 and have the same bandwidth access as the other link nodes. Such an approach is very important because it allows resources 224a-224e to provide, in a dynamic manner, any port served by system 226. For example, suppose a caller on the local port of node 6q wants access to the voicemail system to either leave a message for someone who is not answering or to get it back. If it uses the ESFR or FSER method, it can connect to any voice signal source 224a-224e. Assuming that one of these sources is a voice mail system, the requested service will be provided to the caller. The caller can, of course, be connected to any source of voice signal processing that is served by the inter-node network 12.

Figures 9A and 9B illustrate another embodiment of the present invention in which multiple inter-node networks are interconnected to form a system 228 that has even greater switching capacity, or combined switching / voice capacity. The first two-circuit inter-node network 12c (providing voice signal processing capacity via programmable connection nodes 224f-224i and connection capacity via nodes 6r and 6s) is connected to the second two-circuit network 12d (which provides voice signal processing capacity via nodes

• * • • · • · · • « • v • · · • ♦ ·· «· * Φ Φ · • ··· ··

224f-224i and the connection capacity via node 6t) by means of a programmable bridge of node 230. For the sake of clarity, another pair of backup circuits of each network 12c and 12d is omitted in this figure.

The bridge 230 appears as a node in both networks 12c and 12d and is thus connected to each circuit 1, 2, 5 and 6 via an interface. Based on its access to both inter-node networks, the bridge 230 is able to exchange information between the networks 12c and 12d in both directions. For example, bridge 1230 may effectively connect any local port of node 6r or 6s (or any other network node 12c) to any voice signal processing source 224f-224i, or to local port of connection node 6t of network 12d. The inter-node networks 12c and 12d can operate at different speeds without adversely affecting bridge 230. Referring to Fig. 9C, bridge 230 includes substantially the same components as the programmable interconnect node, but in addition includes two additional cards 40c and 40O from circuit 10, and two more node switches 44c and 44d _f which allow the bridge 230 to be connected via an interface to two other inter-node networks 12e and 12f. Although only two additional node switches 44c and 44d are shown, it is possible to add even more such switches, all of which will work together in the manner already described. Jumper 230 also does not require any network / line interfaces (or connected IO cards and link cards), although it may optionally contain such components.

Referring to Figures 3A to 3E and 9C, an example of how information may be transmitted between inter-node networks 12c and 12d will be described below. First, everyone should understand that Figures 3A-3E show the basic hardware of the node switches three 44a-44d of bridge 230. That is, each node switch is substantially a replica of the switch shown in Figures 3A-3E. Node switch 44a is configured as a local master bus (active) and node switch 44b is configured as a local backup master bus. Node switch 44c is configured as a standard node switch (active) and node switch 44d as a backup

• · » • · · ♦ · * · t e • · · <··· t · • • · · ♦ ·· «· ♦« 4

standard node switch.

It may be recalled that each node switch 44a-44d includes a transmitter memory 102 that stores circuit connection data flowing in the direction from the connection card to the switch (LSDATA), or alternatively from the switch to the connection card (SLDATA). Similarly, the receiver memory 108 of each switch acts as an output for LSDATA or SLDATA. Since jumper 230 does not contain any connection card (although such cards may exist), it is desirable for conceptual reasons to consider LSDATA as circuit connection data flowing in the direction from node switch 44c (and 44d) to node switch 44a (and 44b), and consider SLDATA as connection data flowing in the direction from node switch 44a (and 44b) to node switch 44c and 44d). It is believed, for purposes of this discussion, that the node switches 44a and 44b are actually configured to receive and store LSDATA in their transmitter memories 102 and transmit SLDATA from their receiver memories 108. It is further assumed that the node switches 44c and 44d are configured so that they can receive and store SLDATA in their transmitter memories 102 and transmit LSDATA from their receiver memories 108.

The purpose of this arrangement is that any circuit connection data (including data received from the inter-node network 12c). which are time-switched by the node switch 44a (or 44b if it becomes active) pass to the node switch 44c (44d). The node switch 44c operates to transmit the data it receives from the switch 44a to the network 12d. Conversely, this also means that all connection data of the circuit (including data received from the network 12d). which are time-switched by the node switch 44c f44d. if it becomes active), they are sent to the node switch 44a f44b). from which such data, or parts thereof, are transmitted over network 12c. As a result of this arrangement, circuit connection data originating from either node of the inter-node network 12c or 12d can be transmitted to any node of both networks. The packet connection data is transmitted by bridge 230 from the node switch to the node switch via the HDLC bus.

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99

9 ·· the bridge.

In terms of realizing the required backup features, the communication services provided by the MFDSP 36 and ISDN-24 38 cards, as well as the further expansion of the telecommunication system, the switching control system 112 (Fig. 3C), are helpful. The function of the circuit 112 is to allow one and only one of all the node switches 44 of the MFDSP cards 36 and ISDN-24 28 to transmit circuit connection data via the bus 30a on a time-to-time basis.

In terms of the required backup properties, circuit 112 has the following effect. If the node switch 44a is active and functioning properly, the circuit 112 in the backup switch 44b successfully prevents the switch 44b from transmitting any connection data of the circuit via the bus 30a. although switch 44a is allowed to receive all data passing through the bus. If the node switch 44a failed, then the circuit 112 would allow the backup switch 44b to begin transmitting data over the bus 30a. during the time intervals in which switch 44a, if properly functioning, would normally transmit data. The same consideration applies to switch 44c and its backup switch 44d. In terms of communication services, circuit 112 operates to dynamically prevent node switches 44a and 44c from efficiently transmitting circuit connection data over bus 30a during the time intervals in which service is provided by either card 36 or 28. Details of ownership '' or the right to transmit data, during a given time interval, can be dynamically transferred from one device to another (and back again), are disclosed in patent application 08 / 001,113, which has already been mentioned for comparison.

The role of the circuit 112 in connection with further expansion of the telecommunications system is described using Figures 10B and 10C.

Fig. 10A illustrates another embodiment of the present invention in which up to sixteen programmable interconnection nodes 234 are interconnected by four inter-node networks 12q-12j (eight circuits in total) to form an extended telecommunications interconnection system 232. Although only sixteen

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9 9 9 9>

· 9 9 9 9

9 9 999 999 • 9 9 9

99 99 99 be larger, which and also on the speed of the nodes, it is understood that the number of nodes may depend on the connection capacity of each information transmission node between the inter-node networks 12q-12j. It should also be appreciated that any further expansion of the connection capacity of the system 232 may be achieved by the addition of additional inter-node networks.

Under normal operating conditions, inter-node networks 12g and 12i are active and used to transmit all information between all nodes. The remaining inter-node networks 12h and 12j have a comparable bandwidth to the bandwidth of the nodes 12g and 12i. The information transmission takes place in parallel with the networks 12h and 12j, but remains in the standby mode. In the event of a fault in any of the 12q al2i network circuits, the corresponding backup network becomes active.

Figures 10B and 10C show the main components of one of the nodes 234. The components and their operation are comparable to those already mentioned in connection with the other figures. By adding additional circuit boards 40 and node switches 44, an additional inter-node network 124 can be added to the system 234, again expanding the connection capacity of the system 232.

As already mentioned, the spatial control interconnect circuit 112 (Fig. 3C) plays a role in the system 234. The function of the circuit 112 is to ensure, based on a time slot-by-time slot basis, that one and only one of the multiple non-backup node switches 44a present,

44c and 44d (as well as any MFDSP cards 26 and ISDN-24 cards 38 present) efficiently transmits circuit connection data via bus 30a. Thus, the control circuit 112 allows multiple node switches (even those not shown) to be added to the node, which further increases the overall connection capacity of the system.

The foregoing description has been limited to specific embodiments of the invention. However, it will be apparent that various variations and modifications of the present invention may be practiced without departing from the spirit of the invention. The purpose of the appended claims is to cover all such variations and modifications that do not contradict each other

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000 000 of the spirit and scope of the present invention.

Claims (97)

1. An extensible telecommunications system shall comprise: a plurality of programmable telecommunications means (e.g., exchanges) for dynamically connecting and disconnecting communication paths between different individual ports, the system being characterized in that each of the telecommunication means comprises: means for temporally connecting (switching) information to / from said ports, each such means having a switching capacity corresponding to the maximum number of ports that can be physically connected, means for transmitting and receiving information in packet form, means associated with means time switching for interface connection to a plurality of public or private networks representing said ports, said connection including a bus for transmitting data to and from said ports, and means for interconnecting a plurality of said telecommunications means that cooperate with said means for transmitting and receiving on the transmission of packetized information between said telecommunication means, so that the information, including circuit connection data, which originates from any port of any said telecommunication means portable to any other port of the same or another telecommunication means. The system of claim 1, wherein the interconnection means comprises a packet information transmission medium in the form of an optical signal, wherein: 0 »• 0 0 0 0 0 * · · 0 0 0 0 0 000 000 0 0 00 00 0 0 • 00 said medium provides one or more channels, each capable of transmitting all or some of the information. • • 00 being packed 3. The system of claim 2 wherein said interconnection means comprises a medium for transmitting packet information in the form of an optical signal, said second medium being designed to increase the linking capacity of said system and providing fault isolation with respect to said plurality of telecommunications switching devices. The system of claim 2, wherein said interconnect means comprises a medium for transmitting packet information in the form of an optical signal, wherein said plurality of media is designed to increase the switching capacity of the system. The system of claim 1, wherein the one or more telecommunications switching means comprises a programmable switchboard which is controlled by a host computer. System according to claim 5, characterized in that the one or more programmable switchboards can be operated as client switches. System according to claim 6, characterized in that the main computers and the programmable control panels can be connected via a local network. The system of claim 1, further comprising a host computer connected to one of the plurality of telecommunications exchanges, wherein said host computer controls the telecommunications exchanges to which it is connected and can control -fa- • 9 9 9 9 9 • 9 9 9 9 9 • 9,999 9 • 9 • · 9 9 9 · • 99 999 99 99 and other telecommunications exchanges by means of information transmitted by means of interconnection. System according to claim 8, characterized in that the connection between the main computer and one of said telecommunication means (exchanges) is provided by asynchronous connection lines. The system of claim 1, further comprising a master computer for controlling telecommunication means, which is connected to each of said telecommunication means by asynchronous link lines. The system of claim 1, wherein the telecommunications means operate synchronously with respect to public or private networks, and said interconnection means operate asynchronously with respect to public or private networks. 12. The system of claim 1 wherein said interconnect means comprises a local area network. The system of claim 1, wherein the interconnection means comprises a wireless connection network. The system of claim 1, wherein the interconnection means comprise a portion of a public telephone network. 15. The system of claim 1 wherein the interconnection means uses an asynchronous transmission mode to transmit information between said telecommunication means. - ^ 6 «« · · ^ ^. · S · »» «s« «« «« «« * * The system of claim 1, wherein the interconnect means comprise a network. characterized in that the synchronous optical The system of claim 1, wherein the information transmitted by the interconnection means comprises a packet of connection data. 18. The system of claim 1 wherein said information transmitted by the interconnect means is transmitted by one or more packets, each containing control and address information and a payload for data transmission. The system of claim 1, wherein the one or more packets comprises variable length packets for transmitting information by said interconnection means. 20. The system of claim 18, wherein the circuit switched data transmitted by the interconnect means is arranged within a packet in a predetermined order, said sequence being the address information for determining the ports to which said circuit switched data belongs. 21. The system of claim 1, wherein the circuit switched data is subject to up to three switching levels, wherein the first level is implemented by a time switching means that is physically connected to one of said ports from which the circuit switched data is based, implemented by means of transmitting and receiving in conjunction with means of interconnection, and wherein the third level is implemented by means of time switching, which are physically connected to one of the ports for which the data is mentioned. · -tor · · · · · · · · · · · · · · · · · · · · · · · · · System according to claim 1, characterized in that the one or more telecommunication switching means (switchboards) comprises a plurality of time switching means and one or more switching control means. 23. The system of claim 1 wherein said system is not a blocking system. 24. The system of claim 1 comprising one or more voice processing resources connected to the interconnect means, wherein any of said voice processing resources has access to circuit switching data originating from any port of said port. system. 25.The expandable telecommunications system includes: a plurality of programmable telecommunication means (exchanges) for dynamically connecting and disconnecting communication paths between different individual ports, the system being characterized in that each of these telecommunication means comprises: means for time switching information to / from said ports, means for transmitting and receiving packet-shaped information, and means associated with time switching means for connecting to one or more private or public networks belonging to said ports, wherein the interconnection comprises a data transfer bus to / from said ports, means for interconnecting said plurality of telecommunications means which are connected to and operate with broadcasting and 9 9 • 9 «9 9 9 • 9 • * 9 9 • 9 9 9 • 99 999 9 9 9 9 9 9 9 9 99 999 999 99 '9 9 99 receiving means for realizing three-stage switching with respect to information from any of said ports, wherein the first switching level is realized by time switching means, which are physically connected to one of said ports from which the information originates, the second switching level is realized by transmitting and the third level is realized by means of time switching means that are physically connected to one of the ports for which said information is intended. The system of claim 25, wherein each of said time switching means has a switching capacity that corresponds to the maximum number of ports to be physically connected. The system of claim 25, wherein the information including circuit switching data originating from any port of any telecommunications switch (data logger) is substantially continuously transferable to any port of the same or different telecommunication switch (data logger). 28. The system of claim 25, wherein the interconnection means comprises a medium for transmitting said packet information in the form of an optical signal, wherein said medium provides one or more channels, each channel may carry all or some of the packet information. 29. The system of claim 28, wherein the interconnection means comprises first and second mediums for transmitting packet information in the form of optical signals, wherein said second medium increases the switching capacity of the system and isolates disturbances with respect to telecommunications switching means. • Φ φ · φ Φ φ ΦΦ -49φ «· φφφ φ * · * · φ 30. The system of claim 28 wherein the interconnection means comprises a plurality of media for transmitting said packet information in the form of optical signals, as well as increasing the switching capacity of said system. The system of claim 25, wherein the one or more telecommunications switching means comprises a programmable control panel controlled by a host computer. The system of claim 31, wherein the one or more programmable control panels operate as a server controlled by one (or more) main computer. 33. The system of claim 32, wherein said main computer and said programmable control panels are connected to a local area network. 34. The system of claim 25, further comprising a master computer coupled to one of a plurality of telecommunications switching means (switchboards), wherein said master computer controls the telecommunications switching means to which it is connected and controls the other telecommunication switching means by information. transmitted by means of interconnection. 35. The system of claim 34, wherein the connection between the host computer and said telecommunications means is via an asynchronous communication link. 36. The system of claim 25, further comprising a host computer that controls each of said telecommunications switching means and is connected by an asynchronous communication link to each of said telecommunication switching means. -509 * 9 9 9 • 9 9 «'99» 9 * 99 99 9 9 9 • 9 999 telecommunication switching devices (exchanges) 37. The system of claim 25, wherein a plurality of telecommunication switching means operates synchronously with respect to public or private networks, and said interconnection means operates asynchronously with respect to public or private networks. 38. The system of claim 25, wherein said means of interconnection comprises a local area network. 39. The system of claim 25 wherein said interconnect means comprises a wireless communication network. 40. The system of claim 25, wherein said means of interconnection comprises a portion of a public telephone network. 41. The system of claim 25, wherein the interconnect means operates in accordance with an asynchronous transfer mode to transmit information between a plurality of telecom switching means. The system of claim 25, wherein the interconnection means comprises a synchronous optical network. The system of claim 25, wherein the information transmitted by the interconnection means comprises packet connection data. The system of claim 25, wherein said information transmitted by the interconnection means is transmitted by one (or more) packet, each of which 4 4 4 · 4 4 0 4> 4 45 » 4 » 44 44 -51 W »h 4 4 4 4 9 · 9 4 4 4 4 4 4 4 4 44 444 44 * 44 includes control and address information and a payload for data transmission. 45. The system of claim 44, wherein variable length packets are used to transmit information through the interconnect means. 46. The system of claim 44, wherein said packet information comprises circuit switching data arranged within a packet in a predetermined order, said order being address information for determining the ports to which said circuit switched data belongs. System according to claim 25, characterized in that. That one or more of said telecommunications switching means comprises a plurality of said time switching means and one or more switching control means, wherein said switching control means is designed to dynamically enable one and only one time switching means to transmit circuit switching data to bus. The system of claim 25, wherein the system is not a blocking system. 49. The system of claim 1 comprising one or more voice processing resources coupled to the interconnect means, wherein any of said voice processing resources wherein each voice processing resource has access to circuit switching data. that comes from any port of the system. 50.The expandable telecommunications system includes: a) a plurality of nodes for making a telecommunications connection, each switching node comprising dynamic means -52 • 4 4 4 4 4 4 4 444 444 4 4 4 4 4 44 444 4 ·· 44 4 «« 4 connection and disconnection of connection paths, in terms of various ports from a plurality of ports, means for timing information to or from. said ports, means for transmitting and receiving packet-shaped information, means associated with time switch means, for interface connection to one or more public or private networks that represent said port, said connection comprising a bus for transmitting data to and from said port ports, b) the telecommunication system further comprises means for interconnecting the nodes which cooperate with the means of transmitting and receiving the transmission of said packet information in such a way that information coming from any port of any node can communicate seamlessly with any node that is connected via with the mentioned means of interconnection, c) a plurality of nodes for implementing telecommunication services, each such node being connected to the interconnection means by an interface and comprising means for transmitting and receiving packet-shaped information, each node of the service can dynamically provide telecommunication services with respect to any port of any node. 51. The system of claim 50, wherein each of said timing means has a capacity corresponding to the maximum number of ports that can be physically connected. 52. The system of claim 50 wherein said interconnection means comprises a medium for transmitting packet information in the form of optical signals, wherein said medium provides one or more channels, each of which may transmit all or some of said packet information. -53 4 4 · 4 * * 4 4 ft ft 4 4 · 444 4 • 4 4 4 4 4 · 4 44 44 · * 4 4 · 4 4 44 53. The system of claim 52, wherein the interconnection means comprises first and second media for transmitting packet information in the form of optical signals, the second media serving to increase the linking capacity of the system and providing error isolation in terms of a number of telecommunications means. 54. The system of claim 52, wherein the interconnection means comprises a plurality of media for transmitting packet information in the form of an optical signal to increase the coupling capacity of said system. System according to claim 50, characterized in that the one or more connecting nodes comprise a programmable switch (control panel) which is controlled by a main computer. The system of claim 55, wherein the one or more programmable switches operate as servers and are controlled by one or more computers that act as clients. 57. The system of claim 56 wherein said hosts and programmable control panels are interconnected via a local area network. 58. The system of claim 60, further comprising a master computer that is coupled to one junction node, wherein said computer controls the junction node to which it is connected, and controls the other nodes using information transmitted by said interconnect means. 59. The system of claim 58, wherein the connection between said main computer and one of said computers -5tf9 The connection nodes are realized using an asynchronous communication link. 60. The system of claim 50, further comprising a host computer that controls each junction node and is connected by an asynchronous communication link to each junction node. 61. The system of claim 50 wherein the plurality of connection nodes operate synchronously in a public or private network, said interconnection means operating asynchronously in the public and private networks. 62. The system of claim 50, wherein the interconnection means comprises a local area network. 63. The system of claim 50 wherein said interconnection means comprises a wireless communication network. 64. The system of claim 50 wherein said interconnection means comprises a portion of a public telephone network. 65. The system of claim 50 wherein said interconnect means operates to transmit information between a plurality of nodes in accordance with an asynchronous transmission mode. 66. The system of claim 50 wherein said interconnection means comprises a synchronous optical network. 67. The system of claim 50, wherein the information transmitted by the interconnect means comprises 0000 0 0 · 0 0 0 0 0 0 00 0 «0 0 0 0 * 000 0 ·. Β 00 00 -ss0 0 0 * 0 • 0 ·· 000 packet connection data. The system of claim 50, wherein the packetized information transmitted by the interconnection means is transmitted by one or more packets, each containing control information and address information, and a payload for the transmitted data. 69. The system of claim 68, wherein the one or more packets comprise variable length packets for transmitting information by said interconnection means. 70. The system of claim 68, wherein the packet information comprises circuit switched data arranged in a predetermined order within one or more packets, said sequence representing address information for determining the ports to which the circuit switched data belongs. 71. The system of claim 50, wherein the one or more connection U211 includes multiple time switch means and one or more switching control means, wherein the means dynamically allow one and only one of said time switch means to transmit circuit connection data to the circuit. said bus. 72. The system of claim 50, wherein said system is not a blocking system. 73. The system of claim 60 wherein one or more service nodes provide voicemail. 74. The system of claim 50, wherein the one or more service nodes provide interactive voice responses. • * Τ- w v v · v v v v v v v | ··· · · «9 9 9 9» 9 9 «« The system of claim 50, wherein the one or more service nodes provide a fax service. The system of claim 50, wherein the one or more service nodes provide voice messaging services. The system of claim 50, wherein the one or more service nodes provide a wireless connection. The system of claim 50, wherein the one or more service nodes provide personalized PCS services. The system of claim 50, wherein the one or more service nodes are part of a personal communications network (PCN). 80. A telecommunications exchange operating as a node in an extensible telecommunications system includes: means for dynamically connecting and disconnecting connection paths with respect to different ports from a plurality of ports, means for switching time to / from said ports that can be physically connected to a telecommunications exchange, means associated with time switching means intended to be connected via an interface with one or more public or private networks that represent said port, said connection comprising a bus for transmitting data to / from said ports, means for transmitting and receiving packetized information between the inter-node network, wherein said inter-node network makes a connection; 9 9 9 • 9 9 999 99 -57999 »h 9. »• 9 · 9,999 99 between said telecommunications switchboard and other nodes connected to said system, the information including packet connection data coming from any telecommunications switch port is continuously transmitted to each other switch panel port or any other system node. 81. The control panel of claim 80, which is programmable and controlled by a host computer. 82. The control panel of claim 81, wherein the programmable control panel operates as a server that is controlled by one or more main computers that act as clients. 83. The control panel of claim 82, wherein the one or more computers and said control panel are connected via a local area network. 84. The control panel of claim 81, wherein said computer and said control panel are interconnected by an asynchronous communication link. 85. The control panel of claim 80, wherein said inter-node network operates synchronously and asynchronously to the control panel in the public and private networks. 86. The control panel of claim 80, wherein the inter-nodal network comprises a local area network. 87. The control panel of claim 80, wherein the inter-node network comprises a wireless telecommunications network. 88. The switchboard of claim 80, wherein the inter-node network comprises a portion of a public telephone network. -5a ··· and · * *. a a · a · a a a a a 89. The control panel of claim 80, wherein the inter-node network operates in accordance with an asynchronous transmission mode. 90. The control panel of claim 80, wherein the inter-node network comprises a synchronous optical network. 91. The control panel of claim 80, wherein the information transmitted by the inter-nodal network comprises packet connection data. 92. The exchange of claim 80, wherein said packetized information transmitted by the inter-nodal network is transmitted by one or more packets, each including control and address information, and a payload for data transmission. 93. The system of claim 92, wherein said one or more packets are of variable length and serve to transmit information by means of mutual communication. 94. The control panel of claim 92, wherein the circuit switched data transmitted by said interconnect means are arranged within the packets in a predetermined order, said sequence being the address information to determine the ports to which said circuit switched data belongs. 95. The control panel of claim 80, wherein the telecommunications switchboard comprises multiple time switching means and one or more switching control means, wherein the switching control means serves to dynamically transmit circuit data to the bus by one and only one time switching means. in ··· «· *» · · ·; »·» • »» »» »» »» » 96. The control panel of claim 80, wherein said control panel is not a blocking control panel. 97. The control panel of claim 80, further comprising one or more voice resources connected to the inter-nodal network, each of said voice resources having access to circuit switched data originating from any port of the system.