JPH0642753B2 - Time division multiple time switch circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time switch for time division exchange, and more particularly to a structure of a time switch for handling various types of traffic at various speeds.

(Prior Art) Currently, ISDN (Integrated S)
ervice Digital Network) is being energetically promoted both inside and outside the country. ISDN is a network that comprehensively handles not only voice communication but also various communication services such as data images and images.

In this case, if these various communication services can be provided by a single network with little overhead, simplification of the communication network,
It is considered that there are considerable advantages such as centralized maintenance and operation. It is also well known that ISDN is required to provide not only services of 64 Kb / s or 1 / n, n times that of voice communication, but also communication services in an extremely wide speed range including images. Therefore, it is desired to realize a switch with a single architecture that can handle these as easily and uniformly as possible.

Based on the above idea, a new switching method for switching various communication services in an extremely wide range of speeds with a single architecture integrated switching system including circuit switching / packet switching:
A "line / packet integrated switching system" (Japanese Patent Application No. 58-044740 and Japanese Patent Application No. 58-095169, hereinafter referred to as Documents 1 and 2) has been proposed.

In the system of the invention described in the above-mentioned Documents 1 and 2, as shown in FIG. 2, an exchange is made into a building block, and an exchange switch module is formed. For example, a method was adopted in which a circuit-switched call was assembled into one mixed packet and sent / received at every 125 µsec voice sampling period.

The "line / packet integrated switching system" according to the documents 1 and 2 will be briefly described below with reference to FIG. However, in FIG. 2 and the following description, the additional portion generated by the mixture of packet calls relating to the above method is not directly related to the description of the present invention, and therefore will be omitted.

In FIG. 2, the INF unit in each exchange switch module has an interface function for accommodating a subscriber line and an inter-station relay trunk group accommodated in the exchange, and a function for digitally multiplexing or demultiplexing these. Is. Further, the time division multiplex time switch memory circuit T temporarily buffers the call information in the digital multiplexed channel from the INF section in the forward direction from the INF section to the loop to convert the time phase between channels (time switch). Function), and a function of editing a plurality of circuit-switched calls that span between specific modules into a mixed packet format, which will be described later with reference to FIG. 3, a transmission waiting function to the loop, and a reverse direction from the loop to the INF section. Has the reverse function described above. Further, CM in the figure is a time switch control memory circuit, which is an address for writing the digitally multiplexed call information coming from the INF section to the time switch memory circuit T for each time slot, or vice versa. It has a function of designating an address for reading out, for each time slot, call information to be digitally multiplexed and transmitted from the circuit T to the INF section.

Further, in FIG. 2, D / I is an interface circuit between the exchange switch module and a plurality of digital multiplex loops, which inserts the call information from the exchange switch module into an idle time position on a plurality of loops (Insert function), or On the contrary, it has a function (Drop function) of branching communication information addressed to its own module from the loop.

FIG. 3 shows a mixed bucket format used when a plurality of circuit-switched calls extending between the specific switching switch modules shown in FIG. 2 are assembled into one mixed packet and transmitted / received via a loop. In the figure, DA is an incoming exchange switch
The module number, SA is the number of the originating exchange switch module, and OH _{1 to} OH _n are the n-channel call message portions that are simultaneously talking between the originating and terminating switch modules at that time. The size of the call message part of each channel is secured in proportion to the communication speed of the circuit switched call. For example, in the case of voice, the information amount of one voice channel included in one mixed packet can be one sample (8 bits). In addition, this method enables uniform switching of multiple communication services in an extremely wide speed range.

Now, an economical and concrete method for realizing the above-mentioned "line / packet integrated switching system", in particular, the time division multiplex time switch memory circuit T shown in FIG. 2 and the time switch control memory circuit which is its control circuit. A time-division multiple time switch circuit (Japanese Patent Application No. 58-155581, reference 3) shown in FIG. 4 has been proposed as an economical and concrete method for realizing a CM.

FIG. 4 is a block diagram showing the outline of the configuration and the operation of the time division multiplex time switch memory circuit T and the time switch control circuit CM for controlling it described in FIG. However, in FIG. 4, for simplicity, the time division multiplex time switch memory circuit T shows an outline of the circuit configuration related to the forward direction of the signal flow from the INF section to the loop side in FIG. Flowing circuits are omitted (the reverse direction circuit has almost the same structure as the forward direction, and the operation is just in a reverse relationship, so it can be easily guessed.) In FIG. 4, the time division multiplex time switch memory circuit T is shown. It is composed of two sides of a memory circuit composed of a so-called random access memory (RAM). The first memory surface writes the call information for one frame of each digital multiplexed channel received from the 1NF section in an even time frame, and reads it in the next odd frame to execute the loop branching / inserting circuit shown in FIG. Send to D / I. On the contrary, the second memory surface writes the call information in the odd time frame and reads the call information in the next even time frame. Writing of each piece of call information of the digital multiplexed channel from the INF section to the memory circuits on these two sides is written to the memory address designated by the time switch control memory circuit CM for each input time slot (random writing). On the time switch memory circuit T, the CM has the call information of the input channels, as shown in FIG. 4, from the beginning address of the memory to the switch module # 1 (node # 1 in the figure). , # 2 call information, ..., #N call information, and, for example, call information for the same # 1 exchange switch module, if there are n calls at that time, , #N (FIG. 2, CH ₁ , ..., CH _n ) are arranged in order, and the write address is instructed for each input time slot.

As described above, as a result of writing the call information of the input channel to the time division multiplex time switch memory circuit T, the content is read from the head address at a speed consistent with the transmission speed of the loop side sequentially (sequential read). , For each series of call information addressed to the same exchange switch module,
By adding the destination module address DA and the source exchange switch module address SA as shown in FIG. 3, a desired mixed packet can be formed.

The reason why the time division multiplex time switch memory circuit T is provided on two sides for even and odd frames is to avoid the phenomenon of "slip" which is well known to those skilled in the art. (Refer to the above-mentioned document 3 for details.) By the way, on the time division multiplex time switch / memory circuit T, in order to arrange and write the call information in an orderly manner, from the first address to the exchange switch module, # 1 channel, # 2 channel, ... Each time a call is restored or a new call occurs, the time switch control memory circuit CM
The content of needs to be updated. Now, for example, when the call of the #j channel addressed to the #i switch module is restored, this call uses k words on the time switch memory circuit T, that is, this call has a communication speed k times the basic communication speed. If it is a call, the memory use area of the call of each communication channel, which has used the memory area located in the older number on the time switch memory circuit T, may be advanced to the address k. For that purpose, the result of reading out the memory contents of the CM for each input time slot is sent to the time switch memory circuit T, and at the same time, the result is compared with the address indicating the area used by the restored call to restore the call. If it is larger than the address of, the content is calculated by k and rewritten to the original position. On the other hand, when a new call of k times calls occurs, the memory usage of the call of each communication channel that used the memory area located in the old place of the area on the time switch memory T which the new call should use It is necessary to move the area down by k addresses. For that purpose, as in the case of the previous case, for the memory contents of the CM larger than the address indicating the area used by the new call, the contents may be added by k. Although not shown in the figure, the ASU (address shift unit) in FIG. 4 is an operation for comparing the memory contents of the CM and correcting operation as described above according to an instruction from the control processor that controls the exchange call processing. Circuit.

(Problems of Prior Art) In the time division multiplex time switch circuit including the time division multiplex time switch memory T and the time switch control memory CM described above, the exchange switch
It is not possible to simultaneously distribute the call information of one call coming to the INF part in the module to the switching switch modules of a plurality of destinations. That is, there is a drawback in that 1: N (N ≧ 2) multiple connections cannot be performed. This is because the input call information is written to the time division multiplex time switch memory T by the random write method, and the read from the T to the output highway is the sequential read method. Therefore, the same input channel information in the T is output to a plurality of outputs. This is because the data cannot be read over the time slot. This drawback becomes a serious problem when trying to realize a broadcasting function that simultaneously transmits the same input information to a plurality of destinations.

(Object of the Invention) The present invention eliminates such drawbacks of the prior art, and obtains a time division multiplex time switch circuit that can easily realize the broadcasting function etc. by allowing the same input information to be simultaneously transmitted to a plurality of destinations. It is intended.

(Structure of the Invention) According to the present invention, a time division multiplex time switch memory circuit and an address for reading out call information to be sent to the time division multiplex highway for each time slot from the time switch multiplex memory circuit, or from the time division multiplex highway. In a time division multiplex time switch circuit consisting of a time switch control memory circuit that specifies an address to write incoming call information to the time switch memory circuit, write call information in even time frames and read call information in odd time frames. A time division multiplex time switch memory circuit having a first memory surface for performing writing of call information in an odd time frame and a second memory surface for reading out call information in an even time frame; The first time interval for storing the read address or write address of the switch circuit. A switch control memory circuit and a second time switch control memory circuit, and one of the time switch control memory circuits is set to a read state and the other time switch control memory circuit is set to a write state at the beginning of each frame. The read address or the write address of the time division multiplex time switch circuit read from the time switch control memory is supplied to the time division multiplex time switch circuit, and at the same time, the read address of the time switch control memory is larger than a certain specified first value. In this case, the time division multiplex time switch memory read from the time switch control memory in the read state with a value obtained by adding or subtracting the second value that is also designated to the read address as the write address. Write circuit read address or write address as data Division multiplex time switch circuit is obtained when and writes the time switch control memory state.

(Example) Hereinafter, the Example of this invention is described in detail with reference to drawings. FIG. 1 is a block diagram for explaining an embodiment of the present invention, and a time division multiplex time switch memory circuit T when a signal flows from the INF section to the loop side described in FIG.
3 is a block diagram showing an outline of a configuration and an operation of a time switch control memory circuit CM for controlling the time.

In FIG. 1, the time division multiple time switch memory circuit T is composed of two surfaces of a memory circuit which is a so-called random access memory (RAM). The first memory side writes even one frame of each call information of the digital multiplexed channel received from the 1NF section in the even time frame, and reads it in the next odd time frame to branch / insert the loop shown in FIG. Send to circuit D / I. On the other hand, the second memory side writes the call information in odd time frames,
The call information is read in the next even time frame. The writing of the call information of the digital multiplexed channel from the INF section to these two memory circuits is performed sequentially for each input time slot (sequential writing), and the call information is read from the memory circuit to the D / I section. Is read from the memory address designated by the time switch control memory circuit CM for each output time slot (random read). In the CM, the output channel information read from the time switch memory circuit T is the call information to the exchange switch module # 1 (to the node # 1 in the figure) in the order of the output time slots on the output highway toward the D / I section. , Call information for # 2, ……, #N
Call information addressed to the exchange switch module of the same # 1 will be channel information such as channel # 1, # 2, ..., #n in that number if there are n calls at that time. The read address is instructed for each output time slot so as to be arranged in. That is, for example, if the i-th channel addressed to the # 1 exchange switch module is CH _i, and the address of T where the call information of CH _i is written is I (CH _i ), the read address of T held by the CM Is I (CH ₁ ), I (C
H ₂ ), ..., I (CH _i ) are arranged in this order.

Furthermore, in this case, since the input call channel having the communication speed K times the basic communication speed uses K input time slots during one frame time to transmit the call information,
The CM issues a read address instruction so that the call information for K input time slots relating to the same call is also arranged adjacently when read from the time switch memory circuit T. In Fig. 1, the third channel (I (CH ₃ ) in Fig. 1) addressed to the # 1 exchange switch module is the basic speed (eg, 64 Kb /
It shows the situation when the speed is twice as fast as (s) (128 Kb / s).

As described above, after the call information of the input channel is sequentially written to the time division multiplex time switch memory circuit T, the content is matched with the transmission speed on the loop side from the memory address indicated by the time switch control memory circuit CM in the next frame. If the destination module address DA and the source exchange switch module address SA as shown in FIG. 3 are added to each of a series of call information groups addressed to the same exchange switch module at the desired speed (random readout) Mixed packets can be formed.

The reason why two time-division multiplex time switch memory circuits T are provided for even and odd frames is to prevent slip, as in the conventional example. This will be described according to the present invention. In the present invention, as described above, when the call information of each call channel is read out from T and arranged in the form of a mixed packet, for example, when a call call of a specific channel is restored, the output time of the oldest The address of T read at the time of the slot is shifted to the output time slot which is relatively raised by the output time slot used by the restored telephone call. Conversely, if a new call to a particular switch module is made, only the number of output timeslots used by the new call,
The address of T read at the time of the output time slot of the other older one will be shifted to the output time slot which is relatively lowered. That is, the output time slot destined for a particular switching switch module and from which a particular channel therein is read varies from frame to frame. As a result, when only one surface of the time division multiplex time switch memory circuit T is prepared, there is a possibility that the relative time relationship between the writing and reading of the call information of this specific channel is switched. If the time relations of writing and reading are exchanged, the call information is dropped or duplicated at that time,
That is, since a phenomenon called "slip" well known to those skilled in the art occurs, even in the method of the present invention, two time division multiplex time switch memory circuits T for even / odd frames are provided and writing / reading is always shifted by one frame. This prevents the occurrence of "slip".

Next, the time division multiplex time switch memory circuit T described above
The time switch control memory circuit CM for indicating the read address to each output time slot will be described. CM is m if the number of output time slots per frame is m
It is similar to the conventional time switch control circuit for a time division switch in that it is configured by a word random access memory. The difference is that the function of advancing (decreasing) the contents of CM is required along with call restoration (call origination).

The reason why the time switch control memory circuit CM is provided on two sides of CM ₁ and CM ₂ is that the CM content is delayed as a result of the call origination as described above, so that the CM has only one side. Is 1
This is because the contents of the CM that have not been read yet are destroyed within the frame time. In Fig. 1, SW ₁ , ..., SW ₅ are switched each time a call is originated and restored, and the state of each SW in the figure is the contents read from CM ₁ via SW ₁ and time-division multiplexed. The state is shown in which the time is output to the time switch circuit T and simultaneously written in CM ₂ . In FIG. 1, an ASU (address shift unit) is an arithmetic circuit, which is omitted in the figure, but carries up or down the memory contents of the CM as described above in response to an instruction from the control processor that controls the exchange call processing. .

Consider, for example, the case where the call on the #j channel addressed to the #i exchange switch module is restored. In this case, if this call uses K words on the time switch memory circuit T, that is, if this call has a communication speed K times the basic communication speed, CM
Address on ₁ (this corresponds to the output timeslot) ai
It is assumed that the memory areas of j, aij + 1, ..., Aij + (K-1) are used. As a result of the restoration of this K times call, the contents of CM ₁ of the call of each communication channel that used the memory area corresponding to the output time slot of the older number are K respectively.
The address must be moved up. To do this, access address Ar (r = 1,2,2) of CM ₁ for each output time slot.
, M) and aij given by the control processor are successively compared by ASU, and if Ar> aij + (K-1), the contents of the Ar address of CM ₁ are passed through SW ₂ and SW ₃ , The purpose can be achieved by moving (raising) to the (Ar-K) address of CM ₂ .
If aij> Ar, the write address of CM ₂ does not change, and write to the same Ar address as CM ₁ . On the contrary, a new call of the #j channel occurs to the #i exchange switch module, and this new call is a call having a communication speed K times the basic communication speed, and the K word address aij on CM ₁
If you want to use aij + 1, ..., aij + (K-1),
Although not shown in FIG. 1, according to an instruction from the control processor, the read address of the time division multiplex time switch circuit is written in the addresses aij, aij + 1, ..., Aij + (K-1) of CM ₂ . Further, as a result of this K-fold call, the call memory use area of each call channel, which used the CM ₁ memory area located at an older number than this, must be decremented by K address. For that, like Ar, the address Ar of CM ₁
CM _{2 for} the contents of the address where Ar ≧ aij at (r = 1, 2, ..., M)
If you move to the (Ar + K) address, you can reach the goal. For the address of aij> Ar, the write address of CM ₂ does not change and it is written in the same Ar address as CM ₁ .

This embodiment relates to the flow of signals from the INF section to the D / I section in FIG. 2, but the operation is almost the same in the reverse direction from the D / I section to the INF section. The time division multiplex time switch circuit can be constructed so as to have the inverse relationship of degrees.
However, in the case of this reverse direction, the call information is written from the D / I section to the T by the random writing method, and the reading from the T to the INF section is performed by the sequential reading method, so that multiple connection is impossible.

On the other hand, in the conventional time division multiplex time switch circuit,
In the case of the NF section direction, writing from the D / I section to T sequentially, T
Since it is a random read from the to the INF part, multiple connection is possible. Therefore, in the configuration of FIG.
The / I section direction is a time division multiplex time switch circuit of the embodiment of the present invention, and the D / I section to the INF section direction is a combination of the conventional time division multiplex time switch circuit.
Multiple connections can be made in both the / I section direction and the D / I section → INF section direction.

(Effects of the Invention) As described above, according to the present invention, in a line / packet integrated switch composed of a plurality of modules, the same input information can be transmitted to a plurality of destinations at the same time, which facilitates the broadcasting function and the like. realizable.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a time switch according to the present invention and its operation outline, FIG. 2 is a block diagram showing a configuration of an exchange to which the present invention is applied, and FIG. 3 is a building block. FIG. 4 is a diagram showing an example of a mixed packet format used when exchanging call information between exchange switch modules, and FIG. 4 is a block diagram showing a configuration of a conventional time switch and its operation. In the figure, INF is an interface circuit, T is a time division multiplex time switch memory circuit, CM, CM ₁ and CM ₂ are time switch control memory circuits, D / I is an interface circuit, ASU is an address shift unit, SW ₁ , SW ₂ , SW ₃ , SW ₄ , SW
₅ is a changeover switch.

Claims (1)

[Claims] 1. A time division multiplex time switch memory circuit, and an address from which the call information to be sent to the time division multiplex highway for each time slot is read from the time switch memory circuit, or call information coming from the time division multiplex highway. In a time division multiplex time switch circuit comprising a time switch control memory circuit for designating an address to be written to the time switch memory circuit, a first memory surface for writing call information in an even time frame and reading call information in an odd time frame. And a time division multiplex time switch memory circuit having a second memory surface for writing call information in an odd time frame and reading call information in an even time frame, and a read address or a write of the time division multiple time switch circuit. First time switch control memory circuit for storing address A second time switch control memory circuit, one of the time switch control memory circuits is set to a read state at the beginning of each frame, and the other time switch control memory circuit is set to a write state. When the read address or write address of the read time division multiplex time switch circuit is supplied to the time division multiplex time switch circuit, at the same time when the read address of the time switch control memory is larger than a specified first value, the same applies. A read address of the time division multiplex time switch memory circuit read from the time switch control memory in the read state, with a value obtained by adding or subtracting the designated second value to or from the read address, Alternatively, the write address is used as data and the time switch control of the write state Division multiplex time switch circuit when and writes to memory.