JPS6249799A - Time division multiplex time-switch controlling system - Google Patents

Abstract

PURPOSE:To completely prevent a cross from occurring by making a previous arrangement between communication nodes, and changing the content of a time-switch control memory, at the time when the value of the frame time counted or received and held becomes equal to a specific value, when setting or releasing a communication between the communication nodes. CONSTITUTION:A control processor PROC1 to control the transmission node transmits to the reception node an updating information for a time-switch control memory CMS associated with the call, and at the same time sets in a holding circuit REG12 the value m (0<=m<=N-1) determined by the combination of the transmission node and the reception node. Meanwhile, a control processor PROC2 to control the reception node receives said updating information, and finds the value (m) using the number of the transmission node, and sets it in a holding circuit REG22. The both nodes compare the value (m) with the values in holding circuits REG11 and REG21 holding the frame time of mod N received by their comparing circuits CMP1 and CMP2. In a frame when the said comparison shows coincidence, the both nodes update respective time-switch control memories CMS and CMR to set up the desired communication between the two nodes.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a time division multiplex time switch control system for time division switching, and in particular to a time division multiplex time switch control system that multidimensionally handles various kinds of traffic at various speeds. Regarding control method.

[Prior art]

Currently, the Integrated Digital Service Network (ISDN)
rated 5service Digital Ne
Work) is being actively studied both inside and outside the art world.

15DN is a network that comprehensively handles not only voice communication but also a variety of communication services such as data images and images.

If these various communication services can be provided by a single network with little overhead, the communication network can be simplified,
It is believed that there are considerable benefits such as centralization of maintenance and operation. In addition, in l5DN, voice communication is 54kb/s
Or not only the service of about 1/n1n times that,
It is well known that it is essential to provide communication services in an extremely wide speed range, including images, and it is desired to realize a switching system with a single architecture that can process these services as easily and uniformly as possible.

Based on the above idea, we have developed a new switching system that exchanges various communication services with an extremely wide range of speeds using an integrated switching system with a single architecture, including circuit switching and packet switching.
"Line/Packet Integrated Switching System" (Patent Application 1986-044)
No. 740 and Japanese Patent Application No. 58-095169 (hereinafter referred to as Documents 1 and 2) have been proposed.

In the system of the invention described in the above-mentioned documents 1 and 2, as shown in FIG. 4, the exchange is made into a communication node made up of building blocks, and these are connected by a plurality of loops, and a plurality of lines spanning between specific communication nodes are created. For example, a method is adopted in which a switched call is assembled into one mixed packet for each voice sampling period of 125 μsec, and then sent and received.

The "line/packet integrated switching system" according to Documents 1 and 2 will be briefly explained below with reference to FIG. However, in FIG. 4 and the following explanation, additional parts that occur due to the mixture of packet calls related to the above system will be omitted since they are not directly related to the description of the present invention.

In Figure 4, the INF section (interface circuit) in each communication node has an interface function for accommodating information from subscriber lines and interoffice relay trunk groups accommodated in the exchange, and digital multiplexing of this information. Alternatively, it has a function of demultiplexing. In addition, in the forward direction from the INF section to multiple loops, the time division multiplexing time switch/memory circuit T converts the time phase between the channels by -H buffering the call information in the digital multiplexed channel from the INF section. (Time switch function)
7, as well as a function to edit multiple circuit-switched calls spanning between specific communication nodes into a mixed packet format, which will be described later in connection with FIG. Regarding the reverse direction, it has the above-mentioned reverse function.

In addition, CM in the figure is a time switch control memory circuit, and IN
From part F to the above-mentioned time division multiplex time switch/memory circuit T
Specify the address to write incoming digital multiplexed call information for each time slot, or conversely, the address to read out the digital multiplexed call information sent from the time division multiplex time switch/memory circuit T to the INF section for each time slot. .

It has the function of

In addition, in Fig. 4, D/I is a time division multiplex time switch/memory circuit T of a communication node and a plurality of digital multiplex loops (
A function (Insert function) that inserts call information from a communication node into a vacant time position on multiple loops in an interface circuit with multiple loops, or conversely a function (Drop function) that branches communication information addressed to one's own module from multiple loops.
function).

Figure 5 is '! J4 This is a mixed packet format used when multiple circuit-switched calls extending between specific communication nodes shown in the diagram are assembled into one mixed packet and sent/received via a loop. In the figure, DA is the number of the incoming communication node, SA
is the number of the outgoing communication, /-, and DA and SA constitute the header part. Further, CH, -CH, . . . are the message portions of n-channel calls that are simultaneously in progress between the originating communication node and the terminating communication node at the respective times. The size of the call message portion of each channel is ensured in proportion to the communication speed of the circuit switched call. For example, taking audio as an example, the amount of information for one audio channel included in one mixed packet can be one sample (8 bits). Furthermore, this method allows uniform switching of multiple communication services over an extremely wide speed range.

Now, let us discuss an economical and concrete implementation method of the conventional "line/packet integrated switching system" explained above, especially the time division multiplex time switch/memory circuit T shown in FIG. 4 and the time switch control memory which is its control circuit. As an economical and concrete implementation method of the circuit CM, a time division multiplex time switch circuit (Japanese Patent Application No. 155581/1981,
Reference 3) has been proposed.

Figure 6 shows the time division multiplexed time switch/memory circuit T explained in Figure 4 and the time switch control circuit CM that controls it.
FIG. 2 is a block diagram showing an outline of the configuration and operation of the device. However, for the sake of simplicity in FIG. 6, the time division multiplex time switch/memory circuit T is shown in FIG. The circuit through which the signal flows is omitted (the configuration of the circuit in the reverse direction is almost the same as that in the forward direction, and the operation is exactly the opposite, so it can be easily inferred).

In FIG. 6, the time division multiplexed time switch memory circuit T consists of two memory circuits constituted by so-called random access memories (RAMs). On the first memory surface, l frames of each call information of the digital multiplexed channel received from the INF unit are written in even time frames, and read out in the next odd frame to perform loop branching and insertion as shown in Fig. 4. It is sent to the interface circuit D/I having the function. Conversely, the second memory plane writes call information in odd time frames and reads call information in the next even time frame. Each call information of the digital multiplexed channel from the INF section to these two memory circuits is written to the memory address indicated by the time switch control memory circuit CM for each input time slot (random write). The time switch control memory circuit CM stores the call information of the input channel on the time division multiplex time switch memory circuit T in order from the first address of the memory to the communication node #l (7 in the figure), as shown in FIG. −
Call information for node #1), call information for node #2, etc.
..., call information addressed to node #N, and call information addressed to a communication node with the same number (for example, #l), if there are n calls at that time, this is also channel #l,
#2. ..., #n (Figure 5 CHr, ..., CH,
), a write address instruction is issued for each input time slot so that the input time slots are arranged in order.

As explained above, as a result of writing the call information of the input channel to the time division multiplex time switch/memory circuit T, the contents are read out in the next frame from the first address at a speed consistent with the transmission speed of the loop side (sequential readout). , a desired mixed packet can be formed by adding the destination node address DA and source node address SA as shown in FIG. 5 to each set of call information addressed to the same communication node.

The reason why the time-division multiplexing time switch/memory circuit T is provided on two sides for even and odd frames is to avoid the phenomenon of "slip" which is well known to those skilled in the art (for details, refer to the above-mentioned document 3). .

By the way, in order to always write call information in an orderly manner from the first address to channel #1, channel #2, etc. addressed to the communication node on the time division multiplex time switch/memory circuit T, it is necessary to It is necessary to update the contents of the time switch control memory circuit CM each time a call is restored or a new call is generated. Now, for example, with communication node 1
When the call on the destination channel #j is restored, assuming that this call uses words on the time division multiplex time switch memory circuit T, that is, this call is a call with a communication speed twice the basic communication speed. , the addresses of the memory usage areas of calls of each call channel that used memory areas located at higher numbers than this on the time division multiplex time switch memory circuit T may be moved up by address. To do this, the CVI memory contents are read for each input time slot and the results are sent to the time division multiplexed time switch memory circuit T, and at the same time, the results are compared with the address indicating the area used by the restored call. , if it is larger than the address of the restored call, the content can be subtracted by k and rewritten in the original position.

Conversely, if a new double call occurs, the call of each communication channel that was using the memory area located at a higher number than the area that should be used by the new call on the time division multiplex time switch memo 9T is It is necessary to move down the address of each memory usage area. To do this, as before, it is sufficient to add k to one of the CM memory contents that is thicker than the address indicating the area used by the new call.

Although the ASLI (address shift unit) in FIG. 6 is omitted in the figure, it performs the above-mentioned comparison and correction operations on the memory contents of CMs based on instructions from the control processor that controls switched call processing. It is a circuit.

[Problems with conventional technology]

In the conventional method described above, two communication nodes connected to a loop (hereinafter referred to as "node l" and "node") are communicating, and a call in progress from node l to "node" is restored or a new call is generated. In this case, the length of the mixed packet (kerat) assembled in the time division multiplex time switch of the source node L changes according to the operating principle described above, and the mixed packet after the change is transmitted on the loop, and the time in the receiving node J is changed. Written to the division multiplex time switch.The mixed packet after this change is because the call data after the channel where the call was made or recovered is carried forward in the case of a call, and carried forward in the case of recovery, and the position has shifted. , node" reads the call data forming the mixed packet using the read address supplied by the time switch control memory before the change, other call data is read and interference occurs.

In other words, when updating the time switch control memory during call origination and recovery between communicating nodes, it is necessary to match the times in frames between the originating and receiving nodes, but conventionally, the times in frames have not been made to match. Since no means was provided for updating the time switch control memory, there was a drawback that interference could not be completely prevented.

[Purpose of the invention]

An object of the present invention is to provide a time division multiplex time switch control system that prevents the above-mentioned interference by matching the frame times for updating the time switch control memory of each node upon call origination and recovery.

[Structure of the invention]

The present invention provides a time division multiplexing time switch for a communication system including a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network coupling the communication nodes. In a time division multiplex time switch control method for controlling a switch, one of the communication nodes includes means for counting mod N frame times in units of time division multiplex frames, and means for transmitting the frame times to other communication nodes every frame. and each of the other communication nodes is provided with means for receiving the frame time and holding it for one frame time,
When setting up or opening communication between communication nodes, the communication nodes discuss the intention of setting up or opening the communication, and then the communication node calculates the value of the frame time that it has counted or received and held. The value m determined by the combination of 0≦m≦N-1
The present invention is characterized in that the content of the time switch control memory of the communication node is changed so that the communication is set or released when the communication node becomes equal to the communication node.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic diagram showing the configuration of each node in an embodiment of the time division multiplex time switch control system of the present invention. 1st
The figure shows a case where an input speech signal arriving from the INF section is transmitted to INFaB on the outgoing side via a route of sending node-loop-receiving node. The transmission node includes an INF section, a transmission time division multiplex time switch T8, a transmission time switch control memory cMs, and a loop interface circuit D.
/I, frame time detection circuit DET, , holding circuit REG
,,.

REG, 2, comparison circuit CMP, control processor PRO
It is composed of C. Also, the receiving node is INF
part, reception time division multiplexing time switch T2, reception time switch control memo JCMm, loop interface circuit D/I, frame time detection circuit DET2, holding circuit RE G21. RE 022, comparison circuit CMP2,
It consists of a control processor PROCa. The transmitting node and the receiving node are connected by loops #1 to #l in the loop interface circuit D/I.

In FIG. 1, a transmission time division multiplexing time switch T3,
The operation of the transmission time switch control memo IJcM, loop interface circuit D/I is similar to the conventional time division multiplex time switch/memory circuit T shown in FIGS. 4 and 6.
This is the same as the one-hour switch control memory circuit CM and the interface circuit D/I.

Furthermore, the operations of the reception time division multiplexing time switch T l + reception time switch control memory CMi, and loop interface circuit D/I are almost the same as those on the transmission side, except that the data flow is in the opposite direction. .

On the other hand, in FIG. 1, the frame time detection circuit DET,
, DET detects frame time information sent every frame from a specific communication node (referred to as a system management node). This frame time detection circuit D E
T l, D E Tt detects frame time information from the received data from the loop supplied from the loop interface circuit D/1, and transfers it to the holding circuit REG.
i+ and REG2+, respectively. Here, it is assumed that the frame time cyclically repeats the values from 0 to N-11, that is, it takes the value of moclN. Holding circuit RE
G, I, and REG21 hold this information for one frame time and use it as one input of the comparison circuits CM P r and CM P R.

Here, the operation when a new call occurs from the sending node to the receiving node will be explained. The control processor PROC, which controls the transmitting node, transmits update information of the time switch control memo IJcM, accompanying the call, to the receiving node via the loop interface circuit D/I and one of the loops, and also communicates with the transmitting node and the receiving node. A value m (0≦m≦N-1) determined by the combination of nodes is set in the holding circuit RE G l 2. On the other hand, the control processor PROC2 that controls the receiving node receives and receives the update information from the loop interface circuit D/I, and
The value m is determined from the sending node number attached to the update information, and the value of m is set in the holding circuit REG22. Thereafter, both nodes are connected to the holding circuit REG12. REG2*
holding circuits that hold the value of m set in and the received frame time REG + +, RE G *I
The values of are compared by the comparator circuits CMPI and CMP2, and each time switch control memo is recorded in the frame where the values match! JCMs
, CMm is updated, and desired communication is newly established between both nodes.

The above explanation deals with the case where a new call occurs between the sending node and the receiving node, but the case where the currently active call is restored is also the same, except that the updated information in the time switch control memory is different. It can be processed using the following steps.

Next, a method for transmitting the frame time every frame from the system management node to other communication nodes will be explained using FIG. FIG. 2 is an example of a frame configuration provided on each loop in FIG. 1. That is, a frame is divided into a plurality of time slots, and frame synchronization pits and frame time display pits are also provided at appropriate intervals.

A fixed pattern is displayed in the frame synchronization bit, and a frame time is displayed in the frame time display bit. If the frame time display bit is n pits, the frame time from 0 to 2'-1, that is, the frame time counted by ma62'' is displayed here.
The relationship is N = 2''.The system management node is
It has an N-ary counter for counting time-division multiplexed frames, inserts a fixed pattern into the frame synchronization bits for each frame, and sends the value of the counter to the frame time display bits. By doing this, other general nodes extract the frame time at the same time as synchronizing the frame, and store that part in the holding circuit REG.
ll, can be supplied to RE G21. Note that a method of gathering the frame synchronization bits and frame time display bits at 1 m location within the frame, for example at the beginning, may be considered, but there is essentially no difference. Also, instead of arranging the frame time display bit at a fixed position within the frame, a method of inserting it at an arbitrary position with a unique header or identifier can be considered, but the effect is as follows.
It is exactly the same as that shown in FIG.

It is also possible to combine the functions of the system management node described above with those of a general communication node. In other words, one of the communication nodes is also provided with a system management function. The configuration of the communication node in this case is shown in FIG. The transmitting node in FIG. 3 corresponds to the communication node having the system management function described above. This communication node
Frame time detection circuit DET of the transmitting node in the figure,
An N-ary counter CNT is provided in place of the holding circuit REG, and its output is supplied to the comparison circuit CMP.
Interface circuit D as frame time display pit
It differs from general communication nodes in that it also supplies output to /I. Note that the operation of the second embodiment is similar to that of the first embodiment, so a description thereof will be omitted.

Now, various methods can be considered for determining m for a combination of a transmitting node and a receiving node.

For example, there is a method (first example) in which m matches the sending node number. In this case, the value N of the N-ary counter in the system management node matches the total number of communication nodes. This first example corresponds to providing a dedicated call setup/release frame time for each communication node. By doing this, even if call setup/release requests from each node overlap, the update processing times can be automatically avoided, and control between the nodes can be simplified. In this case, if the update processing capacity of the time switch control memory is a maximum of one call per frame in one communication node, the call setting/release processing capacity of the entire communication system is also one call/frame.

On the other hand, as another example (second example), there is a method in which the value of m is predetermined for each partner node in each node. If the above-described update processing capacity of the time switch control memory is one call/frame/communication node, the value of m must be different for each partner node in each communication node. In this case, the value of N in the N-ary counter is the maximum value of m+1. However, by doing this, at each frame time m, it becomes possible to set up/release a call in a set of multiple transmitting/receiving nodes to which m is assigned, and the call setting/release processing capacity of the entire communication system is reduced first. It is possible to increase it more than in the first example mentioned.

Furthermore, as a third example, there is a method in which the value of m is determined by a meeting between each node. In this method, each time a communication node is added to a communication system, control information and the like are transmitted and received between the new node and the existing node, and m is determined for each combination of nodes. Thereafter, call setup/release processing is performed using this value of m in the same manner as in the second example. Even in this method, if the above-mentioned update processing capacity of the time switch control memory is one call/frame/communication node, the values of m for each code will not match during the meeting between the nodes. It is necessary to select the value of m as follows. In this case, as in the case of the second example, it is possible to increase the call setup/release processing capacity of the entire communication system compared to the first example. Compared to the second example, m
Since each node autonomously determines the value of , the system can be expanded.

It has the advantage of being easy to change.

In addition to the above, there are other ways to assign the value of m, but
Either method can solve the interference problem mentioned in the conventional example, and since the update processing time is automatically determined by the combination of sending and receiving nodes, it is also possible to simplify the control between nodes. be.

By the way, the present invention is also applicable to general communication systems having shapes other than those shown in the above embodiments.

For example, it is effective for a normal electronic exchange system in which communication nodes having a time division multiplex time switch and a time switch control memory are connected by a space division switch, or a communication system in which the communication nodes are connected by a bus. In these systems, even if the frame times for updating the time switch control memory are different between communication nodes, interference as shown in the conventional example of the present invention does not necessarily occur. However, if the frame times for updating the time switch control memory differ between the transmitting node and the receiving node, problems arise such as unnecessary data other than the transmitted data appearing at the receiving node. Therefore, by similarly applying the present invention and making the frame times match, these drawbacks can be completely eliminated.

〔Effect of the invention〕

As explained above, according to the present invention, a call is generated.

During recovery, it is possible to match the frame times for updating the time switch control memory between the sending and receiving nodes, which has the excellent effect of preventing interference, which was a drawback of the conventional method, through simple control. It will be done.

[Brief explanation of drawings]

1 and 3 are explanatory diagrams showing the configuration of each node in the embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of the frame structure on the loop in the embodiment of the present invention, and FIG. FIG. 5 is a block diagram showing the configuration of a communication system to which the present invention is applied; FIG. FIG. 6 is a block diagram showing the configuration of a time switch according to the prior art and an outline of its operation. Ts... Time division multiplexing time switch for transmission T11... Time division multiplexing time switch for reception CMs... Time switch control memory for transmission CMm... For reception Time switch control memory D/I...Loop interface circuit DET, ,DET,...Frame time detection circuit CMP7. CMPz ・・・・・・Comparison circuit REG
11. REG12. REG21. REGzz...
・Holding circuit PROC+, PROCa ... Control processor CNT ... N-ary counter INF ・
...Interface circuit T...
・Time division multiplex time switch CM ・・・・・・Time switch control memory ASLI ・・・・・・Address shift unit agent Patent attorney Yoshiyoshi Iwasa Yukitomi Note-→
← Bow Toy Lazy Node - Figure 1 Frame Figure 2 - Send Note →
← Bow Toy Lazy Node-', Bigo l Zaket Figure 5

Claims (1)

[Claims] (1) A time division multiplex time switch of a communication system consisting of a time division multiplex time switch and a plurality of communication nodes having a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In the time division multiplex time switch control method, one of the communication nodes receives m
means for counting the frame time of the odN and means for transmitting the frame time to other communication nodes every frame;
and each of the other communication nodes is provided with means for receiving the frame time and holding it for one frame time, and when communication is set up or released between the communication nodes, the communication is set up or released between the communication nodes. After that, the communication node transmits the information to the communication node when the value of the frame time counted or received and held becomes equal to the value m of 0≦m≦N-1 determined by the combination of the communication nodes. A time division multiplexing time switch control method, characterized in that the contents of the time switch control memory are changed so that the communication is set or released.