CZ20013173A3 - Identification system - Google Patents

Abstract

An electronic tag (10) is provided which includes processor means and transmitter circuitry (26). The processor means, which is typically a micro-controller (16), is programmed to provide a modulation control signal which includes unique identification data which at least identifies the tag (10) but may include further data. The transmitter circuitry (26) is connected to the processor means and to an antenna (29) for transmission of the unique identification data. The transmitter circuitry (26) is powered by the modulation control signal. Preferably, the transmitter circuitry (26) is exclusively powered by the modulation control signal of the processor means. The invention extends to a receiver (12) for receiving a transmission from the tag (10) and to a system including a plurality of receivers (12) and tags (10). The invention also extends to a method of communicating data from an electronic tag (10) which includes driving transmitter circuitry (26) of the tag with a modulation control signal which substantially powers the transmitter circuitry (26).

Description

Technical field

The present invention relates to electronic labels. It also relates to a method of transmitting data from an electronic tag, an identification system and a receiver for receiving transmissions from the electronic tag.

SUMMARY OF THE INVENTION

According to the present invention, there is provided an electronic tag that includes processor means programmed to provide a modulation control signal that includes specific identification data that at least identifies the tag; and transmitter circuits connected to processor means and an antenna for transmitting said specific identification data, which transmitter circuits are powered by a modulation control signal.

Preferably, the transmitter circuitry is powered exclusively by the modulation control signal from the processor means. Therefore, the transmitter circuitry is not connected to another power supply, but only to ground and to processor resources. Thus, when the modulation signal is on the OVA, the transmitter circuitry is not powered, therefore no transmission occurs, thereby significantly reducing the energy consumption of the electronic tag. Thus, it is not a carrier wave and the output or identification signal is thus a pulse modulated wave alternating between 0 whi and its maximum amplitude.

Transmitter circuits may include passive components and a transistor forming oscillator circuits directly controlled by processor means. The transistor in combination with passive components can be an integral part of the transmitter circuits powered by the modulation control signal.

The processor means may be arranged to provide a modulation control signal having a first portion followed by a second portion. The first portion may comprise at least one pulse with a maximum amplitude (hereinafter a large pulse) of sufficient length to provide sufficient power to the transmitter circuits in part at least to stabilize it for transmitting the second portion. This second portion may contain data defined by a plurality of pulses of substantially shorter length. The signal emitted by the transmitter circuitry in the label resembles a combination of amplitude modulated signal and «« ·· * 44 · * ·

4 signal with pulse width modulation. The processor-controlled transmitter amplitude modulation is typically between about 0% and about 100%. Therefore, the energy consumption of the transmitter is substantially reduced when no data is transmitted. However, it is understood that transmitter circuits can modulate the amplitude of the identification signal with any modulation percentages between 0% and 100%, representing a number of values or levels and not just two levels corresponding to ones and zeroes (“1” and “0”).

The modulation control signal may include a plurality of large pulses which, in combination, provide an identification signal to a receiver in a label for receiving a broadcast from that electronic label. These pulses are typically about 60 psec long and use 50%. It is to be understood, however, that the utilization factor and / or pulse length may vary in different embodiments of the invention.

This portion of the maximum amplitude modulation signal can thus fulfill a double phasing. Firstly, it may increase the power consumption of the transmitter circuits between, preferably, a generally off or idle state to an operative state in which the circuits are sufficiently stabilized to transmit a second portion consisting of a pulse train of substantially shorter length. Second, the first part will allow the receiver to distinguish the transmission from the respective label from any other transmission, eg an interference signal or a signal from another source.

Each pulse of the second portion of the modulation signal may include a start portion for detecting the start of the bit and a data portion for determining the state of the data bit. The length of the data slot, when controlled by the processor means, can selectively define high and low bit states (HSB and LSB, respectively). The pulse width can be defined as the sum of the start and data slots.

The HSB is typically defined by a shorter data period during which the oscillator circuits are off and the LSB is defined by a longer data period during which the oscillator circuits are off.

A shorter pulse may be used to indicate or detect the start of a bit after which the oscillator circuits are completely off. The time interval or time for which the transmitter circuits will be switched on again determines the high or low state of the bit. The amount of energy required to transmit both HSB and LSB is essentially the same, since the energy is only consumed to determine the start of the data bit.

A typical processor means is a microprocessor that includes an internal RC oscillator from which a modulation control signal is derived, and the microprocessor is adapted to insert a sleep mode between data transmissions and thereby reduce power consumption. Therefore, the transmitter circuits, controlled by processor means, may be arranged to retransmit the burst identification signal at a predetermined time interval, for example about 1 sec. Preferably, the identification signal has a recovery factor of about 50%.

• * ··· • to •

The data is typically transmitted in digital form as a sequence of ones and zeros ("1" and "0"). Typically, "0" is transmitted by a transmitter activated about 10 psec, followed by its shutdown lasting for the same time, and "1" is transmitted by a transmitter activated about 5 psec, followed by its shut off for equal length, so that the signal has a 50% duty cycle. However, it is understood that any two different transmission time intervals controlled by the transmitter processor may be used to transmit "1" and "0". In addition, the utilization factor may vary.

According to the present invention, there is further provided an identification system comprising a plurality of electronic tags, each tag comprising processor means programmed to provide a modulation control signal comprising specific identification data that at least identifies the tag; and transmitter circuits connected to processor means and an antenna for transmitting said specific identification data, wherein the transmitter circuits are substantially powered by the modulation control signal; and at least one receiver in an electronic tag configured to receive broadcasts from the tag.

The transmitter circuitry in the electronic tag may be powered exclusively by a modulation control signal from the processor means.

The transmitter circuitry may include passive components and a transistor directly controlled by processor means. The transistor in combination with passive components can be an integral part of the transmitter circuits powered by the modulation control signal.

The processor means may be arranged to provide a modulation control signal having a first portion followed by a second portion. The first portion may comprise at least one large pulse of a length such as to supply sufficient power to the transmitter circuits, in part at least to stabilize them for transmitting the second portion. The second portion may contain data defined by a plurality of substantially shorter pulses.

The first portion of the modulation control signal may include a plurality of large pulses which, in combination, provide an identification signal to the signal detection means at the receiver in the electronic tag to receive the transmission from the electronic tag.

Each pulse of the second portion of the modulation signal may have a start section for determining the start of the bit and a data section for determining the state of the data bit, the length of the data section selectively defining the high and low state of the bit.

The HSB may be defined by a shorter data period during which the transmitter circuits are off, and the LSB is defined by a longer data period during which the transmitter circuits are off.

According to the present invention, in addition to the above, there is also provided a method of transmitting data from an electronic tag, the method comprising driving the transmitter circuitry in the tag with a modulation control signal that substantially powers the transmitter circuitry.

The modulation control signal typically powers the transmitter circuits exclusively

The transmitter circuitry may include an oscillator that is arranged to oscillate at its fundamental frequency when data is transmitted and stops oscillating when data is not transmitted. Accordingly, the method may include selectively modulating the base frequency of the oscillator when data is transmitted and decommissioning the oscillator when no data is transmitted.

The modulation control signal may have a first portion followed by a second portion, a first portion comprising at least one large pulse of a length to provide sufficient power to power the transmitter circuitry, at least partially to stabilize it to transmit a second portion containing data defined by a plurality of pulses substantially shorter.

The first portion of the modulation control signal may include a plurality of large pulses which, in combination, provide the receiver in the tag with an identification signal for receiving a transmission from the electronic tag.

Each pulse of the second portion of the modulation signal may have a start section for determining the start of the bit and a data section for determining the state of the data bit, the length of the data section selectively determining, while controlling the processor means.

The HSB may be defined by a shorter data slot during which the modulation control signal is switched off, and the LSB may be defined by a longer data slot during which the modulation control signal is turned off.

Preferably, the processor means is a microprocessor having an internal RC oscillator from which the modulation control signal is derived, and the microprocessor is adapted to insert a sleep mode between data transmissions and thereby reduce power consumption. The microprocessor, typically PIC 12C509 or similar, may be a transmitter processor programmed with appropriate software to perform said transmitter control method.

Still further according to the present invention there is provided a receiver for receiving a transmission from one of a plurality of electronic labels, a transmission comprising a first part and a second part, and the receiver comprising detection circuits for detecting the first part and the second part of the transmission, the first part comprising at least one large pulse. in response, the receiver monitors the reception of the second portion that contains data

«« ·· ··· ♦ ·· defined by the amount of substantially shorter pulses; and timing means for measuring the length of each of the pulses in the second portion and for selectively generating a high and low level output defining a bit depending on the length of the pulse.

The receiver may include pulse width detection circuitry to decode the identification signal.

The receiver may include receiving circuits connected to an antenna for receiving an identification signal from at least one electronic tag;

demodulation circuits connected to reception circuits for demodulating the identification signal, amplifying circuits connected to demodulation circuits by capacitive coupling; and receiver processor circuits connected to amplifier circuits for processing the identification signal after demodulation thereof.

The receiver may include a retransmitter for retransmitting the identification signal to the central control unit. Typically, each label is affixed to some valuable item, such as a personal computer or other valuable item located in a particular band, and the receiver monitors the transmission of an identification signal in that band. Accordingly, the central control unit may be in wireless communication with a plurality of bands, each having a receiver monitoring respective labels placed on valuable items or on a device in that band.

List of illustrations

The invention will now be described by way of example with reference to the accompanying schematic drawings. In these illustrations,

Giant. 1 shows a simplified circuit diagram of an electronic tag according to the invention;

Giant. 2 shows a simplified circuit diagram of a receiver, also according to the present invention; Giant. 3 shows a flow chart of a method of controlling data transmission by the label of FIG. 1;

Giant. 4 shows an example of a batch of data transmitted by a transmitter; and

Giant. 5 shows a flow chart of a method of decoding data by the receiver of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

Referring to these figures, an identification system according to the present invention is provided which includes a plurality of transmitters having the form of electronic tags JO (also according to the invention and this one only being shown) in the figures), each of which is associated with at least one receiver 12 (see FIG. 2). Typically, valuable items or devices to be monitored in a selected band, eg computers in a particular office area, are individually provided with a label 10 and a receiver 12 is positioned in that band to monitor signals received from the label JO. The receiver 12 is part of a network of receivers that can be installed in a particular building or similar location. Each receiver 12 is in communication with its central control unit (not shown) via its relay transmitter 14. Thus, the central control unit can monitor and record authorized and / or unauthorized removal of said device.

Each label 10 includes microprocessor transmitter processor means 16 with associated support circuits 18 and a long-life lithium battery 20 Designated microprocessor I / O ports 16 are connected to a connection terminal 22 through which the microprocessor 16 is programmed by a resident control method of the data transmission method. In use, reed relay 24 activates transitions of microprocessor 16 to various modes or modes of operation. In one mode of operation, the reed relay 24 can function as a sensor, e.g., motion detection, and the like. In another mode of operation, the reed relay 24 may function as a data input for inputting data to the internal memory of the microprocessor 16, e.g., data for unambiguously identifying the label 10. The microprocessor 16 controls the operation of the transmitter circuit 26.

As can be clearly seen from the circuit diagram shown in Fig. 1, the microprocessor has one of its output ports connected directly to the transistor 25 of the transmitter circuit 26. The transmitter circuit 26 also includes respective passive components 27, which in combination form an oscillator circuit. Furthermore, the transmitter circuitry 26 is not connected to the battery 20, but only to ground, and is powered solely by the modulation control signal from the microprocessor via the link 28. Thus, the transmitter circuitry 26 is flipped between on and off with its antenna 29 and off. when they don't get any energy and are completely out of order.

In order for the transmitter circuitry 26 to be stabilized for data transmission, the microprocessor 16 delivers three pulses to the transmitter circuitry 28 (single pulse portion 31 shown in FIG. 4), each pulse having a maximum amplitude segment of approximately 20 to 70 psec, typically approximately 60 psec and a recovery factor of 50%. Specifically, the modulation control signal generated by the microprocessor software 16 has a first portion followed by a second portion. The first section contains three large pulses of approximately 60 psec, which are generated by the “pulse 4” procedure in Table 2. As shown by arrow 150 in Table 2, the “pulse 4” subprocedure (see arrow • ·

152) is invoked three times. This portion of the maximum amplitude modulation signal provides a dual function. First, it increases the power consumption of the transmitter circuit between, preferably, a generally off or idle state to an operative state in which they are sufficiently stabilized to transmit a second portion consisting of a pulse train of substantially shorter length. Second, the first part will allow the receiver to distinguish the transmission from the respective label from any other transmission, eg an interference signal or a signal from another source.

The microprocessor 16 controls the transmission of specific identification data in the second portion of the modulation control signal by a method also according to the present invention performed by its resident software. The method used by the microprocessor 16 is summarized in Table 2 (see Arrow 154). Specifically, the microprocessor 16 controls the circuits of the transmitter 26 such that the signal it transmits or identifies has a pulse width and amplitude modulation. The amplitude modulation of the transmitted signal varies between about 0% and about 100% of the modulation in the representation of "1" and "0" (see Figure 3). The transmitted signal has a 50% duty cycle and “1” is transmitted, for example, at a pulse width of 5 psec, corresponding to an “on” time, followed by a 5psec corresponding to the “off” time, so the resulting total pulse width is 10 psec. In contrast, “0” is transmitted at a pulse width of 10 psec “on” and 10 psec “off” giving a total pulse width (length) of 20 psec. Thus, the total pulse length, i.e., either 10 psec or 20 psec, determines the state of the bit (see arrow 156 et seq. In Table 2). Many pulses are transmitted in a batch of data, and the batch is typically transmitted by label 10 periodically at a time interval of approximately 1 second. Of course, the pulses of the second portion need not necessarily have a utilization factor of 50%, since the pulse section 33 at maximum amplitude (see FIG. 4) acts as a marker or start section determining the start of the bit. Then the data section determines the state of the bit, while the length of the data section 35 is the total pulse width, including its "off". In the present embodiment, the data section 35 determines the HSB or LSB by the "off" time of the psec transmitter 10 circuits and the off-time of the 20 psec transmitter circuits, respectively (see Fig. 4). When the receiver 12 receives the transmission from the label 10, it detects the total pulse duration or duration, and assigns "0" or "1" as shown in Fig. 5.

Typically, the microprocessor 16 includes a counter whose count state is reset when the battery 20 is installed and which then registers an increment each time the transmitter circuitry 26 sends a batch of data. Data from the microprocessor 16 is fed to the transmitter circuit 26 via link 28. Of course, data transmitted by label 10 may include counter data, specific identification data for tag identification 10, data detected by reed relay 24, or any other data.

· «·« ··

To control the operation of the microprocessor 16, a crystal RC oscillator in the chip is not used. We are confident that this will reduce the power consumption of the JO label and reduce the start delay. In accordance with a further reduction in the power consumption of the label 10, the label 10 is in the idle state between each transmission of its burst of data. To achieve this, a second quiescent RC backup oscillator located in the microprocessor 16 is used. As seen in block 30, after a predetermined time interval, typically about 0.7 to 1 sec. (See arrow 158 in Table 2), the microprocessor 16 is instructed to start / wake. Then, a specific identification code and other data to be transmitted by the label 10 are issued as shown in block 32, whereupon the data is arranged in series as shown in block 34, where the next / first byte of the remaining bytes (indicated by X) applied to the transmitter circuit 26 as shown in block 36. The microprocessor 16 then analyzes each bit of the series sequentially (see block 38). If the bit is on logic "1", the transmitter circuitry 26 is activated to transmit a pulse having a maximum amplitude of 5 psec as shown in block 40, and then a low-level 5 psec portion as shown in the block is realized. 42 to achieve a duty cycle of 50% and a total pulse width of 10psec. However, if the bit is at logic "0", then the transmitter circuitry 26 is instructed to send a pulse with a maximum amplitude for 10 psec as shown in block 44, followed by a low-level portion also lasting 10psec as shown in block 46, which is shown in block 46, gives a utilization factor of 50% and a total pulse width of 20 psec if “0” is transmitted.

When all the bits from that byte as outlined in block 48 have been transmitted, the microprocessor 16 is then instructed to raise the pointer to the next byte as outlined in block 50 (see also arrow 154 in Table 2). However, if not all 8 bits have been transmitted from the byte, then the microprocessor 16 is instructed to take the next bit as shown in block 52 and the above procedure is repeated. As shown in block 54, if the last byte of a given batch of data has been transmitted, then the microprocessor 16 enters a sleep or sleep mode for a predetermined period of time (see block 55). However, if the last byte has not been transmitted, then the microprocessor 16 takes the next byte as shown in block 34.

Referring in particular to Fig. 2 of the figures, receiver 12 includes receiver processor 56 implemented by receiver microprocessor 58, e.g., PIC 16F64 and the like. The designated I / O ports of the receiver microprocessor 58 are connected to the I / O terminals 60 to be able to program the microprocessor 58 with resident software from an external device such as a PC or the like. Receiver microprocessor 58 is connected via link 62 to retransmitter transmitter 14, whose circuitry is substantially similar to transmitter circuit 26, and retransmitter transmitter 14 has a transistor 64 that is selectively turned on and off by receiver microprocessor 58 to generate "1" and "0" and thereby retransmits the signal received by the receiver 12 to the central monitoring or control unit. As in the case of transmitter circuitry 26, transmitter 14 draws power to operate directly from the modulation control signal supplied to the microprocessor output port 58 via link 62.

The identification signal transmitted by the label 10 is received by the receiver circuitry 68 whose output signal is routed to the RF amplifier 74 and the link 72 to the demodulator circuit 70. The output of the demodulator circuit 70 is connected via a decoupling capacitor 76 to amplifier circuits generally indicated by 78, consisting of from a series of operational amplifiers. The output stage of the operational amplifiers is connected to the microprocessor port of the receiver 58 via a link 80. Power is supplied to the various components of the receiver 12 by the power supply unit 82.

The designated I / O ports of the receiver microprocessor 58 are connected to a programming terminal 84 through which the appropriate receiver control software 12 is inserted into the receiver microprocessor 58. The receiver control method 12 is shown in Table 1 and described in more detail below.

Referring in particular to FIG. 5 of the figures, the receiver software first comprises a method of resetting the bit / byte information as shown in block 86. Initialization of the bit / byte information and various other function parameters is generally indicated by arrow 160 and subsequent in Table The arrow 162 indicates the start of the procedure when the microprocessor ports 58 are initialized. The software implementing the procedure then waits for the high-level input (with maximum amplitude) as shown in block 88. If received, the pulse length is checked. Specifically, the "HIG 1" procedure (see arrow 164 in Table 1) determines the length corresponding to the maximum pulse amplitude and the "HIG 2" procedure determines the length corresponding to the low level (see arrow 166). Then, the sum of the lengths corresponding to both levels is calculated to verify that the total length is within acceptable limits, which is typically between about 50 and about 70 psec. Thus, the pulse interval is counted or determined or the time for the next large pulse is received. is given in block 90. If this interval is 10 psec (i.e., 5 psec maximum amplitude followed by 5 psec low level) as shown in block 92, then the incoming bit from the batch of data received from label 10 is "1" as The bit counter is then incremented by one as shown in block 96, and if it is the last bit calculated (see block 98). then the bit / byte value is reset, as shown by connector 100 leading to block 86. However, if this interval is not equal to 10 psec, then it is measured with a timer to determine whether or not approximately 20 psec (i.e. 10 psec maximum amplitude) followed by 10 psec low level). If 20 psec is equal, then the bit is recognized as “0” as shown in block 104, and the bit counter state is again incremented as shown in block 96. However, if the interval is not equal to 20 psec, then the procedure includes The procedure for recognizing "1" and "0" is generally indicated by an arrow in Table 1. Table 1 also contains various other procedures, such as the RS 232 procedure for data delivery. to other devices. Of course, the microprocessor of the receiver 58 may have different versions of additional procedures allowing the transmission of data received from the label 10 to communicate with other devices.

The inventor believes that the present invention, as described, provides an identification system including a method of transmitting data from a label 10 to a receiver 12 exhibiting reduced power consumption. Features of the invention that support this low power consumption include supplying the transmitter circuitry 26 via a modulation control signal and an arrangement in which the bit state is determined by the "off" time of the transmitter circuitry 26. The power consumption of the label 10 is also substantially reduced when the label 10 its sleep or sleep mode '' ~ / IDUjftUtjgtXU «* • 99« • 99

999

TABLE 1 ds5000 dev capetown system with dave update check for freq and cost less than 64 current program

START SEQUENCE CORRECTED FOR THE ERRORS AND SPEED INCREASE

BIT 1 OF DATA CORRECTED

DECREASE START FRAME HIGH AND LOW

ADD CHECK FOR CHECKSUM data sheet p = 16f84, f β inbx8m, _CONFIG 3FF1H

INDIR = 0

FSR = 4

PORTA = 5

PORTB = 6

TRISA = 85h TRIS8-86h TMRO = 1 STATUS a = 3 PCL 2 OPTN = 81h INTCONasQB

RPO EQU 5 TEMP2 EQU 11b TEMP1 EQU 12h T1MER1 EQU 13h TIMER VALUE TEMP VALUEX EQU 14b ; TEMP DIGIT1 EQU 15h ; TEMP DIGIT2 EQU 16h , 'TEMP DIGIT3 EQU 17h , -TEMP ASCII EQU 18h ; TEMP VALUE EQU 19h TEMP equ 20h -Temporary storage location CHAR EQU 21h Cbaracter storage location- DIGÍTS EQU 22h VALUE1 EQU 23h VALUE2 EQU 24h VALUE3 EQU 25b VALUE4 EQU 26h VALUES EQU 27h VALUES EQU 28h VALUE7 EQU 29h VALUES EQU 2Ah VALUES EQU 2Bb VALUE10 EQU 2Ch VALUE11 EQU 2Dh VALUE12 EQU 2Eh VALUE13 EQU 2Fh VALUE14 EQU 30h CALB EQU 31h CALA EQU 32h DUNE EQU 33h

SPARE PART (RULE 26)

YOU IN WWW)

........

CHECK1 EQU 36h CHECK2 EQU 37h CHECK3 EQU 38h CHECKX EQU 39b CSUM EQU 3Ah , -CHECK SUM CSUM 2 EQU 3Bh GIVE EQU PORTB CNTRL EQU PORTA E EQU 3 RW EQU 2 RS EQU 1 C EQU 0 W EQU 0 F EQU 1 P EQU 0 START CLRF OLINE CLRF CHECK1 call LCDInit call LCDInit CALL LCDInit BCF PORTB.O .MAIN .TIMER / COUNTER SETUP movlw OPTN movwf FSR movlw OOh 20h = counter + no prescaler movwf INDIR clr TMRO bcf STATUS. RPO pulp PORTA drf PORTB .Configure ports A and 0 to outputs bsf STATUS. RPO ; Selections Register page 1 movlw ΒΌΟΟΟΟΟΟΟ * ; Set lower 4 bits in PORTB movwf TRISB as outputs movlw ΒΌ0000011 ' Set port and as outputs movwf TRISA bcf STATUS, RPO , Se! Ect Register page 0 pulp PORTA clear pon.a MOVLW .5 MOVWF TEMP2 MOVLW .10 MOVWF TIMER1 MOVLW .100 MOVWF TEMP1

SPARE PART (RULE 26): PtT / ltf00 / Ig220

444

WO 0U / 526J6

4444

ZXC INCF TEMPU INCF TEMPU INCF TEMPU CALL BEEP DECFSZ TEMP2.1 GOTO zxc

CLRF PORTA MAIN BCF ΡΟΚΤΒ, Ί BCF R0RTB.4 BCF PORTA.O NOP CLRF CSUM SSA BTFSS CHECK1, GOTO HIG1 BSF PORTB.4 MOVLW WAS 2 MOVWF TEMP2 MOVLW .10 MOVWF TIMES 1 MOVLW .100 MOVWF TEMP1 ; XXC CALL BEEP DECFSZ ΤΕΜΡ2.Ί GOTO XXC MOVLW .50 MOVWF T1MER1 RTR1 MOVLW , 200 MOVWF CHECK2 RTR MOVLW .200 MOVWF TEMP1 RTR2 DECFSZ TEMPU GOTO RTR2 DECFSZ CHECX2 GOTO RTR DECFSZ TIMER1 GOTO RTR1 BCF P0RT3.4 CLRF CHECX1 CLRF CHECKX HIG1 BTFSS PORTA.O GOTO HIG1 CLRF TEMP1 HWW1 NOP

, Β O; TO OPEN DO UN REMARK; 100 = 3sec

164

SPARE PART (RULE 26) wu uwxíojo / ί. ! ϊ? φ * / {ρ <ΜφΐΜΚ2υ.: ...:. ·: · ......

ΝΟΡ ΝΟΡ INCFSZ TEMP1.F GOTO GOTO HWZ1 HIG1 HWZ1 BTFSC PORTA.O GOTO HWW1 wait for HIGH • BTFSC TEMP1.3 ; 8 GOTO HIG2 BTFSC GOTO TEMP1.4 HIG2 ; 16 BTFSC GOTO TEMPU HIG2 ; 32 BTFSC TEMPU 64 - GOTO HIG2 BTFSC GOTO GOTO TEMPU HIG2 HIG1 128 H1G2 CLRF TEMP! I66 HWW2 NOP NOP NOP INCFSZ TEMR1.F

GOTO GOTO HWZ2 HIGl HWZ2 BTFSS PORTA.O GOTO HWW2 , -wait for HIGH BTFSC TBWP1.3 ; 8 GOTO HIG3 BTFSC TEMP1.4 , ‘1S GOTO HIG3 BTFSC TEMP1.5 ; 32 GOTO HIG3 BTFSC TEMPU 64 GOTO HIG3 BTFSC TEMPU 128 GOTO HIG3 GOTO HIGl HIG3 CLRF TEMP1

HWW3 ŇOP

ΝΟΡ

ΝΟΡ

INCFSZ TEMPl.F

GOTO HWZ3 GOTO HIG1 HWZ3 BTFSC PORTA.O GOTO HWW3 wait for HIGH BTFSC TEMPU ; 8 GOTO HIG4 BTFSC TEMPU ; 16 GOTO HIG4 BTFSC TEMP1.5 : 32 GOTO HIG4 BTFSC TEMPU 64 GOTO HIG4 BTFSC TEM Fri, 7 .128 GOTO HIG4 GOTO HIG1

SPARE PART (RULE 26)

• · · ·

.. * », ·

HIG4 CLRF TEMP1 HWW4 NOP NOP NOP INCFSZ TEMPl.F GOTO HWZ4 GOTO HIG1 HWZ4 BTFSS PORTA.O GOTO HWW4 wait for HIGH BTFSC TEMP 1.3 ; 8 Ř GOTO H1G5 BTFSC TEMP1.4 ; 16 GOTO HIG5 BTFSC TEMP! , 5 : 32 GOTO HIG5 BTFSC TEMPU 64 GOTO HIG5 BTFSC TEMPU .128 GOTO HIG5 GOTO H1G1 HIG5 CLRF TEMP1

WNVJ5 NOP

NOP ΝΟΡ

INCFSZ TEMP1.F

GOTO GOTO HWZS HIG1 HWZ5 BTFSC PORTA.O GOTO HWW5 wait for HIGH BTFSC TEMPU ; 8 REPETER ONLY GOTO HIG6 BTFSC TEMPU ; 16 GOTO HIG6 BTFSC TEMP1.5 ; 32 GOTO HIG6 BTFSC TEMPU 64 GOTO HIG6 BTFSC TEMPU 128 GOTO HIG6 GOTO HIG1 HIGS CLRF TEMP1

HWW6 ΝΟΡ

ΝΟΡ ΝΟΡ

INCFSZ TEMP1.F

GOTO GOTO HWZ6 HIG1 HWZS BTFSS PORTA.O GOTO HWW6 wait for HIGH BTFSC TEMPU ; 8 and GOTO HIG7 BTFSC TEMPU ; 16 GOTO HIG7 BTFSC TEMPU ; 32 GOTO HiG7 BTFSC TEMPU : 64 GOTO HIG7

SPARE PART (RULE 26) «*

: *: 16 ............... BTFSC 7ΕΜΡΊ / 7 128 GOTO HIG7 GOTO HIG1

HIG7

END

SX1

LX1

NOAH

CLRF VALUE1 BTFSC PORTA.O GOTO SX1 INCF VALUE1 MOVLW .200 MOVWF VALUE2 DECFSZ VALUE2.F GOTO NOAH GOTO ENDF BTFSS ΡΟΚΤΑ, Ο GOTO LX1 GOTO SX1

ENDF GOTO SKIPP

NOP

CLRF VALUE1

CALL WAÍTD

MOVF T1MER1.W

MOVWF VALUE1

CALL WAÍTD

MOVF TIMER1, W.

MOVWF VALUE2

CALL WAÍTD

MOVF TIMER1.W

MOVWF VALUE3

CALL WAÍTD

MOVF TIMER1, W.

MOVWF VALUE4

CALL WAÍTD

MOVF TIMER1.W

MOVWF VALUE5

CALL WAÍTD

MOVF TIMER1, W.

MOVWF VALUE6

CALL WAÍTD

MOVF TIMERt.W

MOVWF VALUE7

SPARE PART (RULE 26)

17 . ·; * LL ~ r / lttUWU «229 ··· »· · ··· * CALL WAITD MOVF TJMER1.W MOVWF VALUE8 CALL WAITD MOVF TIMER1.W MOVWF VALUE9 CALL WAITD MOVF TIMER1.W MOVWF VALUE1O CALL WAITD MOVF TIMER1.W MOVWF VALUE11 CALL WAITD MOVF TEAM ERI, W MOVWF VALUE12 CALL WAITD MOVF T1MER1W MOVWF VALUE13 CALL WAITD MOVF TIMER1.W MOVWF VALUE14 CALL WAITD MOVF T1MER1.W MOVWF VALUE15 CALL WAITD MOVF TIMER1, W. MOVWF VALUE16 CALL WAITD : CHECK SUM MOVF TIMER1.W MOVWF CSUM MOVLW .98 REC ID MOVWF; CHECK DATA VALUE15 goto tst7 MOVF VALUE1.W ADDWF VALUE2.W ADDWF VALUE3.W ADDWF VALUE4.W ADDWF VALUES.W ADDWF VALUE6.W ADDWF VALUE7.W ADDWF VALUE8.W ADDWF VALUES.W ADDWF VALUE10.W ADDWF VALUEfl.W ADDWF VALUE12.W ADDWF VALUE13.W

REPLACEMENT PAGE (RULE 26) '· VZ M ¥ »

BBB · BBB

A · A x x A * Α ***> BB BBB BB

ADDWF VALUE14.W ADDWF VALUE15.W MOVWF CSUM2 MOVF CSUM, W. CHECK SUM

SUBWF CSUM2.W

MOVWF TEMP1 BTFSC TEMPU GOTO OUT; BTFSC TEMPU J GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMP1.4 GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT MOVF CSUM2.W CHECK SUM

SUBWF CSUM, W.

MOVWF TEMP1 BTFSC TEMPU GOTO OUT BTFSC TEMPU; GOTO OUT; BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO our BTFSC TEMPL4 GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT

MOVF VALUE2.W ; CHECK STATE AND FREQ MOVWF TEMP1 BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT MOVF VALUE3.W CHECK STA AND FREQ MOVWF TEMP1 BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT

SPARE PART (RULE 26) «·» ·

goto tsp7 ; skip looking for P oř Q look for P OR Q MOVLW .80 ; was 80h iess bitO SUBWF VALUE 16 W MOVWF TEMP1 BTFSC TEMPU LOOK FOR P ONLY GOTO OUT; HEM = BTFSC TEMPU P, Q, R.S GOTO OUT * BTFSC TEMP! , 2 GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMPU GOTO OUT BTFSC TEMP1,5 GOTO OUT BTFSC TEMP! , 6 GOTO OUT BTFSC TEMP1,7 GOTO OUT

; TURN ON 10 PORTB 0 PIN 7 MOVW .84 ; T SUBWF VALUE1.W MOVWF TEMP1 BTFSC TEMPU ; remark GOTO KKK WAS KKL BTFSC TEMPU GOTO KKK BTFSC TEMPU GOTO KKK BTFSC TEMPU GOTO KKK BTFSC TEMP1.4 GOTO KKK BTFSC TEMPU GOTO KKK BTFSC TEMPU GOTO KKK BTFSC TEMPU GOTO KKK INCF CHECK1 GOTO KKD MOVLW .69 ;E

SUBWF VALUE1, W.

MOVWF TEMP1 BTFSC TEMPU , -remark GOTO KXS WAS KKL BTFSC TEMPU GOTO KKS BTFSC TEMPU GOTO KKS BTFSC TEMPU

REPLACEMENT PAGE (RULE 26) • * VI * KkVU / UU ^ Af 4 4 ’c 'cJ · J \ ff« 4 4 4 4 4 4

4 4 4 4 4 5

4444 444 444 · 44 44 444

GOTO KKS BTFSC TEMP1.4 GOTO KKS BTFSC TEMP1.5 GOTO KKS BTFSC TEMP1.6 GOTO KKS BTFSC TEMPU GOTO KKS INCF CHECKX GOTO KKD KKS CLRF CHECK1 CLRF CHECKX KKD BSF P0RTB.4 MOVLW .5 MOVWF TEMP2 MOVLW .20 MOVWF TIMER1 MOVLW .200 MOVWF TEMP1 MOVLW .50; 100 MOVWF T1MER1 RTR1 MOVLW .200 MOVWF CHECK2 RTR MOVLW .200 MOVWF TEMP1 RTR2 DECFSZ TEMP1.F

GOTO RTR2

DECFSZ CHECK2

GOTO RTR

DECFSZ TIMER1

GOTO RTR1

KKL; check for alarm on

OKD MOVLW -50; was SUBWF VALUE3.W MOVWF TEMP1 BTFSC TEMP1.0 GOTO OUT3; WAS BTFSC ΤΕΜΡΊ, Ι GOTO OUT3 BTFSC TEMP1.2 GOTO OUT3 BTFSC TEMPU GOTO OUT3 BTFSC TEMP1A GOTO OUT3 BTFSC TEMP1.5 GOTO OUT3 BTFSC TEMP1.6 GOTO OUT3

SPARE PART (RULE 26). . .i • t '“· * *« «« «« «« «« «i i i i i

0UT2

ZXC1

0UT1

CUT3

OUT

BTFSC GOTO TEMP 1,7 OUT3 CLRF CHECK1 GOTO OUT2; WAS 1 -ALARM ON BEEP MOVLW .5 MOVWF TEMP2 MOVLW .10 MOVWF TIMER1 MOVLW .100 MOVWF TEMP1 TEMPU fNCF TEMPU INCF TEMPU CALL BEEP DECFSZ TEMP2.1 GOTO ZXC1 MOVLW .200 MOVWF TIMER1 MOVLW .100 MOVWF TEMP1 CALL BEEP GOTO SKIPP NOT SEEN AND T .SEEN UNIT NOT A TO SO SET OFF BTFSS CHECK1.3 INCF CHECK1.F BTFSS GOTO OUT3 NOP GOTO 0UT2 CHECK1.3 MOVLW .10 MOVWF T1MEH1 MOVLW .20 MOVWF TEMP1 CALL BEEP GOTO SKIP

; VALUE NOT RIGHT RETURN

ALARM 1F SEEN MORE THAN 4 TIMES; WAS 3; 5ET OFF ALARM

READ AGAIN

MOVLW .200

MOVWF T1MER1

MOVLW .100

SPARE PART (RULE 26) *

T J t ί.

· UurwA ^ U »· U U U

· · ·

t MOVWF CALL TEMP1 BEEP GOTO MAIN SKIPP OUTV BSF P0RTB.1 GOTO GKL TOR NO DISPLAY

GKL; SEND ONLY ALARM DATA

BTFSS PORTA, 1

GOTO TX2

MOVLW .50; was2A = T

SUBWF VALUE3.W

MOVWF TEMP1 BTFSC TEMP1-0 GOTO TX1 BTFSC TEMPU GOTO TX1 BTFSC TEMPU GOTO TX1 BTFSC TEMPU GOTO TX1 BTFSC TEMPU GOTO TX1 BTFSC TEMPU GOTO TX1 BTFSC TEMP1,6 GOTO TX1 BTFSC ΤΕΜΡΊ.7 GOTO TX1 GOTO TX2 GOTO MAIN

TX2

PC VERSION FOR DS5000 MOVLW 65h CALL TXDATA MOVLW 65h CALL TXDATA MOVLW .33 CALL TXDATA MOVLW .42 CALL TXDATA

SPARE PART (RULE 26)

4 · «

MOVLW .42 CALL TXDATA MOVF VALUE1.W CALL TXDATA MOVF VALUE2.W CALL TXDATA MOVF VALUE3.W CALL TXDATA MOVLW .65 CALL TXDATA MOVLW .66 CALL TXDATA MOVLW .67 CALL TXDATA MOVF VALUE4.W CALL TXDATA MOVF VALUE5.W MOVLW .48 CALL TXDATA MOVF VALUE6.W CALL TXDATA MOVF VALUE7.W CALL TXDATA MOVF VALUEB.W CALL TXDATA MOVF VALUEl.W CALL TXDATA MOVF VALUE9.W CALL TXDATA MOVF VALUE10.W CALL TXDATA MOVF VAÍUE11.W CALL TXDATA MOVF VALUE12.W CALL TXDATA MOVF VALUE13.W ΑΛΙ 1 VrZKÍ.L TXDATA MOVF VALUE14.W CALL TXDATA MOVF VALUE15.W CALL TXDATA MOVF VALUE16.W CALL TXDATA MOVLW .43 CALL TXDATA MOVLW OAh CALL TXDATA MOVLW ODh CALL TXDATA MOVLW SOh CALL TXDATA BSF PORTB.2

SPARE PART (RULE 26) ··· * · * ·· ·

TERRYX

MOVLW .01 MOVWF CHECK3

TERRYY

GOTO GOTO; tx data on MAIN NOTX MOVF VALUE1.0 ADDWF VALUE2.0 ADDWF VALUE3.0 ADDWF VALUE4.0 ADDWF VALUE5.0 ADDWF VALUE5.0 ADDWF VALUE7.0 ADDWF VALUE8.0 ADDWF VALUE9.0 ADDWF VALUE 10.0 ADDWF VALUE11, O ADDWF VALUE12.0 ADDWF VALUE13.0 ADDWF VALUE14.0 ADDWF VALUE15.0 MOVWF CSUM

MOVLW MOVWF 20h; TEMP! moviw 21h movwf TEMP HI. pulse4 MOVLW 20h MOVWF TEMP1 MOVLW 20h MOVWF TEMP CALL pul $ e4 moviw 21h movwf TEMP call pulse4 MOVLW .04 MOVWF TEMP1 movf VALUE 1.0 movwf TEMP call pulse movf VALUE2.0 movwf TEMP call pulse

WAS 20 YES START; TX ON TIME

SPARE PART (RULE 26) • this this * this this it this this »« to • «··« · «• to ··· ·« ··· ·· ·

movlw .50 movf VALUE3.0 movwf TEMP call pulse movf VALUE4.0 movwf TEMP call pulse movf VALUE5.0 movwf TEMP call pulse movf VALUE6.0 movwf TEMP call pulse movf VALUE7.0 movwf TEMP call pulse movf VAL (JE8) movwf TEMP call putse movf VALUE3.0 movwf TEMP call pulse movf VALUEIO.O movwf TEMP call putse movf VALLfE11 Q movwf TEMP call pulse movf VALUE12.0 movwf TEMP call pulse movf VALUE13.0 movwf TEMP call pulse movf VALUE14.0 movwf TEMP call pulse movf VALUE15.0 movwf TEMP call pulse movf VALUET6.0 movlw .83 movwf TEMP call pulse

MOVF CSIINLO

SPARE PART (RULE 26)

4444 »4 5 ·

_f - - _r + 14 4

44

4

4 «

44

MOVWF TEMP CALL puise call pulseS DECFSZ CHECK3.F GOTO TERRYY NOTX

MOVLW 65h CALL XXDATA MOVLW 65h CALL XXDATA MOVLW .33 CALL XXDATA MOVLW .42 CALL XXDATA MOVLW .42 CALL XXDATA MOVF VALUELW CALL XXDATA MOVF VALUE2.W CALL XXDATA MOVF VALUE3.W CALL XXDATA MOVLW .65 CALL XXDATA MOVLW .66 CALL XXDATA MOVLW .67 CALL XXDATA MOVF VALUE4.W CALL XXDATA MOVF VALUE5.W MOVLW .43 CALL XXDATA MOVF VALUE6.W CALL XXDATA MOVF VALUE7.W CALL XXDATA MOVF VALUE3.W CALL XXDATA MOVF VALUELW CALL XXDATA MOVF VALUE3.W CALL XXDATA MOVF VALUEIC.W CALL XXDATA MOVF VALUE1LW CALL XXDATA MOVF VALUE12.W CALL XXDATA MOVF VALUE13.W

SPARE PART (RULE 26)

V 1 / ·

•> · * · · · · · · · · · 2 / ··· »· * · ··· ··· ·· ··· CALL MOVF CALL MOVF CALL MOVF CALL MOVLW CALL XXDATA VALUE14.W XXDATA VALUE 15, W. XXDATA VALUE16.W XXDATA .48 XXDATA MOVLW CALL MOVLW * CALL MOVLW CALL . MOVLW CALL OAh XXDATA ODh XXDATA 80h XXDATA 8Oh XXDATA BCF PORTB.2 GOTO MA1N

pulse

BTFSS CALL BTFSC cafl ΤΕΜΡ, Ο puíseB ΤΕΜΡ, Ο pulse2 BTFSS CALL BTFSC call TEMP.1 pulse3 TEMP.1 puise2 BTFSS CALL BTFSC n *> ll Ulili TEMP.2 pulse3 TEMP, 2 pips2 BTFSS CALL * BTFSC call TEMP.3 pufseS TEMP, 3 pips2 * BTFSS CALL BTrSC call TEMP.4 pulse 3 TEMP, 4 pulse 2 BTFSS CALL BTFSC call TEMP.5 pulse3 TEMP.5 pulse2

REPLACEMENT PAGE (RULE 26).

• return pulse6

BTFSS TEMP.6 CALL puise3 BTFSC TEMP.6 call pulse2 BTFSS TEMP.7 CALL pulseS BTFSC TEMP, 7 call pulse6 CALL puJse5 clrwdt

ding

TNY2

MOVF movwf bsf NOP NOP NOP TEMP1.W TIMER1 PORTB.3 nop nop nop nop ; new nop nop nop decfsz T1MER1.1 goto dííig BCF PORTB.3 MOVLW .22 MOVWF TIMER1 DECFSZ T1MER1.1 GOTO TNY2

; on fo 3 6 9 12 ETC.

; cycie 46 turn off; was 13

RETURN puiseZ clrwdt

MOVF TEMP1.W movwf TIMER1 bsf ddgf WCP NCP , 'JOP NCP NCP NOP NOP PORTB.3

; on fo 3 6 9 12 ETC.

replacement page (rule 26)

V UUIJmUJU ijv ιιι ^ ννι ^ μύΜ · · n n «n || || n n n n n n

decfsz goto BCF TIMERU ddgf PORTB.3 cvd 46 turn off MOVLW .17 WAS 13 MOVWF TIMER1 DECFSZ TIMERU GOTO TNY1

RETURN pulse5 cfrwdt

MOVF TEMP1.W new TIMER1 bsf PORTB.3; on foR 3 6 9 12 ETC.

(tigg NOP

NOP

NOP decfsz TIMERU goto digg

BCF PORTB.3; cyde 46 turn off

NOP

NOP

NOP

NORWEGIAN

NOP

NOP

RETURN pulse 3 cfrwdt MOVF TEMP1.W movwf TIMER1 bsf PORTB.3 on fo 3 6 9 12 ETC digpp NOP NOP NCP decfsz TIMERU goto digpp 3CF PORTa.3 ; cycie 46 turn off MOVLW .3 MOVWF T1MER1 TNY4 NOP NOP NOP DECFSZ TIMERU GOTO TNY4

REPLACEMENT PAGE (RULE 26) ftCT / IBOO / OOMO * 9 · 9 · 9 · 9 · 9

II • • • • 4 ”TV / UW-JJVJV * 1 *

RETURN dcph digf pulse4

clrwtft MOVF TEMP1, W. movwf TIMER1 NOP NOP 12 CYCLES NOP NOP bsf P0RTB, 3 NOP NOP NOP decfsz TiMEHIJ goto digph BCF ΡΟΠΤΒ.3 NOP NOP NOP decfsz TEMP.1 goto digf NOP NOP RETURN

on for 46us; cyde 46 tum off

TXDATA

MOVWF TEMP cail PPSE2 nop eg eg nop nop BTFSS ΤΕΜΡ, Ο CALL PPSE2 o i Fob PACE cail PPSE3 BTFSS TEMP.1 CALL PPSE2 3TFSC TEMP.1 cail PPSČ3 3TF3S TEMP.2 CALL PPSE2 3TFSC TcMP.2 CAL! PPSE3 BTFSS TEMP, 3 CALL PPSE2 BTFSC TEMP, 3 cail PPSE3

SPARE PART (RULE 26)

WO 00/52636

Ρ £ Ϊ7ΙΒ0Ϊ) / ΰ $ 220 · • »« «220

BTFSS TEMP.4 CALL PPSE2 BTFSC TEMP.4 call PPSE3 BTFSS TEMP.5 CALL PPSE2 BTFSC TEMP.5 call PPSE3 BTFSS TEMP.6 CALL PPSE2 BTFSC TEMP.6 call PPSE3 BTFSS TEMP.7 CALL PPSE2 BTFSC TEMP.7 call PPSE3 CALL PPSE3 call PPSE3 rewrn XXDATA MOVWF TEMP call PPSE3 call PPSE3 call PPSE3 call PPSE3 call PPSE3

call nop nop nop nop nop XPSE2 BTFSS ΤΕΜΡ, Ο CALL XPSE2 3TFSC ΤΕΜΡ, Ο call XPSE3 5TF5S ΤΕΜΡ, Ί CALL XPSE2 2TFSC TEMP.1 call XPSE3 BTFSS TEMP.2 CALL XPSE2 BTFSC TEMP.2 call XPSE3 BTFSS TEMP, 3 CALL XPSE2

SPARE PART (RULE 26) \ j υυ / jiiv-vv • · 44 ·

4 4 • 4 • 44 444

* 4 4

BTFSC call TEMP, 3 XPSE3 BTFSS TEMP.4 CALL XPSE2 BTFSC TEMP.4 call XPSE3 BTFSS TEMP, 5 CALL XPSE2 BTFSC TEMP, 5 call XPSE3 BTFSS TEMP.S CALL XPSE2 8TFSC TEMP.S call XPSE3 BTFSS TEMP, 7 CALL XPSE2 BTFSC TEMP.7 call XPSE3 CALL XPSE3 call XPSE3 CALL XPSE2

return

PPSE2 clrwdt MOVLW .7 movwf TEMP1 bsf PORTB.2 dlgfih decfsz TEMPU

; on fo 3 6 9 12 ETC.

goto díghh

NOP

NOP

NOP

RETURN

PPSE3 clrwdt diggh MOVLW movwf bcf decfsz .7 TEMP1 PORTB.2 TEMPU RETURN goto NOP NOP NOP 1 diggh

; on fo 3 6 9 12 ETC.

XPSE2 clrwdt MOVLW .7 movwf TEMP1 bcf PORTB

; was bsf on foR 6 6 12 ETC.

SPARE PART (RULE 26)

VW W VWJ4VWV · · to · to to to * to * * to * to

Xighh decfsz goto NOP NOP NOP

RETURN

XPSE3

TEMP1,1

Xighn clrwdt

Movlw movwf bsf

Xiggh decfsz goto NOP NOP NOP

RETURN .7

TEMP!

PORTB.2; was bcf on foR 3 6 9 12 ETC.

TEMPU

Xiggh

BEEP

DS2 movf movwf SSF TEMP1, W. TEMP PORTBJ SD2 decfsz TEMP.F goto SD2 BCF PORTBJ movf TEMP1.W movwf TEMP SD3 decfsz TEMP.F goto SD3 DECFSZ TIMERI.F GOTO lipům DS2

; WAS1

WAITD

CLRF

CALL

BTFSC

BSF

CALL

3TFSC

SSF

CALL

BTFSC

SSF

CALL

BTFSC

BSF

CALL

BTFSC

SSF

CALL

BTFSC

BSF

TIMER1

WAITD D

TEMPU

TIMERU

WAITD D

TEMPU

TIMERU

WAITD D

TEMPU

TIMERU

WAITDD

TEMPU

TIMERU

WAITDD

TEMP! .3

TIMERU

WAITDD

TEMP! , 3

TIMERU

REPLACEMENT PAGE (RULE 26).

> «· ··· •» · * · ·. · · ·· ···

CALL WAITDD BTFSC TEMP1,3 BSF TIMER1.6 CALL WAITDD BTFSC TEMPU BSF TIMER1.7

RETURN WAITDD CLRF TEMP1 S1 incf TEMP1.F

NOP

NOP

ΝΟΡ

ΝΟΡ

ΝΟΡ

ΝΟΡ

BTFSC PORTA.O

GOTO S1

L1 nop nop nop nop

INCFSZ TEMPU

LL1 GOTO GOTO BTFSS LL1 HH1 PORTA.O GOTO IF

HH1 RETURN Λ CPA MOVLW 2Oh and CALL TXDATA MOVLW .48 MOVWF ASCII

RPT4 INCF DECFSZ GOTO MOVLW MOVWF MQVF call DIGÍT1 ASCILF RPT4 .48 ASCII DIGITLW TXDATA RPT5 INCF DIGIT2 DECFSZ ASCILF GOTO RPT5

SPARE PART (RULE 26) • ♦

MOVLW

MOVWF

MOVF call

RPT6 INCF

DECFSZ

GOTO

MOVF Call .48

ASCII

DIGJT2.W

TXDATA

DIGIT3

ASCII.F

RPT6

DIGIT3.W

TXDATA

MOVLW

CALL

20h

TXDATA

RETURN

ASC

MOVLW

MOVWF

KrTI INCF

DECFSZ

GOTO

MOVLW

MOVWF

MOVF call

RPT2 INCF

DECFSZ

GOTO

MOVLW

MOVWF

MOVF call

RPT3 INCF

DECFSZ

GOTO

MOVF cali

RETURN .48

ASCII

DIG1T1

ASCII, F

RPT1, 48

ASCII

DIGITI.W

SendChar

DIGIT2

ASCII.F

RPT2 .48

ASCII

DIGIT2.W

SendChar

DIG1T3

ASCII.F

RPT3

DIGIT3.W

SentíChar

ASC1

MOVWF

MOVF call

RETURN

CONVERT

CLRF

CLRF

CLRF

MOVWF

DIGÍT1

DIGITI.W

SendChar

DIGIT1

DIGIT2

DIGIT3

VALUE

REPLACEMENT PAGE (RULE 26) *, Ί * '* “' ¥ ^ν 'in *' ^- · '·' φ ·· * ·· ·

• * * 4 Ο

CALL Dl CALL D2 CALL RETURN D3 D1 movlw .100 subwf VALUE.W BTFSS STATUS, C RETLW 0 MOVWF VALUE .BALANCE IN VALUEA INCF DIGIT1.F GOTO D1 02 / movlw .11 subwf VALUE.W BTFSS RETLW 0 STATUS.C MOVWF VALUE .BALANCE IN VALUEA INCF DIGIT2.F GOTO 02 / D3 movlw .2 subwf VALUE.W BTFSS STATUS.C RENTLW 0 MOVWF VALUE , BALANCE IN VALUEA INCF DIG! T3, F GOTO D3 CLRLCD lipům SetupOelay lipům SendChar lipům SendCmd lipům SusyCheck return

LCOInit SLP lipům cND

SPARE PART (RULE 26) ·

· ♦ ·· * r vj 1! ^ u {uj * · · · · «· ·

T140798

TABLE 2 cunent project

ADD START PULSE TO DECRES TQ 48uS

INCREASE START PULSE TO 100uS

SET INPUT TO BE AT CENTER FRAME 100BAUD sheet p = 12C509, f = inhxQm

IOLOCS

CONFIG

JDLOCS

STATUS = 3

OSCCAL = 5; 12CS09

INDIR = 0

FSR = 4

PORTA = 6; PORT8 = 6; TRISA = 85h; TRISB «86h; OPTN = 81h

TMRO = 1

OOOOH

OOOEH, ΗΕΗ for int 4 meg axis ***** ·· **************

OOODH FOR EXT 4 MEG XTAL .001EH FOR MCLR ON EXT P1N 4 + INT OSC, -OOWH FOR MCLR ON EXT

WAS 5

VALI = OSh VAL0 = O9h

DIGITS-ICh DIGIT6 = 11h DIGIT7 = 12h DIGI1 = 1hh DIGIT13 = 1h DIGi13 = 15h DIGiT3 = 15h DIGIT1 = 17h DIGIT3 = 18h = 1Fb Gap = OFh TERRY2 = 0Eh VAL5 = 0Dh VAL2 = 0Ch TERRY = OBh VAL3 = 0Ah; code to send; delay / repeat

THE SPARE PART (RULE 26) i i * juuv (* vm ^ u

Β

ί.

; ORG 0 MOVWF OSCCAL start ORG 0 MOVWF OSCCAL , ‘SETUP PORT DDR MOVLW 3EH TRIS PORTA ; all INPUTS EXEPT FOR 10 BCF PORTA.O MOVLW WAXE OPT1ON OO4FH WAS OF 4F DEFALT IS SLOW WAS OOADH FOR NO UP ON P1N CHANGE

BTFSS GOTO BSF CALL BCF P0RTA.2 CHECK STATUS.5 SET UP STATUS FIXED SETUP loop • INCFSZ DÍGIT8.1 GOTO OOT INCFSZ DIG1T7.1 GOTO OOT INCFSZ DIGIT6.1 GOTO OOT INCFSZ DIGIT5,1 GOTO OOT COT NOP BTFSS TERRY.7 ; 1F 0 GOTO X GOTO OUTA MOVLW 14h MOVWF TERRY CUTA BTFSS TERRY, 6 GOTO OUTB MOVLW 14h MOVWF TERRY CUT3 BTFSS TERRY, 5 GOTO OUTC MOVLW 14h MOVWF TERRY OUTC BTFSC TERRY GOTO ALLOK BTFSC TERRY, 6 GOTO ALLOK BTFSC TERRY, 5

SPARE PART (RULE 26)

FTV UWJiLUU

ALLOK ·· TCl / JHUP / DOJZO

In 9 * 9 · 9

GOTO ALLOK BTFSC TERRY.4 GOTO ALLOK BTFSC TERRY.3 GOTO ALLOK MOVLW 14h MOVWF TERRY

_WAS HERE

STFSS PORTA, 2 GOTO CHECK

TO HERE

NEXT

CLRWDT BTFSS PORTA.2 GOTO NEXT CLRF PORTA

· 9 # * <* 4

PSD

BSF STATUS.5 CALL CSUM BCF STATUS.5

FIXED SETUP

....... ». _{CHECK SUM TOR DATA}

MOVLW .48 SUBWF DIGIT15.W MOVWF VAL1 BTFSC VAL1.0 GOTO TX1 BTFSC VALU GOTO TX1 BTFSC VAL 1,2 GOTO TX1 BTFSC VALU GOTO TX1 3TFSC VAL1,4 GOTO TX1 3TFSC VALÍ, 5 GOTO TX1 STFSC VALU GOTO TX1 BTFSC VALU GOTO TX1 GOTO TX2 MOVLW 20h MOVWF VAL5 movlw 20h

; was 20 AND 11

REPLACEMENT PAGE (RULE 26) · 4 · 444

movwf CALL VALÍ pulse4 MOVLW 20h MOVWF VAL5 MOVLW 20h MOVWF VAL1 CALL pulse4 movlw 20h movwf VAL1 call pulse4 MOVLW .04 MOVWF VAL5 movf DIGITI.O MOVWF VALÍ cafl pulse movf DIGIT2.0 movwf VALÍ cafl pulse movf DIGIT3,0 movwf VALÍ call pulse movf DIGIT4,0 movwf VAL1 call pulse movf DIGIT5.0 movwf VAL1 cail puise movf DIGIT6,0 movwf VAL1 call pulse movf DIGIT7.0 movwf VALÍ call pulse movf DIGITS.O movwf VAL1 call pulse movf DIGITS.O movwf VALÍ call puise movf DIG1T1O.0 movwf VAL1 call pulse movf DIGTTTLO movwf VAL1 call pulse

; was 04 TX ON TIME; DIGm

; + -1 on io change; inc on io cfaange; inc on tx 1; inc on tx 2; inc on tx 3

SPARE PART (RULE 26)

«« 4 *

4 4

14 «4

movf DIGIT12.0 movwf VAL1 call pulse movf OIGIT13.0 movwf VALÍ call pulse movf DIGITU.O movwf VAL1 caif pulse movf DIGITIS.O movwf VAL1 call pulse movfw .80 movwf VAL1 call pulse movf TERRY2,0 movwf VAL1 caO pulse eg nop nop nop nop nop nop nop nop nop call puíse5

-SLEEP MODE AFTER CODE

TX2 cifwdt

MOVF PORTA.O MOVWF VAÍ1 sleep nop MOVF VAL1.0 MOVWF PORTA clrwdt RETURN

NOP MOVWF VAL1 BTFSS VALÍ.7 IF 0 GOTO X GOTO OUTX

SPARE PART (RULE 26)

* * it • r ^ if AJtoWVVHV • this this this • it • it • · * it • it • • to * it ♦ · to * • • it and • to · • • · · · · "•it it·· • · «··

CLRF VAL1 INCF VALU BTFSS VALU GOTO 0UTX2 CLRF VAL1 INCF VALU OUTX2

RETURN; PROC FOR OUTPUT COOE t

pulse

BTFSS VAL1.0 CALL pulse3 BTFSC VAL1.0 call pulse2 BTFSS VALU CALL pulse3 BTFSC VALU call pulse2 BTFSS VALU CALL pulse3 BTFSC VALU cail putse2 BTFSS VALU CALL pube3 BTFSC VALU cafl pulse2 BTFSS VALÍ, 4 CALL pulse3 BTFSC VAL1.4 call pulse2 BTFSS VALU CALL pulse3 BTFSC VALU call pulse2 BTFSS VALÍ, 6 CALL pulse3 BTFSC VALÍ, 6 call pulse2 BTFSS VALU CALL pulseS BTFSC VALU call pulse6 CALL pulseS return clrwdt

alternate side (R 26)

Ktl / LMW / UUJťU TEST OF RANGE BUT STILL SHOULD BE BLGGER

«* ·«

THAN4 ffiiig

MOVLW .20 MOVF movwf fasf NOP NOP VAL5.W VALO PORTA.O NOP NOP decfsz goto BCF VAL0.1 ďiig PORTA.O

; on fo 3 6 9 12 ETC.

; NEW CHECK POWER; cyde 46 turn off, nop nop nop nop nop nop nop nop nop nop nop nop nop

RETURN putse2 clrwdt

MOVF wovwf osf NOP NOP VAL5, W VALO PORTA, 0 NOP NOP decfsz goto 3CF NOP NOP NOP VALO ,! digfih PORTA.O NOP NOP NOP

; on fo 3 6 9 12 ETC.

; ALSO NEW CHECK POWER icycle 46 turn off

SPARE PART (RULE 26) «· ·

4 · 4 4 • · ·: ηο »» »ο »ο

RETURN pulsež cbrwdt

MOVLW .10 -TEST OF RANGE MOVF VALS.W movwf VALO bsf PORTA.O ; on fo 3 6 9 12 ETC. decfsz VAL0.1 goto ifigg BCF PORTA.O cyde 46 tum off RETURN

pulse3 clrwdt

MOVF VALS.W movwf VALO bsf PORTA.O decfsz VAL0.1 goto digpp BCF nop nop nop nop nop nop RETURN PORTA.O

pulse4 clrwdt

MOVF VALS.W movwf VALO NOP NOP 12 CYCLES bsf PORTA.O

; on fo 3 6 9 12 ETC.

cycle 46 tum off

152 for he 46us

REPLACEMENT PAGE (RULE 26) CTU

WO 00/52636 * WO 00/52636

digph decfsz VAL0.1 goto dígph 3CF PORTA.O digf decfsz VALU goto digf NOP RETURN MOVEDTQ HERE CHECK COUNTER MODE MOVLW .48 SU8WF DIGmS.W MOVWF VAL1 BTFSC VALÍ, 7 GOTO TTl BTFSC VAL1,6 GOTO TT1 BTFSC VAL1,5 GOTO TTl BTFSC VALÍ, 4 GOTO TTl BTFSC VALU GOTO TTl BTFSC VAL1.2 GOTO TTl BTFSC VAL1.1 GOTO TTl BTFSC VAL1.0 GOTO TT3 GOTO TT2 TT2 BTFSC PORTA. 2 GOTO KX1 BTFSC SPARE.0 GOTO KK1 MOVLW Olh MOVWF SPÁRE INCF DIGIT3,1 INCF DIG1T4.1 KK1 BTFSS PORTA, 2 GOTO KK2 BTFSS SPARE.0 GOTO KK2 CLRF SPÁRE DECF DtGIT3,1 KK2 GOTO NEXT TT3 BTFSC PORTA.2 GOTO NEXT

: cyde 46 tum off; WAS PORTA. 1; BTFSC = BIT = O NEXT INSTRUCTION SK1PPED; WAS DIGJT4; WAS PORTA, 1

SPARE PART (RULE 26) «rv. i / wvwvittíu *:: * to ·>

it to it •

• this · it ··· it to this *

MOVLW MOVWF 1Fh TERRY MOVF VAL4.W SUBWF DIG1T4.W MOVWF VALÍ BTFSC VALU GOTO TT1 BTFSC VALÍ, 6 GOTO TT1 BTFSC VALU GOTO TT1 BTFSC VALÍ .4 GOTO TT1 BTFSC VAL1.3 GOTO m BTFSC VALÍ, 2 GOTO m BTFSC VALU GOTO m BTFSC VALU GOTO m

MOVLW 16h MOVWF TERRY CLRF VAL4

TT1: WSB

PM1

PM2

BTFSC ..... PROG GOTO PORTA.2 RAM MODE OFF ···· NEXT 10 IS NOW LOW SO SET UP DATA CLRF VALÍ BTFSS PORTA.2 GOTO WSB CLRWDT ; we must now wait 4500 us MOVLW Í20 WAS 10-25-23-45 MOVWF VAL3 MOVLW .23: 23 , -reusable values are val5 and v3 val3 MOVWF VAL2 CLRWDT DECFSZ VAL2.1 GOTO PM2 DECFSZ VAL3.1 GOTO PM1

BII

B12

MOVLW .46: 45 MOVLW VAL3 MOVLW .46 .Teusable values are rolling vai5 vaI3 MOVWF VAL2 CLRWDT DECFSZ VAL2.1

SPARE PART (RULE 26) • 44 44 · •

4

GOTO DECFSZ GOTO BTFSC BSF B12 VALU B11 PORTA.2 VAL1.0 BCF PORTA.O MOVLW .46 MOVWF VAL3 321 MOVLW .46 MOVWF VAL2 B22 CLRWDT DECFSZ VAL2.1 { GOTO B22 DECFSZ VAL3.1 GOTO B21 BTFSC PORTA, 2 BSF VALU and BSF PORTA.O MOVLW .46 MOVWF VAL3 B31 MOVLW .46 MOVWF VAL2 B32 CLRWDT DECFSZ VAL2.1 GOTO B32 DECFSZ VAL3.1 GOTO B31 BTFSC PORTA.2 BSF VALÍ .2 BCF PORTA.O

jreusabie values.are val va va 5 va) 2 val3 .feusable vabes are val va va 5 va! 2 vaJ3

MOVLW MOVWF .46 VAL3 B41 MOVLW .46 MOVWF VAL2 B42 CLRWDT DECFSZ VAL2.1 GOTO B42 DECFSZ VAL3.1 GOTO B41 BTFSC PORTA.2 8FS VALU BFS PORTA.O MOVLW .46 MOVWF VAL3 S51 MOVLW .46 MOVWF VAL2 B52 CLRWDT DECFSZ VAL2.1 GOTO B52 DECFSZ VAL3.1 GOTO 051 BTFSC PORTA.2

jreusable vabes are rolling in vaJS val2 vai3; reusable vabes are rolling in vaf5 val2 va (3

SPARE PART (RULE 26) «; «Ϊ́ • * * * *« ««

* · ♦ ·· · 4 ···

BSF VALÍ, 4 BCF PORTA, 0 MOVLW .46 MOVWF VAL3 B61 MOVLW .46 MOVWF VAL2 362 CLRWDT DECFSZ VAL2.1 GOTO B62 DECFSZ VAL3.1 GOTO B61 / BTFSC PORTA.2 BSF VAL 1.5 - BSF PORTA.O MOVLW .46 MOVWF VAL3 871 MOVLW .46 MOVWF VAL2 B72 CLRWDT DECFSZ VAL2.1 GOTO B72 DECFSZ VAL3.1 GOTO B71 BTFSC PORTA.2 BSF VALÍ .6 1 BCF PORTA.O MOVLW .46 MOVWF VAL3 B81 MOVLW .46 MOVWF VAL2 B82 CLRWDT DECFSZ VAL2.1 GOTO B82 DECFSZ VAL3.1 GOTO B81 BTFSC PORTA.2 BSF VAL 1.7 • BCF PORTA.O INCF TERRY.1 BTFSC TERRY, 4 GOTO SSM MOVLW 14h MOVWF TERRY SSM MOVF TERRY.O MOVWF FSR MOVF VAL 1.0 MOVWF INDIR INCF TERRY.1 CLRF DIGIT5 t CLRF DIGÍT6

^ eusabie vafues are rolling va! 5 va! 3 jreusabie vafues are rolling vaiS val2 va! 3, eusabte values are rolling va! 5 va! 2 va! 3

SPARE PART (RULE 26)

WO 00/52636

44 «4 • 4 · 4 * & CT / 33O <W22O • 4 4 · 4 · · · ··· 4 ·« ··

CLRF DIGtT7 CLRF DIGIT8 MOVF VAL1,0 MOVWF DIGIT4 MOVLW .48 SUBWF DIGIT5, W MOVWF VALÍ BTFSC VAL1.0 GOTO TX1 BTFSC VALU GOTO TX1 BTFSC VALÍ, 2 GOTO TX1 BTFSC VALÍ, 3 GOTO TX1 BTFSC VALÍ, 4 GOTO TX1 BTFSC VALU GOTO TX1 BTFSC VAL1,6 GOTO TX1 BTFSC VALÍ, 7 GOTO TX1 GOTO TX2

; TX1

GOTO NEXT END ORG 200H

SET_UP

MOVF MOVWF DIGIT2,0 VAL5 : 3,4,5 GOTO 0UT3 NO PRIOR SETUP MODE BTFSC VAL5.7 GOTO OUT3 BTFSC VAL5.6 GOTO 0UT3 BTFSS VAL5.5 GOTO OUT3 BTFSS VAL5,4 GOTO OUT3 BTFSC VAL5,3 GOTO OUT1C BTFSC VAL5,2 GOTO OUT1C BTFSC VAL5,1

•••• REMOVE »

SUBSTITUTE SHEET (RULE 26) »

WO 00/52636 4 "4"

PCT / IBO / 00220

GOTO OUT1C

BTFSC VAL5.0

GOTO OUT1C

MOVLW 004FH; was Q04FH for no pull ups

OPTION

GOTO 0UT4

OUT1C

BTFSC VAL5,3

GOTO OUT1B

BTFSC VAL5.2

GOTO OUT1B

BTFSC VAL5.1

GOTO OUT1B

BTFSS VAL5,0

GOTO OUT1B

MOVLW 004EH;

OPTION

GOTO 0UT4

OUT1B

BTFSC VAL5.3

GOTO OUT1A

BTFSC VAL5,2

GOTO OUT1A

BTFSS VAL5.1

GOTO OUT1A

BTFSC VAL5,0

GOTO OUT1A

MOVLW 004DH;

OPTION

GOTO 0UT4

0LFT1A

BTFSC VAL5,3

GOTO OUT1

BTFSC VAL5.2

GOTO OUT1

BTFSS VAL5,1

GOTO OUT1

BTFSS VALS, 0

GOTO OUT1

MOVLW 004CH; 16

OPTION

GOTO OUT4

OUT1

BTFSC VAL5,3 GOTO OUT2 BTFSS VAL5.2 GOTO OUT2 BTFSC VAL5.1 GOTO OUT2 BTFSC VAL5.0 GOTO OUT2

*, r ~ K · • · · · · · · · ·

WO 00/52636 & PCT / IB0 / 00220 MOVLW OO4BH; 16 OPTION GOTO OOT 4 OUT2 BTFSC VAL5.3 GOTO OUT3 BTFSS VAL5.2 GOTO OUT 3 BTFSC VAL5.1 GOTO OUT 3 BTFSS VALS.O GOTO OOT3 MOVLW 004AH; 32 OPTION GOTO OUT4

OUT3 BTFSC VAL5.3 GOTO OUT5 BTFSS VAL5.2 GOTO OUT5 BTFSS VAL5,1 GOTO OUT5 BTFSC VAL5.0 GOTO OOT5 MOVLW 0049H WAS 0049H OPTION GOTO 0UT4

OUT5 * RESET TAG MOVLW OPTION MOVLW 004DH; OE 2SEC OB = 13FAST OOODH FOR 1 PER SEC AND OOOFH FOR SLOW .50 ; WAS 50 OA 2SEC FROM = 13FAST OBH FOR 1 PER SEC AND 09H FOR SLOW MOVWF DIGIT2 ; SPEED MOVLW , 50 MOVWF D1GIT3 ; SWITCH MOVLW .00 MOVWF DIGIT4 ; COUNTER MOVLW .00 MOVWF DIGIT5 ; AGE MOVLW .00 MOVWF DIGIT6 MOVLW .00 MOVWF DIGIT7 MOVLW .00 MOVWF DIGIT8 MOVLW .48 MOVWF DIGIT1 DATA 1 MOVLW .48 MOVWF DIGIT9 data 2 MOVLW .48 MOVWF DIGIT10 MOVLW .48 MOVWF DIGIT11

 ·· β

WO 00/52636 &quot; &quot;, &quot; &quot;

PCT / IBOO / 00220

MOVLW .48 MOVWF DIGIT12 MOVLW .48 MOVWF D1GIT13 MOVLW .48 MOVWF DIGIT14 MOVLW .65 MOVWF DIGIT15 MOVLW .80 MOVWF DIGIT16 MOVLW 14h MOVWF TERRY

OUT4

INCFSZ DIGIT8.1 GOTO OOTA

INCFSZ DIGIT7.1 GOTO OOTA

INCFSZ DIGIT6.1 GOTO OOTA

INCFSZ DIGIT5.1 GOTO OOTA

OOTA

RETURN

CSUM

MOVF DIGITI.O ADDWF DIGIT2,0 ADDWF DIGrT3.0 ADDWF DIGIT4,0 ADDWF DIGITS.O ADDWF DIG1T6.0 ADDWF DIG1T7.0 ADDWF DIGIT8,0 ADDWF DIGITS.O ADDWF DIG IT 10.0 ADDWF DIG 1711.0 ADDWF DIGIT12.0 ADDWF DIGIT13.0 ADDWF DiGrri4, Fr ADDWF DIGITIS.O MOVWF TERRY2

RETURN

Claims (28)

PATENT CLAIMS 1. An electronic tag comprising processor means programmed to provide a modulation control signal comprising specific identification data that at least identifies the tag and transmitter circuits connected to the processor means and an antenna for transmitting said specific identification data, which transmitter circuits are powered by the modulation control signal. The electronic tag according to claim 1, wherein the transmitter circuits are exclusively powered by the modulation control signal from the processor means. The electronic tag of claim 1 or claim 2, wherein the transmitter circuitry comprises passive components and a transistor forming oscillator circuits directly controlled by processor means, the transistor in combination with the passive components being an integral part of the transmitter circuitry that is powered by the modulation control signal. An electronic tag according to any of the preceding claims, wherein the processor means is arranged to provide a modulation control signal having a first portion followed by a second portion, a first portion comprising at least one large pulse of a length such as to supply sufficient power to the transmitter circuits partially at least for transmitting a second portion that includes data defined by a plurality of substantially shorter pulses. The electronic tag according to claim 4, wherein the first portion of the modulation control signal comprises a plurality of large pulses which, in combination, provide the receiver in the electronic tag with an identification signal for receiving a transmission from the electronic tag. The electronic tag of claim 4 or claim 5, wherein each pulse of the second portion of the modulation signal has a start portion for detecting the start of a bit and a data portion for determining the state of the data bit. • to • to • it • · it • ·· • « ·· it • • > · • « • · • • • • • • it to · · ··· • it • it The electronic tag of claim 6, wherein the high bit state is defined by the shorter data period during which the oscillator circuits are off, and the low bit state is defined by the longer data period during which the oscillator circuits are off. The electronic tag according to any of the preceding claims, wherein the processor means is represented by a microprocessor having an internal RC oscillator from which the modulation control signal is derived, and the microprocessor is adapted to insert a sleep mode between data transmissions and thereby reduce power consumption. 9 9 9 · · · 4 · 9 ·· ·· · * · 9 9 * 9 99 9 9 9 9 9 9 9 9 An identification system comprising a plurality of electronic tags, each tag comprising processor means programmed to provide a modulation control signal that includes specific identification data that at least identifies the tag; and transmitter circuits connected to processor means and an antenna for transmitting said specific identification data, the transmitter circuits being substantially powered by the modulation control signal; and at least one receiver arranged to receive a broadcast from said label. The identification system of claim 9, wherein the transmitter circuitry is powered exclusively by the modulation control signal from the processor means. The identification system of claim 9, wherein the transmitter circuitry comprises passive components and a transistor directly controlled by processor means, the transistor in combination with the passive components being an integral part of the transmitter circuits that are powered by the modulation control signal. An identification system according to any one of the preceding claims 9 to 11 inclusive, wherein the processor means is arranged to provide a modulation control signal having a first portion followed by a second portion, a first portion comprising at least one large pulse of sufficient length to supply sufficient power to the transmitter circuits in part. at least to stabilize them for transmitting a second portion that includes data defined by a plurality of substantially shorter pulses. The identification system of claim 12, wherein the first portion of the modulation control signal comprises a plurality of large pulses which, in combination, provide the receiver in the electronic tag with an identification signal for receiving a transmission from the electronic tag. An identification system according to claim 12 or claim 13, wherein each pulse of the expensive portion of the modulation signal has a start section for determining the start of the bit and a data section for determining the state of the data bit. An identification system according to claim 14, wherein the high bit state is defined by the shorter data period during which the oscillator circuit is off and the low bit state is defined by the longer data period during which the oscillator circuit is off A method of transmitting data from an electronic tag, the method comprising driving the circuit of the tag transmitter with a modulation control signal that substantially powers the circuit of the transmitter. The method of claim 16, wherein the modulation control signal powers the transmitter circuits exclusively. The method of claim 16 or claim 17, which comprises selectively modulating the base frequency of the oscillator when data is transmitted and disabling the oscillator when no data is transmitted. A method according to any one of the preceding claims 16 to 18 inclusive, wherein the modulation control signal has a first portion followed by a second portion, a first portion comprising at least one large pulse of a length such as to provide sufficient energy to power the circuits. The transmitter partly at least to stabilize it for transmitting a second portion containing data defined by a plurality of pulses substantially shorter. The method of claim 19, wherein the first portion of the modulation control signal comprises a plurality of large pulses that, in combination, provide the receiver in the electronic tag with an identification signal for receiving broadcasts from the electronic tag. The method of claim 19 or claim 20, wherein each pulse of the second portion of the modulation signal has a start section for detecting the start of a bit and a data section for determining the state of the data bit, the data section length under processor control selectively defining high and low state. The method of claim 21, wherein the high bit state is defined by the shorter data period during which the oscillator circuit is off and the low bit state is defined by the longer data period during which the oscillator circuit is off The method of any one of the preceding claims 16 to 22 inclusive, wherein the processor means is represented by a microprocessor having an internal RC oscillator from which the modulation control signal is derived and the microprocessor adapted to insert a sleep mode between data transmissions and thereby reduce power consumption. 24. A receiver for receiving a transmission from one of a plurality of electronic tags, the transmission comprising a first portion and a second portion, and a receiver comprising detection circuits for detecting the first portion and a second portion of the broadcast, the first portion comprising at least one large pulse; a second portion that contains data defined by a plurality of substantially shorter pulses; and timing means for measuring the length of each of these pulses in the second portion and for selectively generating a high or low level output defining a pulse-length dependent bit. 25. A new electronic tag, essentially as described and illustrated herein. 26. A new system, essentially as described and demonstrated herein. 27 Mar: A new method of reducing power consumption in an electronic tag, essentially as described and demonstrated herein. 28. A new receiver, essentially as described and demonstrated herein. WO 00/52636 1/5 «··· ··· ··· ·· * ·· PCT / IBOO / 00220 in 29— 28