CS269514B1

CS269514B1 - Time-compensated pulse formatter for integrated circuit testers

Info

Publication number: CS269514B1
Application number: CS872775A
Authority: CS
Inventors: Lubomir Ing Burian; Jozef Ing Csc Chamraz; Bedrich Ing Csc Sindelar
Original assignee: Lubomir Ing Burian; Jozef Ing Csc Chamraz; Sindelar Bedrich
Priority date: 1987-04-21
Filing date: 1987-04-21
Publication date: 1990-04-11
Also published as: CS277587A1

Abstract

Jedná se o zapojenie formátovača impulzov, ktoré umožňuje optimálnu realizáciu štrnástich rozličných módov formátovania údajov s časovou kompenzáciou z generátore testovacej postupnosti vedených cez pinelektroniku na meraný integrovaný obvod. Podstata řešení spočivá ve vhodnom přepojení prijimačov údajov prijimačov časovacich fáz, prijimačov riadenia, príjimača invertu, formátovača s časovou kompenzáciou, obvodov stálých logických úrovni, multiplexera s časovou kompenzáciou a budiča s invertorom. Formátovacie módy sú realizované zo vstupu údajov a vstupu časovačích fáz vo formátovači s časovou kompenzáciou a vedené z výstupov formátovača a obvodov stálých logických úrovni na údajové vstupy multiplexera s časovou kompenzáciou. Na výstup multiplexera je vyselektovaný jeden z Osmých základných módov formátovania podlá kombinácie riadiacich signálov na vstupe multiplexera. Údaje z výstupu vedú na vstup budiča s invertorom a možu prechádzaf na výstup bud v priamej formě alebo v invertovanej formě pódia stavu vstupu budiča s invertorom.This is the connection of the pulse formatter, which enables the optimal implementation of fourteen different data formatting modes with time compensation from the test sequence generator, which are routed through the pin electronics to the measured integrated circuit. The essence of the solution lies in the appropriate connection of data receivers, timing phase receivers, control receivers, an invert receiver, a formatter with time compensation, constant logic level circuits, a multiplexer with time compensation and a driver with an inverter. The formatting modes are realized from the data input and the input of the timer phases in the time-compensated formatter and led from the outputs of the formatter and constant logic level circuits to the data inputs of the time-compensated multiplexer. One of the Eight basic formatting modes is selected for the output of the multiplexer according to the combination of control signals at the input of the multiplexer. The data from the output leads to the input of the driver with inverter and can be passed to the output either in direct form or in the inverted form of the state stage of the driver input with inverter.

Description

CS 269514 B1 1CS 269514 B1 1

Vynález se týká zapojenia formátovača impulzov s časovou kompenzáciou pře testeryintegrovaných obvodov, ktorá umožňuje jednoduchá a technickými parametrami výhodnárealizáciu štrnástich rozličných formátovacích módov s kompenzáciou .zmien oneskoreniapri zmene módu pre ádaje z generátora testovacej postupnosti prechádzajáce cez pinele-ktroniku na testovaný integrovaný obvod.BACKGROUND OF THE INVENTION The present invention relates to a pulse formatter incorporating time-compensated transistor integrated circuits, which allows for simple and technical advantageous implementation of fourteen different formatting modes with delay compensation over mode change for requesting from a test sequence generator passing through the pinel to the tested integrated circuit.

Doteraz známe riešenia podobných formátovačov impulzov bud využívali štandartnéobvodové celky a integrované obvody, čo vedle k neásporným ríešeniam s menším technic-kým a ekonomickým áčinkom, alebo nemajá dostatočný počet rozličných formátovacích módov,ktorý umožňuje efektivnejšie využivanie technických aj programových prostriedkov testeraV uvedených riešeniach taktiež nebol komplexně riešený problém časovej kalibrácíe každé-ho kanálu.So far known solutions of similar pulse formatters have used standard circuitry and integrated circuits, which in addition to unsafe solutions with less technical and economical pickups, or does not have a sufficient number of different formatting modes that allows more efficient use of technical and program resources. solved the problem of time calibration of each channel.

Uvedené nevýhody odstraňuje zapojenie formátovača impulzov s časovou kompenzácioupre testery integrovaných obvodoch Vl$podla vynálezu vhodného na realizáciu pomocou hradlových poli ECL, podstata ktorého spočívá v tom, že na vstup prijimačov ádajov je připo-jený výstup obvodov postupného spracovania ádajov generátora testovacej postupnosti.The above drawbacks are eliminated by the inclusion of a time-compensated pulse formatter of the V1a integrated circuit testers according to the invention suitable for ECL gate arrays, the output of the request sequence generator circuitry being connected to the receiver request input.

Na vstup prijimačov časových fáz je připojený výstup programovatelného přepínačefáz časovacieho generátora, na vstup prijimačov riadenia je připojený výstup MODE-re-gistra bloku riadenia pinelektroniky a na vstup prijimača invertu je připojený výstupINVERT-registra bloku riadenia pinelektroniky. Výstupy prijimača ádajov vedie na prvývstup formátovača s časovou kompenzáciou, výstup prijimačov časovačích fáz je přivedenýna druhý vstup formátovača s časovou kompenzáciou. Výstupy formátovača sá připojené naúdajové vstupy multiplexera s časovou kompenzáciou a taktiež výstupy obvodov trvalýchlogických úrovni sá přivedené na údajové vstupy multiplexera.· Výstup prijimačov riadeniaje připojený na riadiaci vstup multiplexera s časovou kompenzáciou. Údajový výstup mui-tiplexera vedie na vstup budiča s invertorom. Výstup prijimača inv,ertu je připojený nariadiaci vstup budiča s invertorom. Výstup budiča s inve torom je vedený na programova-telnú oneskorovaciu linku časovej kalibrácíe. Přednostou zapojenia formátovača impulzov s časovou kompenzáciou podlá vynálezu je,že v zapojení sá použité optimalizované funkčně obvodové celky, čim sa dosahuje minima-lizácia obvodových prostriedkov a zjednodušeníe aplikácie najm3 v případe, že celý obvo-dový systém formátovača impulzov je realizovaný v jednom integrovanou) obvode na bázehradlových poli. Oalšou přednostou zapojenia je použitie rýchlej ECL-technológie v danomhradlovom polí, čim sn zmenšuje oneskorenie signálu pri přechode obvodovým systémom aminimalizujů sa rozdieiy v oneskorenl jednotlivých módov činnosti formátovača impulzov.The output of the time phase receivers is connected to the output of the programmable switch of the timer generator phase, the output of the control receivers is connected to the output of the MODE-re-gister of the pinelectronics control block and the input of the invert receiver is connected to the output of the INVERT-register of the pinelectronics control block. The receiver request outputs lead to a time-compensated first formatter, the output of the timing receivers is inputted to the second time-compensated formatter. The outputs of the formatter are connected to the data inputs of the time-compensated multiplexer as well as the outputs of the perpetual logic levels applied to the data inputs of the multiplexer. The data output of the mu-tiplexer leads to the input of the inverter driver. The receiver input inv, ert is connected to the inverter driver input with the inverter. The driver exciter output is routed to a programmable time calibration delay line. A preferred embodiment of the time-compensated pulse formatter according to the invention is that optimized functional circuitry is used in the circuitry, thereby minimizing circuitry and simplifying the application in the event that the entire circuit of the pulse formatter is implemented in one integrated mode. perimeter on base-track fields. Another advantage of the circuit is the use of fast ECL technology in a field array, thereby reducing the signal delay when passing through a circuitry system to minimize the difference in the delay of each mode of the pulse formatter.

Použitie obvodového systému podlá vynálezu vo formě jedného integrovaného obvoduna báze hradlových poli prináša efekt zlepšenia technických vlastnosti výsledného pro-duktu a ekonomický efekt vyplývajáci zo zniženia výrobných nákladov.The use of a circuit system according to the invention in the form of a single integrated gate field base provides the effect of improving the technical properties of the resulting product and the economic effect resulting from the reduction of production costs.

Zapojenie formátovača impulzov s časovou kompenzacicupre testery integrovaných ob-vodov podlá vynálezu je zobrazené na priloženom výkrese. V konkrétnom pripade je formátovač impulzov s časovou kompenzáciou realizovaný tak,že na vstup 11 prijimačov ádajov 2. je připojený výstup obvodov postupného .spracovaniaádajov generátora testovacej postupnosti, na vstup 21 prijimačov časovačích fáz 2 jepřivedený výstup programovatelného prepínača fáz časovacieho generátora, na vstup 32prijimačov riadenia 3 vedie výstup MODE-registra bloku riadenia pinelektroniky a tak-tiež na vstup 41 prijimača invertu 2 vedie výstup INVERT - registra bloku riadenia pi-nelektroniky, pričom výstup 12 prijimačov ádajov 2 je připojený na prvý vstup 51 formá-tovača s časovou kompenzáciou a výstup 22 prijimačov časovačích fáz 2 na druhý vstup52 formátovača s časovou kompenzáciou 5, výstup 53 formátovača 2 je připojený na prvýúdajový vstup 71 multiplexera s časovou kompenzáciou výstup 54 na druhý údajovývstup 72» výstup 55 na treti údajový vstup 73, výstup 56 na štvrtý údajový vstup 74,A time-compensated pulse formatter for integrated circuit testers according to the invention is shown in the attached drawing. In a particular case, the time-compensated pulse formatter is implemented by outputting the sequence of the test sequence generator circuits to the input 11 of the request receivers 2, the output of the programmable switch of the timing generator phase is applied to the input 21 of the timing phase receivers 2, to the input 32 of the control receivers 3, the output of the MODE-register of the pinelectronics control block leads to the input 41 of the invert receiver 2 and the output of the INVERT-register of the electronics control block, the output 12 of the receivers 2 is connected to the first input 51 of the time compensator and the output 22 of the timing receivers 2 to the second input 52 of the formatter with time compensation 5, the output 53 of the formatter 2 is connected to the first data input 71 of the multiplexer with time compensation output 54 to the second data input 72 »output 55 on the third data input 73, output 56 to the fourth data vs tup 74,

Claims

CS 269514 B1 output 57 to fifth data input 75 and output 58 to Siesty data input 76, wherein the seventh data input 77 of the time compensation multiplexer 77 is connected to the first output61 of the permanent logic level circuits 6 and to the eighth data input 78 to the second output 62, except in addition, the control input 79 of the multiplexer 7 with the time compensation 7 has a control output 3 output 33 and the output 710 of the multiplexer 7 is connected to the input 81 of the driver 8, the input 42 of the invert receiver 4 is applied to the control input 82 of the driver 8 and its output 83 leads to a programmable delay line input. The data receivers 1 generate pulses routed through the data processing circuitry of the test sequence generator to the input 11, and these are further fed from the output 12, the input 51 of the formatter with time compensation 5,. The timing phase receivers 2 again receive and generate timing phase pulses that are routed through a programmable phase generator phase switch to input 21.

2 of the output 22 the timing phase pulses go to the second format 52 of the formatter with time compensation 5. The output of the MODE register is inputted from the output 32 to the control input 79 of the time compensation multiplexer 7 after the control transducers 3 and determines the selection of one of the eight basic modes of multiplexing output 710 7, the formatter with time compensation>> based on sequential combination circuits realizes and outputs the following modes of formatting Ia / “without return to zero (NON RETURN TO ZERO) using the Tpf phase which is output from the formatter output 53 to the input 71 of the multiplexer 7 ^, b / "without returning to zero (NRZ) using the TGX phase" which is output from the output 54 input 72, c / "returning to zero (RETURN TO ZERO - RZ) using phase TGX, which is output 55 to input 73, d / "returning to zero (R2) for inverted TGX data" output 56 to input 74, e / "EXCLUSIVE OR - XOR" using the TGX phase, which is routed from output 57 to input 75, f / "multiplexing two data ('MULTIPLEX - RETURN TO ZERO - MUX - RZ) using two phases TGX and TGY, which is output from formatter output 58 to time compensator 5 on input 75 of multiplexer 7. The last two basic modes are PERMANENT LOGIC ZERO (PLO), which is routed to the input 77 of the time-compensated multiplexer7 and the so-called "persistent unit" (permanent logic level 6). PERMANENT LOGIC ONE - PLO, output from output 62 to input 78multiplexer 7, time compensation output 710 of the multiplexer 7 is connected to input 81 of the inverter driver which transmits formatted data via output 83 to the input of the correction line and further to the pinelectronics bud in direct form (8 basic modes) or data I will be inverted to create another 8 derived formatting modes: "NON RETURN TO ONE" with TG O or TGX "," with return to unit (RETURN TO ZERO - RG) with TGX, or TGX inverted data "," logical match (LOGIC COINCIDENCE - LOC) with TGX "," inverted multiplexing of two data (INVERT MUX - RZ) with TGX and TGY " and duplicate PLO and PLZ modes. The invention finds application in VLSI integrated circuit testers with a large number of test channels. SUBSTITUTE A time-compensated pulse formatter for integrated circuit testers, characterized in that the test sequence generator sequential processing data circuits are connected to the data receiver input (1), to a timing phase receiver (2) the CS 269514 B1 3 Vacuum Generator Programmable Phase Switch output is connected to the control receiver input (31)

(3) The output of MODE; -register of the pinelectronics control block and also the input (41, of the receiver of the invert (4) the output of the INVERT - register of the control block of the pinelectronics, the output (12) of the receiver (1) is connected to the first winding (51). of the formatter 3 by time compensation (5) and by the output (22) of the timing phase receivers (2) to the second input (52) of the time compensator (5), the output (53) of the formatter (5) is connected to the first data input (71) , time-compensated mul-buffer (7), output (54) to second data input (72), output (55) to third data input (73), output (55) to fourth data input (74), output (57) ) to a fifth data input (75) and an output (58) to a sixth data input (76), wherein a first output (51) of the logic level circuitry (5) is connected to the seven-time multiplexer data input (77) and to the eighth data input (7Θ) the second output (62), in addition to the tuning input (7) 9) the time compensation multiplexer (7) leads the control receiver output (33) (3) and the multiplexer output (710) (7) is connected to the inverter driver input (81), the invert receiver output (4) ) is connected to the inverter control input (82) of the inverter (8) and its output (83) to the programmable delay line input. 1 drawing