CS255857B2 - Device for inlet treatment of biological signals - Google Patents

Description

(54) Biological signal input processing apparatus

The present invention relates to a biological signal input processing apparatus consisting of measuring modules connected to a module bus. The device is equipped with galvanic isolation according to safety regulations. Biological signals come from the sensor after appropriate shaping in the input processing unit to the analogue-to-digital converter. The digitized signal is routed along with the status information of the measurement module together via the galvanic isolation unit to the module bus, which provides this information to the computer if the digital command words entered by the computers that also arrive via the galvanic isolation unit to the measurement module module.

BACKGROUND OF THE INVENTION The present invention relates to a biological signal input processing apparatus, in particular for a multi-channel medical microcomputer provided with measuring systems, which is galvanically isolated and provided with measuring modules composed of standard components and connected to sensors and a standard contact circuit.

A known device of this kind consists of input modules for biological signals - measuring units - and a modular bus. Input processing modules contain besides the signal conditioning part also special technical equipment - part for digital input processing. This special hardware is suitable for organizing module collaboration in a simple way and for processing information related to operations performed on a biological signal, signal conditioning such as blocking, calibrating, gain gain, zero level shift, and other module states. The device is further equipped with a standard interface and the usual protective device for galvanic separation of the patient.

Prior art solutions use, as far as the input processing of biological signals is concerned, the transmission of the carrier frequency of the analog signal through the galvanic isolation site to the processing side.

In the known solution, the measured analog signal is transmitted by means of frequency or pulse modulation of the waves through a galvanic separator. This solution does not allow simple organization of cooperation of measuring units measuring biological signals. The transmission of information associated with biological signals is limited due to the use of a reed relay. In addition, there are various distortions and interceptions in the measured analog signal, depending on the type of modulation.

To eliminate these phenomena, a solution is used in which the signal transmission is carried out by means of a two-way galvanic separation. This greatly reduces channel distortion. However, the organization of the cooperation of the measuring units and the processing of the information associated with the states of the measuring units is not ensured even with this solution.

These disadvantages are eliminated in the biological signal input processing apparatus according to the invention, the principle being that the measuring modules are connected via a galvanic isolation unit via an input contact circuit to a module bus adapted for individual measuring modules having a standard output contact circuit, a signal conditioning unit measuring modules, equipped with controllable analog switches and amplifiers, is connected via a digital input processing unit to the galvanic isolation unit, the input processing unit is connected to the input isolator and output separator of the galvanic isolation unit and to the power supply unit input of control circuit, on the one hand with input of serial-parallel converter, whose output is connected with first memory unit and with trigger the output of the address identification unit is connected to the input of the control circuit, the outputs of the first memory unit are connected to the control inputs of the signal conditioning unit, the output of the signal conditioning unit is connected to an analog to digital converter, whose parallel outputs are connected via a data control selector, parallel - serial converter and admission circuit to the output separator, the first and second outputs for the control circuit write are connected to the first memory unit, the analog-to-digital control output of the control circuit is connected with analog-to-digital converter, control circuit data state switching output is connected to data control selector, control output parallel - control circuit serial conversion is connected with a parallel-serial converter, and the control circuit admitting output is coupled to the admitting circuit, wherein the inputs of receiving the status information of the data control selector are connected to the control bodies. ¹

The device according to the invention is advantageously applicable where it is necessary to measure and process several biological parameters simultaneously.

Such an area of application of the device is, for example, intensive patient care. The device is applicable to multi-purpose medical measuring systems equipped with a microcomputer and has a modular design.

An exemplary embodiment of a biological signal input processing apparatus according to the invention is shown in the drawings, in which Fig. 1 shows a block diagram of the device; Fig. 2 shows the arrangement of its measuring module;

FIG. 5 shows a timing diagram of the operation of the apparatus control circuit.

As can be seen from FIG. 1, the device is provided with measuring modules 6 connected via sensors 6 to the patient 6 and via a galvanic isolation unit 28 via an interface 6 to the module bus 6 common to all measurement modules 6. The module bus 6 is provided with a standard contact circuit 7 and has power units and circuits for adapting the individual measuring modules 6 to the contact circuit 6. The measuring module 6 is provided with an analog signal conditioning unit 3 and a digital input processing unit 6, which performs analog-to-digital conversion which are connected together. The galvanic isolation unit 28 is connected to the input processing unit 6 and the sensor 6 is connected to the signal conditioning unit 6.

The apparatus shown in FIG. 1 operates as follows:

The signal obtained by the sensor 2 from the patient 6 with the signal conditioning unit 6 is amplified as a function of the signals applied to its input, its DC voltage level is shifted thereto and optionally a calibration signal is generated or the signal conditioning unit 6 is blocked. All these operations are carried out using analog switches and operational amplifiers. The signals coming from the signal conditioning unit 6 are converted into digital signals by the input processing unit 6 and transmitted in the case of a query coming from the interface 6.

These signals are obtained by the interaction of the module bus 6 on the contact circuit 6 to which any known computer can be connected. This computer activates the query by indicating the address of the requested measuring module 6 and the operations to be performed by the signal conditioning unit. Different addresses are assigned to the individual measuring modules.

The apparatus formed in the manner described above can advantageously be arranged as shown in FIG. 2. According to this arrangement, the module bus 6 can be housed in the housing 8, whereas the individual measuring modules 8 can be provided as separate housings 12 with a faceplate 13 and guided on their the edges 11 by means of rails 10 to a location formed in the cover 8 and can be releasably connected therein by attaching to a retaining element 54 fixed to the cover 9 by means of a fastening element 52 operated through the front plate 63. The connections of the sensors 8 may be formed by a double socket connection arranged on the faceplate 13, the interface 6 being located on the backplate of the housing 12.

In FIG. 3, the measuring module 6 and the connection and interface 6 are shown in more detail. The control inputs of the signal conditioning unit 6 passing through the sensor 6 in connection with the patient 6 are connected to the first memory unit 17, while the output of the signal conditioning unit 6 is connected to an analog-to-digital converter 64 whose parallel outputs are connected via a selector 18 of the control. data converter, parallel-serial converter 19 and admission circuit 24 with output separator 25.

The output separator 25 together with the input separator 26 and the power supply unit 27 form part of the galvanic separation unit 28 connected to the interface 6. The input separator 26 and the output separator 25 are each a splitter coupler, while the power supply unit 27 is provided with a clock pulse transformer so that a portion of the power supply unit 27 forms a clock pulse generator 27 'that is connected to the clock pulse CK. The input separators 26 are connected to the control input C of the control circuit 21 and to the serial-parallel converter 20, the output of which is connected to the first memory unit 22 » ^{to the} trigger output V of the control circuit 21 and to the address identification unit 23. The first write command output E and the second write command output F of the control circuit 21 are connected to the first memory unit 17, while the analog-to-digital conversion control output 21 of the control circuit 21 is connected to the analog-to-digital converter 16. admitting input and output signal.

The data state switching output control circuit 21 is coupled to a data control selector 18, while the parallel-serial conversion control output 21 of the control circuit 21 is connected to a parallel-serial converter 19. The admission output G of the control circuit 21 is coupled to the admission circuit 24 . The inputs for receiving the status information of the selector 18 of the data control member are coupled to the control members 22. In this embodiment, an analog-to-digital converter of the progressive approximation type 16 is provided which has outputs switchable to a high impedance state.

Therefore, the data control selector 18 can be formed in a simple manner by connecting the outputs to the control elements through a resistive network. Thus, the logical state of the outputs determines the analog-to-digital converter 16, in the high-impedance state, on the other hand, the position of the control elements 22. An 8-channel selector containing simultaneously the admission circuit 2.4 was used as a parallel-serial converter 19. The address identification unit 23 is formed by a digital comparator to which a circuit reproducing the actual address of the measuring module 81 or an internal control element is connected. The clock pulse CK coupled to the clock pulse generator 27 'is also coupled to the series-parallel converter 20 and the control circuit 21.

FIG. 4 shows an embodiment of the control circuit 21 in more detail in the event that a computer connected to the interface circuit 7 supplies a serial 8-bit serial syllable inserted between the start bit and the stop bit on the module bus 6. The first four bits of the first syllable are not the address information of the called metering module, while the remaining four bits contain the command passed to the signal conditioning unit 2 of the metering module 8. The control circuit 8 consists of a decimal ICI decoder encoded in binary-decimal code. double flip-flop IC3, first and second IC4 / 1, IC4 / 2 disjunction with four inputs, first, second and third inverters 1С5 / 1, 1С5 / 2, 1С5 / 3, first and second 1С6 / 1 , 1С6 / 2 logic product with two inputs, from the first and second differentiation circuits diff1, diff2 and from the delay element α _t .

In the control circuit 21, the first input of the clock pulses of the double counter IC2 and the first input of the second logic product IC6 / 2 are connected to the clock CK line. On a second input circuit IC6 / 2 ANDing via a second differentiator circuit diff2 comprising a capacitor connected in series in the signal path and the ground resistor connected к, connects the second output Q ₂ of the double flip-flop IC3. The analog-to-digital control output H of the control circuit 21 is coupled to the second logic product IC6 / 2.

The first input of the double flip-flop IC3, which is identical to the trigger input V of the control circuit 21, is outputted by the highest-order bit of the serial-parallel converter 20. The first output of the double flip-flop IC3 is connected to the first and second reset inputs R ^, R. _{2 of the} double counter IC2. The first, second, third, fourth output Q, P ₂ 2j * -13 * -14 twin counter IC2 are connected with each nstupy decimal decoder ICI, i.e. the first, second, third and fourth inputs a, b, c, d. _x

The fourth output Q ₁₄ of the double counter IC2 is also coupled to the second input E ₂ of the double clock pulse counter IC2. The fifth output of the double counter 1 (^ 2 is coupled to the first input of the first logic IC6 / 1 circuit, while the sixth output _{22 of the} double counter IC2 is coupled via a delay element a _t which consists of a resistor connected in series with a capacitor connected to ground with the second input of the first circuit 1С6 / 1 logic product.

Output of first IC6 / 1 logic product and first and second clearing input Cp C? the double flip-flop IC3 are connected together. First to third output druhý.a ц Q, ^ ₁₂ 'Q ₁₃ double counter IC2 forms a first portion of the output control Paral linseed-serial converter 19, while the second part of A *, the controller also parallel-to-serial converter 19, that is, more precisely in other words, used to create start and stop bits, is formed by the first and second outputs of the decoder IC1. .

The output of the first disjunction negation IC4 / 1 circuit is formed by the first for sending a write command through the output E of the control circuit 21 and the output of the second disjunction negation negation IC4 / 2 is formed by the second output F for sending the write circuit of the control circuit 21. are connected via the first inverter IC5 / 1 and the first differential circuit dif.fl, which consists of a series capacitor in the signal path and a resistor connected to the power supply, to the second output Q9 of the decoder IC1, to the output of the input separator 26 23 address identification via the second inverter IC3 / 2 and with the fifth output Q _{21 of the} double counter IC2.

The inputs of the second disjunction negation IC4 / 2 circuit are also coupled to the output of the input separator 26, the fifth output of the double counter IC2 via the third inverter IC 5/3, the second output Q9 of the decoder IC1 via the first, the inverter IC5 / 1 and the third output Q2 _. double flip-flop IC3. The inputs of the first and second circuit IC4 / 1 IC4 / 2 negation disjunction, which are connected to the output of the input separator 26, constitutes the control input C of the control circuit 21. The output Q ₂ of the double-flop IC3 constitute breeding output Q of the control circuit 21, while the sixth the output Q _{22 of the} double counter IC2 forms the output 1 of the switching state of the control circuit 21.

The control circuit 21 described above is incorporated into a measuring module 8, the individual components of which are shown in FIG. 3 as follows. The address identification unit 23 comprises a four-bit digital comparator having an equality indication output and four switches capable of transmitting to the digital comparator a logical level YES - and in the next logical level H - and a logical level NO - in another level L - as comparative patterns . The first memory unit 17 is preferably formed by two 8-bit fixation bistable circuits. The analog-to-digital converter 16 is an integrated circuit with binary sequentially approximated outputs with three states and a trigger input. Serial-parallel converter 20 is a step register with a serial input and a clock pulse input. The parallel-serial converter 19 is an eight-channel selector with three control inputs, by means of which the eight inputs can be selected in the appropriate sequence. The output of the parallel-serial converter is connected to the power supply via a resistor. The bypass circuit 24 is a product circuit.

In Fig. 5 the function of the apparatus shown in Figs. 3 and 4 can be monitored by means of time diagrams.

In FIG. 5, the signals appearing at the first output 0- ^, a second outlet ₁₂ and the Q output of the third double counter IC2 and to the first output Q _q decimal decoder IC1 signals actually occurring at the output A of the parallel-serial transfer control circuit 21, wherein the first output and a second output Q _q decimal decoder IC1 are characteristic of the second portion a 'output of the controller in parallel - serial converter 19. the output Q ₂ of the double flip-flop IC3 is identical to G připouštěcím output control circuit 21 and the sixth output of the double counter -22 IC2 is identical to the data state switching output I of the control circuit 21.

In the above-mentioned manner, computer-supplied two-syllabic information is transmitted to all measuring modules 8 connected to the module bus 15. The first syllable activates the control circuit 21 via its trigger input B. The modular responses arise when the address identification unit 23 releases the control input 21 of the control circuit 21. Serial bits coming from the input separator 26 are routed to the control input C of the control circuit 21. Control circuit 21 receives clock pulses from the CK line of clock pulses.

255957

The command bits are written from the first and second outputs E, F to transmit the double counter IC2 write command from the first memory unit 17. The first syllable contains, status information related to the housing 12, the position of the actuators 22, while the second syllable contains a digitized analog signal.

The data state switching output 2 of the control circuit 22 separates the data from the status information. The analog-to-digital control output H of the control circuit 21 actuates the analog-to-digital conversion. The parallel-serial conversion output A of the control circuit 21 of the serial-parallel conversion, while the second portion A 'of the outputs of the parallel-serial converter 19 controls the start and stop bits. The admission output G of the control circuit 21 releases the admission circuit 24 upon a valid query. The signal appearing on the trigger input В flips the first flip-flop of the double flip-flop IC3, whereby the logic level L appears on the first output of the double flip-flop IC3, while on the second output Q? double flip-flop IC3 appears logical level H.

This releases the double counter IC2, which starts counting, since at its first clock input it receives clock pulses from the clock CK line. The double counter IC2 counts to ten, its first, second and third outputs 0-12 '-13 control the parallel-serial converter 19, thus always matching the corresponding bit to the output of the parallel-serial converter 19, see FIG. FIG. 5, signals at the first, second and third outputs of the double counter IC2. The start and stop bits are generated by the decoder IC1, i.e. at its first output Q _q and the second output Qg.

When the first output Q _{q of the} decoder IC1 is brought to the logical level H and its second output Qg to the logical level L, the parallel-serial converter 19 is selected, but its output is not enabled and goes into a high impedance state. the output gets to logic level H by the resistance applied to the supply voltage. If its first output Q _{q is} at logic level L and its second output Qg reaches logic level H, the output of the serial converter 19 is paralleled to logic level L, thereby not releasing the circuit.

The period of the signal appearing on the Q output _{14 of} the fourth double counter IC2 equal to ten pulses of the clock signal. This output produces the clock signal of the other half of the double counter IC2. The fifth output Q ₂₁ and the sixth output of the second half of the double counter IC2 are via a delay element Λ in a logical product session using a first logical product 1С6 / 1 whose output signal resets the first and second flip-flop circuits of the double flip-flop IC3. Then the ten-bit sequence is terminated three times and the process can start from the beginning.

The first flip-flop, as already mentioned, is flipped by the signal coming to the trigger input V of the control circuit 21, while the second flip-flop is flipped by the write signal of the first output E for transmitting the write command of the control circuit 21.

This signal writes the bits appearing at the output of the serial-to-parallel converter 20 to the first 8-bit portion of the first storage unit 22. The signal of the first output E for transmitting the write command of the control circuit 21 arises with the logical level L of the following signals:

the signal inverted by the first inverter IC5 / 1 and derived by the first derivative circuit (iif ii of the second output Qg of the decoder IC1), the control input signal C of the control circuit 22 of the fifth output signal _{21 of the} double counter IC2.

When the write signal of the first output E for transmitting the write command, the control circuit 21 flips the second flip-flop circuit of the double flip-flop IC3 goes second output Q ₂ of the double flip-flop IC3 to logic level H, and since this same připouštěcím output G of the control circuit 21 releases the second output signal E for transmitting the write command of the control circuit 21.

The write signal of the second input F for transmitting the write command of the control circuit 21 causes the second syllable of the signal received serially at the control input 21 of the control circuit 21 to be written to the second 8-bit portion of the memory of the first memory unit. The write output signal F for transmitting the write signal of the control circuit 21 arises when the logic level L of the following signals coincides:

the signal at the control input C of the control circuit 21, the signal of the fifth output Q _{21 of the} double counter IC2 inverted by the third inverter LC5 / 3. Q output signal of the second decoder IC1 _g decimal inverted by the first inverter IC5 / 1, the output signal of the second flip-flop IC3 double flip-flop on its third output Q _2nd

The control state data switching state output 21 releases the output of the analog-to-digital converter 16. The control state data switching state output I signal is at logic level H during the output of the data bits, as shown in the timing diagram. The analog-to-digital conversion control output signal H of the control circuit 21 actuates the analog-to-digital converter 16. This signal is generated from the admission signal of the admission output G of the control circuit 21 synchronously with the clock signal appearing on the CK line of clock pulses by differentiation.

It is clear from the above terminals that when querying each of the measurement modules 8, the sequence citation begins, but the response arises only when the measurement module 8 recognizes its own address, i.e. in the signal appearing on the control circuit input D. During identification, the command bits are written to the first memory unit 17, the status information is delivered, the analogue-to-digital conversion is activated and the converted information is returned.

Claims (3)

The object of the invention An apparatus for input biological signal processing, in particular for multi-channel medical microcomputers, provided with measuring systems by which they are galvanically separated and provided with measuring modules composed of standard components and connected to sensors and a standard contact circuit, characterized in that the measuring modules (8) are via a galvanic isolation unit (28) via an input contact circuit (5) connected to a module bus (6) adapted for individual measuring modules (8) having a standard output contact circuit (7), a signal conditioning module (3) 8), provided with controllable analog switches and amplifiers, is connected to the galvanic isolation unit (28) via the input processing digital unit (4), the input processing unit (4) being connected to the input amplifier (26) and the output separator (25) of the galvanic isolation unit units (28) as a power supply unit (27) also providing a clock signal, the input separator (26) being connected both to the control input (C) of the control circuit (21) and to the input of the serial-parallel converter (20) whose output is connected to the first memory unit (17), firstly with the trigger input (B) of the control circuit (21) as well as with the address identification unit (23), the output of the address identification unit (23) being connected to the admission input (D) of the control circuit (21); the first memory units (17) are connected to the control inputs of the signal conditioning unit (3), further the output of the signal conditioning unit (3) is connected to an analog-to-digital converter (16) whose parallel outputs are connected via a data control selector (18) , a parallel-serial converter (19) and an admission circuit (24) to the output separator (25), further a quad and second output (E _a , F) for transmitting a write command the control circuit (21) is connected to the first memory unit (17), the analog-to-digital conversion control output (H) of the control circuit is connected to the analog-to-digital converter (16), the data state switching output (I) of the control circuit (21) is connected to the data control selector (18), the parallel-serial conversion control output (A) of the control circuit (21) is coupled to the parallel-serial converter (19), and the admitted output (G) of the control circuit (21) is coupled to the admitted circuit (24), wherein the inputs of receiving status information of the data control selector (18) are coupled to the control bodies (22). 255857 8 Apparatus according to claim 1, characterized in that the signal conditioning unit (3) is provided with analog CMOS switches and its amplifier is a low power operational amplifier. Device according to claim 1 or 2, characterized in that the measuring module (8) is a separate, releasably connected unit to the modulated bus (6).