CS246409B1 - Involvement for analysis of non-periodic events in digital devices - Google Patents

Abstract

The connection in combination with an oscilloscope creates a measuring instrument for analyzing logical signals. The inputs are connected to the first, second to fifteenth comparators, which are connected to the first, second to fifteenth RAMs, whose outputs are fed to the display block and simultaneously to an auxiliary block, whose output is connected to a hexadecimal display unit, while the digital comparator is connected to a control logic block, whose first output is fed to the RAM, the second to an address generator and the third to a display block, whose first output is fed to the RAM, the second to an address generator and the third to an amplifier with three outputs connected to an external oscilloscope. The address generator has an external sampling input connected and its output is connected to the RAM. The digital comparator is connected to an external synchronization input, a comparison word block and a digital delay block.

Description

246409

BACKGROUND OF THE INVENTION The present invention relates to the connection of analysis of periodic events in digital devices which, in combination with an oscilloscope, produces a meter for analyzing logic signals.

The constant growth of the complexity of digital and mainly computer, respectively. microcomputer systems have forced the design of devices that are capable of detecting an error and a particular location, possibly originated from hardware or software. Current devices by world-class manufacturers of cost-effective, dedicated devices, their servicemen require deep software knowledge, some have a firmly set decision level and usually provide two-state output information in a formal time course. The ambiguous ones evaluate the unconnected input in relation to the logic zero and logical one levels. Most of the current devices evaluate the unconnected input as a logical one. Also, it incorrectly evaluates the logical state if the bus input is in the third state, or have an incorrect voltage level. At a low sample rate in relation to the sensed waveform, levels recorded at the moment of the sampling pulse arrive in memory. This results in loss of information when multiple input signal changes occurred between the court sampling pulses. Some devices only work in one logic, usually in TTL. The above-mentioned drawbacks are eliminated by the device for analyzing non-periodic events by digital devices according to the invention. The inputs are connected to a first, second to pat-board comparator, which are connected to the first, kinds of RAM, whose outputs are fed to the display block simultaneously to an auxiliary block, which output is coupled to a hexadecimal display unit, the digital processor being connected to a control logic block, the first output of which is output to the RAM memory, the second output to the address generator, and the third display block whose first output is connected on the RAM memory, the second on the address generator and the third on the three-output amplifier connected to the external oscilloscope. The address generator has attached external sampling and its output is connected to the RAM memory. An external synchro- nization input, a comparative word block, and a digital delay block are connected to the digital compiler. The advantage of this solution is the rapid detection of errors in the measured system when the classicizing apparatuses, multimeters or oscilloscopes are practically unusable. In oscilloscope-equipped workstations, this connection will extend its use to simultaneously track 16 waveforms and keep them in digital form. It is also capable of retaining non-periodic signals and allowing events to be captured before or after the trigger pulse.

The schematic diagram of the present circuit is shown in the attached drawing.

Inputs 100 to 115 are connected to the first to fifteenth comparator 1. The comparators 1 are connected to the first to the fifth RAM memory. The RAM memory outputs 2 are fed to the display block 8 and simultaneously to the auxiliary block 10, the output of which is connected to the hexadecimal display unit 11. The digital comparator 5 is connected to a control logic block 4, the first output of which is brought to memory 2 RAM , a second address generator 3, and a third to display block 8. Its first output is coupled to memory 2 RAM, the second to address generator 3 a third to amplifier 9, which is connected to an external oscilloscope by three outputs 90, 91 and 92. An external synchronization input, a comparative word block 7 and a numeric delay block 6 are connected to the digital comparator 5. An external sampling input 30 is connected to the address generator 3. An important feature of the wiring is quadruple on-screen information, where: "0" = logical zero character "1" = logical one character "X" = third state, disconnected input, per-prime level, low sampling rate, character "-" “= Unwritten memory.

By varying the decision levels, it is possible to investigate different logic. In addition to displaying the characters, it is possible to select a digitized alcohol output waveform display of 2 RAM.

The analyzed digital device is connected to the input comparators 1. The number of connected signals can be expanded. For the analysis in the microprocessor field, it is appropriate to select the number of signals to be analyzed, eg 16. In input inputs 1, the input signal is compared with an adjustable reference level for the logical zero and the logical unit, and is evaluated as a logical zero, a logical unit, possibly as a forbidden condition. The bars appear as "0", "1", "X". A pair of 2 RAM memorized for each channel is written for comparison. The 2 RAM RAM is sampled either by an adjustable frequency in the address generator 3 or by external sampling input 30 of the time-analyzed digital device.

The first case is suitable for hardware analysis, the sampling is asynchronous with respect to the analyzed system, and the second case is suitable for software analysis, eg control of a microprogram, is sampled synchronously. As a forbidden condition, 246409 6 is also evaluated if at least one whole pulse occurs, e.g. gambling.

Also, any of the inputs 100 to 115 is not -not connected, as a forbidden condition. Prior to writing to RAM 2, they are adjusted to a predefined state that is displayed by the alcohol. In this way, we cannot get ambiguous measurement results and thus a flawless closure in the analysis. Writing 2 RAM memory takes place cyclically, after filling up, the steam is rewritten, address bus selection 2 controls RAM. Writing stop and subsequent display is conditioned by the arrival of synchronization event. This synchronization can occur either: a) External synchronization input signal. For example, this signal may be a microprocessor device error signal. b) The appearance of such a combination of input signals-v at the inputs 100 to 115 that we have assumed and pre-set the comparator word menu 7. In these cases, the contents of 2 RAM will be displayed before the sync event appears. c) If a digital delay is selected, the synchronization occurs after the set number of pulses has elapsed after the trigger word has been discovered. This delay can be set numerically on the keys in the 6-digit delay block.

After processing in the circuit of the numerical comparator 5, the control logic block 4 is switched to the read mode. In the address generator 3 in the address counter, the address to which it was last written is retained. In the 2 RAM memory, the most recently written bands, such as the last 256 16-bit words, are located.

The last write address must be added to the display address so that the data in the administrative order appears on the oscilloscope screen. The address bus now selects the individual cells by storing 2 RAM with a stable reading frequency. If no delay has been set, the trigger word that caused the synchronization will appear on the screen last. The digital delay block 6 allows data to be displayed after the combo word has arrived and after the determined count of clock pulses or comparisons selected in the delay block 6 has been passed.

The display block 8 and the amplifier 9 is a separate functional unit of the device. They transfer the information from the input screen to the oscilloscope operating in the X / Y mode. The time base of the display block 8 creates a raster on the screen. Synchronously with the beam motion along the screen, the oscilloscope is modulated by the PROM memory content, where the embedded content corresponds to the shape of the displayed characters or the element of the alpha waveform.

When displaying information, a 24-bit long section is displayed from each RAM 2 memory. Up to a maximum of 16 memorized 2 RAMs, ie, character lines or analogue waveforms, can be displayed on-screen for maximum use of the display circuitry and screen area. Another task of the display block 8 is to control the operation of the address generator 3 over the display and to ensure synchronous development of adriess-display information. Similar to the signaling from the display block 8, the connection of such a memory 2 of RAM is ensured, the content of which is assigned to the displayed display characters.

In particular, the amplifier 9 concentrates the display imaging circuitry generating the capture voltage for the inputs X, Y of the oscilloscope, the amplifier and the signal amplifier for the luminance modulation of the oscilloscope. synchronizes the operation of the sub-block 10 with the cursor state on the screen.

The auxiliary block 10 is a complement to the device, the output of which is a four-seven-segment display forming a hexadecimal display unit 11. The task of the block 10 is to provide a hexadecimal listing of the oscilloscope screen located in the cursor region on the sedeimmune displays. The representation of characters is controlled by the abbreviation of contents, where the embedded content corresponds to the shape of the displayed numeric and alphabetic characters used by the hexadecimal system. A special sign is the "hyphen" if the selected word contains an undefined binary value.

Claims (2)

246409 7 8 PREDMEI Involvement for the analysis of non-periodic de-Jovs in digital devices, characterized in that the inputs (100 to 115) are connected to the first, second to fifteenth comparators (1), which are connected to the first, kind to pat-to-remember memory (2) RAM whose outputs are fed to a blocking block (8) and simultaneously to a block (10) whose output is linked to a hexadecimal display unit (11), the digital comparator (5) being connected to the block (4) control logic, the first output of which is provided to the RAM memory (2), the second to the address generator (3), and the third to the display block (8) whose first output is connected to the memory (2) of the second, an address generator (3) and a third to an amplifier (9) with three outputs (90, 91, and 92) connected to an external oscilloscope, while the address generator (3) has an external sampling input (30) connected to the memory (2) RAM, wherein an external synchronization input (50), a comparative word blob (7) and a digital delay block (6) are connected to the digital comparator (5). 1 sheet of drawings