CS236302B1 - Wiring to transform the alphanumeric keypad code - Google Patents

Abstract

The aim of the invention is to enable the use of the alphanumeric display Sk 7202 and its keyboard for devices that do not have small alphabet characters, namely by simple connection, which when permanently connected can be put out of operation by simply switching switches. The stated aim is achieved by connection with logic circuits, where the display 3!.I 7202 performs code combinations of small experts into code combinations of large characters, with the exception of the code combination of the DEL key, which is left in its original state. It does not matter whether the display mode is currently set for small or large characters. The display SK 7202 modified in this way can be used for effective use of the INTELLEG KDS 800 development workstation both in creating complex programs and in activating newly developed devices using the ICE 80 emulator.

Description

The invention relates to a circuit for transforming an alphanumeric keypad code operating in KOI-7 code.

The INTELLEC MDS 800 development center and its operating system only accept and transmit ASCII capital letters. If an appropriate alphanumeric display is not available for this site, using the SM 7202 alphanumeric display with a K0I-7 keypad causes some difficulty, as the display sends and receives both uppercase and lowercase alphabetic characters x of KOI-7, but shows on the display screen only capital letters. Information on the shift to large alphabet is indicated on the auxiliary panel, which is not very prominent and easy to overlook. The use of the SM 7202 display is further hampered by the DEL key, which deletes characters that are frequently used and included in a small character set. The operator is thus burdened by inefficient shifting of the display to uppercase and lowercase mode, without taking into account the frequency of errors and their impact on the work with the INTELLEC MDS 800 development device.

These drawbacks are eliminated by the KOI-7 alphanumeric keypad transformation transformer according to the invention, which is based on the REMOTE signal input terminal being connected to the REMOTE signal output terminal, the SHIFT signal input terminal being connected to the SHIFT signal output terminal, the signal input terminal b8 is connected to b8 signal output terminal, b7 signal input terminal is connected to b7 signal output terminal, to the seventh inverter input, and to the third input of the second 3-input logic negation circuit, b6 signal input terminal is connected to the sixth inverter input, signal input terminal b5 is connected to b5 signal output terminal and fifth inverter input, b4 signal input terminal is connected to b4 signal output terminal and fourth inverter input, b3 signal input terminal is connected to Γ3 signal output terminal and third inverter input terminal, input terminalsignal b2 is

238 302 connected to the output terminal b2 and the input of the second inverter, the input terminal of the signal bl j $ is connected to the output terminal of the signal b2 and to the input of the first inverter, the positive voltage input terminal is connected to the positive voltage output terminal. ZEMI is connected to output terminal for ZEMI, input terminal of SIG.IMP signal is connected to output terminal of SIG.IMP signal, input terminal for ZEM2 is connected to output terminal for ZEM2, eventually input terminals for ZEM3 to ZEM6 are connected to output terminals for ZEM3 to ZEM6, the first inverter output is connected to the first and second inputs of the eight-input logic product negation circuit, the second inverter output is connected to the third input of the eight-input logic product negation circuit, the third inverter output is connected to the fourth input of the eight logic negation logic input the output of the fourth inverter is ex connected to the fifth input of the eight-input logic product negation circuit, the output of the fifth inverter is connected to the sixth input of the eight-input logic product negation circuit, the output of the sixth inverter is connected to the seventh input of the eight-input logical product negation circuit the product and through the switching element both to the second and third input of the third three-input circuit of the negation of the logic product, and through the second resistor to the positive voltage output terminal, the seventh inverter output is connected to the eighth input of the eight input input of the first three-input circuit of the negation of the logical product and to the first input of the second three-input circuit of the negation of the logical product, the output of the second three-input circuit of the negation of the logical product is connected to the third input logic product negation circuit, the first input of which is connected via the first resistor to the positive voltage output terminal, and through another switching element to the output terminal for ZEM2, the output of the first three-input logic product negation circuit is connected to the first input, the third three-input circuit type of logic product negation, the output of which is connected to the output terminal of the signal b'6.

The advantage of wiring for transforming the alphanumeric keypad code operating in the KOI-7 code of the invention is that the SM 7202 display generates only uppercase alphabetic characters, ASCII code and the correct DEL key code, with number and other character codes corresponding to ASCII code regardless display mode, it is re3

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Also give him lower or uppercase alphabets. The wiring is simple, making it possible to efficiently use the development workstation to create complex programs and use the ICE 80 emulator to revive newly developed devices, saving time and reducing operating errors. By simply switching the switches, the wiring can be deactivated when the displays of the MDS 800 are used without having to remove them.

An example of a circuit for transforming the alphanumeric keypad code operating in the KOI-7 code of the invention is shown schematically in the attached drawing.

The REMOTE signal input terminal 1 is connected to the REMOTE signal output terminal 01. The SHIFT signal input terminal 2 is connected to the SHIFT signal output terminal 02. The input terminal 3 of signal b8 is connected to the output terminal 03 of signal b8. The input terminal 4 of the signal b7 is connected to the output terminal 04 of the signal b7, to the input of the seventh inverter 25 and to the third input of the second three-input logic-type negation circuit 30. Input terminal 9 of signal b6 is connected to input of sixth inverter 24 · Input terminal 6 of signal b5 is connected to output terminal 06 of signal b5 and to input of fifth inverter 23. Input terminal 7 of signal b4 is connected to output terminal 07 of signal b4 and The input terminal 8 of the signal b3 is connected to the output terminal 08 of the signal b3 and to the input of the third inverter 21. The input terminal 9 of the signal b2 is connected to the output terminal 09 of the signal b2 and the input of the second inverter 20. it is connected to the output terminal 010 of the signal b1 and to the input of the first inverter 19. The positive voltage input terminal 11 is connected to the positive voltage output terminal 011 + 5V. The ZEMI input terminal 12 is connected to the ZEMI output terminal 012. The SIG.IMP signal input terminal 13 is connected to the SIG.IMP signal output terminal 013. The ZEM2 input terminal 14 is connected to the ZEM2 output terminal 014. Input terminal 15 for ZEM3 is connected to output terminal 015 for ZEM3. Input terminal for ZEM4 is connected to output terminal 016 for ZEM4 · Input terminal 17 for ZEM5 is connected to output terminal 017 for ZEM5. The ZEM6 input terminal 18 is connected to the ZEM6 output terminal 018. The output of the first inverter 19 for signal b1 is connected to the first and second inputs of the eight-input logic-type negation circuit 26. The output of the second inverter 20 for signal b2 is connected to the third input of the eight-input circuit 26

236 302 logical product negation. The output of the third inverter 21 for signal b3 is connected to the fourth input of the eight-input logic-type negation circuit 26. The output of the fourth inverter 22 for signal b4 is connected to the fifth input of the eight-input logic product negation circuit 26. The output of the fifth inverter 23 for signal b5 is connected to the sixth input of the eight-input logic-type negation circuit 26. The output of the sixth inverter 24 for the signal b6 is connected to the seventh input of the eight-input logic-type negation circuit 26, to the second input of the second three-input logic-type negation circuit 30 and via the switching contact of the second switch 31? negation of the logic product, on the one hand through the other resistor 33 to the + positive 5V output terminal 011. The output of the seventh inverter 25 for the signal b7 is connected to the eighth input of the eight input logic product negation circuit 26, the output of which is connected to the second input of the first three input logic product negation circuit 29 and to the first input of the second three input logic product negation circuit 30. The output of the second three-input logic product negation circuit 30 is connected to the third input of the first three-input logic product negation circuit 29, the first input of which is connected via a first resistor 27 to the + + 5V output terminal 011 and the output terminal 014 for ZEM2, the two switches 28, 31 being coupled to each other. The output of the first three-input logic product negation circuit 29 for signal b'6 is connected to the first input of the third three-input logic product negation circuit 32 whose output for signal b'6 is connected to the output terminal 05 of signal b'6.

The wiring is arranged on a printed circuit board. The input terminals 1 to 18 are arranged on an input connector that connects to the keyboard output connector. The output terminals 01 to 018 are arranged on an output connector that connects to the display electronics input connector. It is not necessary to connect the two switches 28 »31.

The output from the alphanumeric keypad of the SM 7202 display is parallel, 8-bit. The lowest bit is denoted by function b and the highest by b8. The functions b1 to b8 are numbered identically to the alphabetical table of the International Reference Version. The function b8 is even parity to the code combination. The transformation itself applies only to function 56, which is marked after the transformation

238 302 as a function of b ^{out of} 6. For a transformed function h'6, if the functions b7 at logical level zero, the function b'6 goes to logical level one. If b7 goes to logic level one, then b'6 = b6. For the code combination of the DEL key, it must not change and the function b'6 = b6. If a small alphabetic character is displayed on the SM 7202 display keypad, for example a lowercase a character whose code combination at the keyboard output is in the order of functions b7 to B1 = 0011110, the transformation of function b6 is applied as follows. In this combination, you can see that b7 is zero at logical level. This causes the output of the second three-input logic product negation circuit 30 to go to logic level one independently of the logical levels of the other two inputs of the other three-input logic product negation circuit 30. Inputs of the first three-input logic product negation circuit 29 are provided with logical levels one of the output of the second three-input logic product negation circuit 30, the eight-input logic product negation circuit 26, and also from the open switch 28. which is at logic level zero is connected to the input of the third three-input circuit 32 of the negation of the logic product, whose other inputs are also at the logical level one from the other switch 31. Output of the third three-input circuit 32 of the negation it will be one at logical level. The resulting output code combination b1 to b7, whose function b'6 = 1, corresponds to the capital A character. For the code combination of the DEL key on the keyboard output, functions b1 to b7 are all at logical level zero. After inversion of functions b1 to b7 by inverters 19 to 25, logic levels one are applied to all inputs of the eight-input logic-type negation circuit 26. The output of the eight-input logic product negation circuit 26 goes to logic level zero, which independently of the logical levels of the remaining inputs of the first three-input logical product negation circuit 29 goes to logic level one via the output of the first three input logic product negation circuit 29. The output of the third three-input logic-type negation circuit 32 as a function of Έ 16 goes to logic level zero because all the inputs of the third three-input logic-type negation circuit 32 are at logic level one. It can be seen that there was no change in output function 5 * 6 compared to input function b6. Thus, the code combination of the DEL key is transferred in its original state.

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For code combinations of capital letters, b7 will always be equal to logic level one. The third input of the second three-input logical product negation circuit 30 will receive both logic level one from function b7, and the output of the eight-input logical product negation circuit 26 unless the DEL character is issued and the second input of the second three-input logical product negation circuit 30 brings inversions of function b6. This is copied over the first three-input logic product negation 29 and the third three-input logic product negation circuit 32 as a function of b * 6 with the same logical level as coming from the keyboard output. This means that code combinations of uppercase characters will remain in their original state. Switching both switches 28, 31 disables the code combination transformation and restores the 5M 7202 to its original state.

The invention can be used to connect the SM 7202 display with an alphanumeric keypad to the INTELLEC MDS 800 development site.

Claims (1)

SUBJECT OF THE INVENTION 236 302 An alphanumeric keypad code transformation circuit, characterized in that the REMOTE signal input terminal (1) is connected to the REMOTE signal output terminal (O1), the SHIFT signal input terminal (2) is connected to the SHIFT signal output terminal (02), input terminal (3) of signal b8 is connected to output terminal (03) of signal b8, input terminal (4) of signal b7 is connected to output terminal (04) of signal b7, to input of seventh inverter (25) and to third input of second three-input circuit (30) logic product negation type, input terminal (5) of signal b6 is connected to input of sixth inverter (24), input terminal (6) of signal b5 is connected to output terminal (06) of signal b5 and to input of fifth inverter (23) , the input terminal (7) of signal b4 is connected to the output terminal (07) of signal b4 and to the input of the fourth inverter (22), the input terminal (8) of signal b3 is connected to the output terminal (08) of signal b3 and to input t the third inverter (21), the input terminal (9) of signal b2 is connected to the output terminal (09) of signal b2 and to the input of the second inverter (20), the input terminal (10) of signal b1 is connected to the output terminal (010) to the first inverter input (19), the positive voltage input terminal (11) is connected to the positive voltage output terminal (011), the ZEMI input terminal (12) is connected to the ZEMI output terminal (012), the signal input terminal (13) The SIG.IMP is connected to the output terminal (013) of the SIG.IMP signal, the input terminal (14) for ZEM2 is connected to the output terminal (014) for ZEM2, or the input terminals (15 to 18) for ZEM3 to ZEM6 are connected to output terminals (015 to 018) for ZEM3 to ZEM6, output of the first inverter (19) is connected to the first and second inputs of the eight input circuit (26) of the logic product type, output of the second inverter (20) is connected to the third input of the eight input circuit type of negation logick the output of the third inverter (21) is connected to the fourth input of the eight-input logic product negation circuit (26), the output of the fourth inverter (22) is connected to the fifth input of the eight-input logic product negation circuit (26), the output of the fifth inverter (23 the output of the sixth inverter (24) is connected to the seventh input of the eight input circuit (26) of the negation of the product, to the second input of the second three input circuit (30) of the negation of the lo8 type 238 302 of the logic product and through the switching element both to the second and third input of the third three-input circuit (32) of the type of negation of logical product, and through the second resistor (33) to the positive voltage output terminal (011). the eighth input of the eight-input logic product negation circuit (26), the output of which is connected to the second input of the first three-input logic product negation circuit (29) and to the first input of the second logical product negation type three input circuit (30); ) of the logic product negation type is connected to the third input of the first three-input logic product negation circuit (29), the first of which is connected via the first resistor (27) to the positive voltage output terminal (011) and through another switching element to the output terminal For ZEM2, the output of the first three-input logic-type negation circuit (29) nu is connected to the first input of the third three-input logic product negation circuit (32), the output of which is connected to the output terminal (05) of the signal b'6.