CS232011B1 - Manufacturing process shortchannel mos tranzistor - Google Patents

Description

232 011

The present invention provides a method for producing a short-channel MOS transistor with a polycrystalline silicon gate - Salyi " poly-Si "

So far known MOS transistor® processes use the thermal oxidation process, thermal diffusion®, chemical deposition from the gaseous phase. - CVD saline, ion implantation and Standard contact photolithography. A disadvantage of these methods is the inability to use standard photolithography in the production process of the short-channel MOS transistor, since this does not produce a reproducible dimension below 4 to 5 µm.

The aforementioned drawbacks are obviated by the method for producing a polycrystalline silicon dioxide gate gate MOS transistor. with a polycrystalline silicon and metal gate, employing an intramuscular implant technique, the core of which is a polycrystalline gate is formed by selective plasma chemical adhesion of the polycrystalline silicon to the photoresist and by selective thermal oxidation of the formed polycrystalline gate structure. During thermal oxidation, the surface of the polycrystalline silicon is protected by a layer of silicon nitride etched in conformance with the structure of the polycrystalline silicon. At present, the high temperature and oxidation to the self-imparting photoresist impregnated admixture preferentially diffuse across the interface between the plant-oxide and the substrate into the gate region. The result of this whole process is a self-enclosed polycrystalline gate. The advantage of the method of making the short-channel MOS transistor is to use standard contact mask photolithography, while achieving a high-precision reproducible size of the gate pin, which reduces the transistor's parasitic capacities, shortens the channel length and thereby increases transistor operating frequencies. 232 011

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A characteristic process for the production of the short-channel MOS transistor poly-Si gate, respectively, is shown in the attached drawings. FIG. 1 is a sectional view of a thermally-grown coarse oxide Si plate which is formed by a photolithograph of a first mask and a collector and emitter diffusion is made.

Fig. 2 is a sectional view of the Si-plate after more technological operations such as: forming a coarse oxide according to a second mask, growing the gaseous oxide, deposition of poly-Si, diffusion into poly-Si, deposition of Si-N 2, photolithographic shaping of photoresist under mask. Fig. 3 is a sectional view of the Si-plate after other technological operations such as: etching of the Si-N-layer on photoresist-unmasked surfaces; plasma-chemical etching of poly-Si on foamer-unmasked surfaces with its subsequent homogeneous adhesion to the photoresist to the desired poly dimension; -Si, implanting hem implants. Fig. 4 is a sectional view of the Si-plate after further technological operations such as: photoresist removal, thermal oxidation of the coarse oxide, maskless etching of the SiO 2 layer. In Fig. 5, the Si-plate section after other technological operations such as: etching contact holes according to the fourth mask, steaming the metallic Al-layer, forming the Al-layer according to the fifth mask. The method for producing the short-channel MOS transistor according to the invention is made by increasing the basic high-resistance, monocrystalline type conductivity, Si-plate 1 by thermal oxidation of the coarse oxide layer 2, which is photolithographically formed by a parquet mask. Furthermore, a thermal diffusion of the admixture 3 is carried out in the opposite direction to that of the base Si-plate 1. The state after these operations is only shown in FIG. -Si 5, whose conductivity is enhanced by thermal diffusion of the additive. Next, the deposition is carried out by the CVD method, the SiN4 layer 6. The deposition and photolithographic formation of the photoresist according to the third mask follows. The state after these operations is shown in Fig. 2. Next, the plasmachemical bonding of the SiO2 ^ 6 layer and the poly-Si layer 5 on photoresist uncovered surfaces follows. In etching the poly-Si layer 5, this is etched in the photoresist 7 to the desired size poly-Si XI. The following is an ionic implantation of admixture 8 of the same conductivity type as type 232 011-3 - admixture diffusion Condition after these operations Figure 3 is followed by removal of the photoresist and thermal, local oxidation of coarse oxide 9 and poly-Si 5, during which the implanted admixture 8, which, together with the thermo-diffusion, forms the collector and emitter region 10, is disintegrated. In the process-local local oxidation of the coarse oxide 9, there is a temperature-induced sag between coarse oxide 9 and Si-plate 1v the transition region of the coarse oxide 9 to the gate oxide 4, and those formation disorders in this region, of which the diffusion of the impregnated dopant is greater. This Java leads to the self-concealment of the MQS gate of the transistor. Next, the mask-free improvement of the Sulfur layer 6 is followed. The condition after these operations is shown in FIG. 4. The etching of the collector contact holes and the fourth mask emitter followed by vaporization of the Al layer, which is formed according to the fifth mask, follows. to create contacts 11. The status of this operation is in Figure * 5 ·

This method of producing a C-channel MOS transistor can be used in the design of both integrated circuits and discrete transistors. When used in integrated circuits, the chip area is not treated, but allows for a considerable, but reproducible, shortening of the MOS transistor channel, allowing an increase in the operating speed of the integrated circuit. When used in the design of particular transistors, insufficient water conductivity of the Si gate can be prevented. We remove this obstacle by covering the entire poly-Sihradlo. AI. The overlap of Al against the collector and emitter is already on the coarse oxide, so the parasitic capacities are small enough. The Al-Al layer can be shaped with the same layer as the poly-Si and Si-N 2 layers. Another possibility of increasing the water conductivity of the Si-gate is by sputtering the layer of hardenable metal. By annealing such a structure, a layer of silicide is formed. After the electroporated metal, we obtain a structure for the next standard treatment.

Claims (2)

OBJECT OF THE INVENTION 232 011 A method for producing a short-circuit MOS transistor with a polycrystalline silicon gate gate, respectively. with a gate combined from polycrystalline silicon and metal, using a self-enclosing planting technique, characterized in that the polycrystalline barrier is formed by selective plasmachemical erosion of the polycrystalline silicon against the photoresist and by selective thermal oxidation of the formed polycrystalline gate structure, the surface being surface of polycrystalline silicon protected by a silicon nitride layer etched in accordance with the structure of the polycrystalline silicon, preferably self-confining to the photoresist impregnated dopant preferably diffuses across the interface between the growth oxide and the substrate into the gate region, thereby forming a polycrystalline gate. 2 drawings