CS231127B1 - Wiring a Programmable Frequency Type N; (n + 1) / 1 - Google Patents

Abstract

Connection of a programmable frequency prescaler of type n; (n + 1)/1, which consists of a programmable divider, a coincidence circuit, a first auxiliary flip-flop, a blocking circuit, a first electronic switch, a number detector, a third electronic switch, a second auxiliary flip-flop and a gate.

Description

Author of the Invention (54) Connection of a programmable frequency divider type n; (n + 1) / 1

Connection of programmable frequency divider type n; (n + 1) / 1, which consists of a programmable divider, coicide circuit, first auxiliary flip-flop, lockout circuit, first electronic switch, number detector, third electronic switch, second auxiliary flip-flop, and a gate.

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The invention relates to a wiring of a programmable frequency divider type n; (n + 1) / l.

In the present process, on the principle of a frequency divider with multiple feedback is produced circuit HEF 4751 - universal frequency divider whose function is described in detail,

Gilese Versatile LSI Frequency Synthesiser System Electronical Componets and Application No. 2, 1980. KNOWLEDGE A detailed solution for a n-type programmable divider; (n + l) / l, that is its individual components of which it is composed. A detailed solution of the divider is not described in the data sheets

Frequency Synthesiser Integrated Circuit LN 123 - Frequency Synthesiser, LN 124 - Universal Divider January 1980, not in technical information Usé of LN 123 and LN 124

LOCMOS LSI Devices In Frequency Synthesiser Systems ”1979, or in the Digital Catalog

LOCMOS Integrated Circuits HE 4000 B Family October 1980 (LN 123 and LN 124 are HEF 4750 and HEF 4751 circuit designations). Therefore, the advantages and disadvantages of the programmable divider of the invention cannot be clearly formulated.

Connection of programmable frequency divider type n;

(n + 1) / l according to the invention consists of a programmable divider, coincidence circuit, first auxiliary flip-flop, blocking circuit, first electronic switch, second electronic switch, number detector, third electronic switch, second auxiliary flip-flop, and a gate, The programmable frequency splitter is connected simultaneously to the first input of the interlock circuit, the first input of the first auxiliary flip-flop, the first input of the second auxiliary flip-flop, and the first programmable splitter input whose second input is connected simultaneously to the output of the first auxiliary flip-flop. , to a third input of the first electronic switch, a first input of the second electronic switch, and a first input of the third electronic switch, wherein the third input of the programmable divider is simultaneously connected to the second input of the blocking circuit, t a first auxiliary flip-flop input, a third electronic switch input third, a third electronic switch input, a first gate input, and a second auxiliary flip-flop output whose second input is connected to a third electronic switch output having a second input connected to a second electronic second input switches, the second input of the first electronic switch, the fourth input of the first auxiliary flip-flop, and the output of the number detector whose first input, the second input, the third input, the nth input is simultaneously connected to the first data input, the second data input, the third data input, except nth data input and ns fourth input, fifth input, sixth input, except nth input of programmable divider whose first output, second output, third output, up to the th output is connected to the first input , second input, third input up to nth input koinc idenčního circuit whose output is connected to a second input of the auxiliary flip-flop, the output of the blocking circuit is connected to a first input of the electronic switch whose output is connected to the output f _ou programmable předdšliče frequency, wherein the synchronization of the outputs is connected to the output of the second an electronic switch and the speed feedback ZV ^ _n is connected to the second input of the gate whose output is connected to the third input of the auxiliary flip-flop.

The wiring of a programmable frequency divider type nj (i + 1) / l according to the invention is shown in Fig. 3. This wiring of a programmable frequency divider type nj (n + 1) / l consists of a programmable divider 1, coincidence circuit 2, first auxiliary flip-flop χ, the blocking circuit 4, the first electronic switch 2, the second electronic switch of the number 2 detector, the third electronic switch 8, the second auxiliary flip-flop 6 and the gate 10, the input of the programmable divider kmi3

231 127 turntable 1 is connected simultaneously to the first input 41 of the interlock circuit to the first input 31 of the first auxiliary flip-flop to the first input 91 of the second auxiliary circuit 2 ® ^{to the} first input 11 of the programmable divider 1 35 of the first flip-flop 2 to the third input 53 of the first electronic switch 5, to the first input 61 of the second electronic switch 6 and to the first input 81 of the third electronic switch 8, the third input 13 of the programmable divider 1 being connected to the second input 42 of the blocking circuit J. to the third input 33 of the first auxiliary flip-flop, to the third input 63 of the second electronic flip-flop 6, to the third input 83 of the third electronic flip-flop 8, to the first input 101 of the gate 10 third electronic switch wherein the second input 82 is connected simultaneously to the second input 62 of the second electronic switch 6, the second input 52 of the first electronic switch 2t ^{to the} fourth input 34 of the first auxiliary flip-flop} and not the output 7n + l of the number 2 detector. input 72. the third input 73 through nth input 7n is simultaneously connected to the first data input 1, the second data input to the third data input 2 through the nth data input to the fourth input 14. to the fifth input 15 «to the sixth input 16. except for the nth input In of the programmable divider 1, whose first output ln + k is connected to the first input 21, to the second input 22, to the third input 23, to the nth input 2n of the coincidence circuit 2, whose output 2n + 1 is connected to the second input 32 of the first auxiliary flip-flop 2, the output 43 of the blocking circuit Jr being connected to the first input 51 of the first electronic switch 11, whose output 54 is connected to the output £ programmable Pre-division, wherein the sync output SY is connected to the output 64 of the second electronic switch \ 6, and the speed feedback ZV ^ _n is connected to a second input 102 of AND gate 10 whose output 103.ie connected to the third input 93 of the second sub-flop 2 »

Connection of programmable n-type divider; (n + 1) / l according to the invention is new, there has not been a requirement for such a splitter in the field of controlled frequency dividers. Of the available materials, 4,231,127 materials, it was not possible to compare the advantages of the divider according to the invention with the divider used in the HEF 4751 circuit by Philips. The solution of the frequency divider according to the invention (Fig. 3) respects all requirements resulting from the use of the divider in the system of universal programmable frequency divider with multiple feedback (especially the maximum cut-off frequency and the possibility of setting n = 1).

The function of the programmable frequency divider type nj (n + l) / l will be further explained in the wiring of the programmable divider of Fig. 1, where the detailed logical structure of the individual blocks of the wiring shown in Fig. 3 is detailed. Figures 2a, b, e show timing diagrams of signals at some important points of the frequency divider. The function of the frequency divider according to Fig. 1 can be divided into three stages in terms of setting n: n »1, n» 2 and n> 2 (max 15) ·

a) Setting η = 1 detects number 7 detector by setting output v

logical levels' H. This ensures continuous adjustment of the first sub-flop 2 to state Qj ^{= H>} switching the first electronic switch J5, so as to allow passage of the input signal ^f IN ^{to the} ^ ^STU P ^ ou blocking circuit 4, and simultaneously switches the second electronic switch 6 so to be passable for the signal from output 9 of the second flip-flop. Fig. 2a shows idealized waveforms of signals at the important points of the programmable divider of Fig. 1 at η * 1. From Fig. 2a it can be seen that the frequency divider m at logic level L at ZV input · divide ratio 1. At logic level “H” has a frequency divider of 2.

b) The n »2 setting detects the number 2 detector by setting the output logic level L”. This ensures a permanent switching of the first electronic switch so that the signal 3 of the first auxiliary flip-flop 6 is connected to the output 6, the auxiliary flip-flop is not adjusted, and the second electronic switch 6 is switched to allow the signal circuit J to synchronization output SY. FIG. 2b shows

231 127 idealized Signal waveforms at some points of the programmable divider shown in Fig. 1 at n = l · From Fig. 2b it can be seen that the divider at logic level L at input ZV ^ _n divides ratio 2. With logic level changing to H changes the dividing ratio ^ divider to 3 »

c) When setting 2 <n <15, the function of the circuit in Fig. 1 is the same as in b) (n = 2). In addition, the programmable frequency divider 1 (16/1 counts down) is automatically included to provide the required counter capacity corresponding to the set number n from the integer range of 3 to 15 · Fig. 2c shows idealized time waveforms at some points of the programmable frequency divider according to Fig. 1 with the setting n 3 3 obr From Fig. 2c it can be seen that the divider at logic level L at input Z7 ^ _{n has a} partition ratio £ · Changing the logical level from L to H vyvol causes a partition ratio from 3 to 4 · often the setting n is not required over the whole range of integers 1 to 15. In these cases the connection according to Figs. 1 and 3 can be simplified. If only η = 1 is required, the first auxiliary flip-flop coincidence circuit 2, programmable frequency divider 1 second and third electronic switches

5. »6 ®® ^and number 2 detector * Only N = 2 requires omission of blocking circuit 4, coincidence circuit 2, programmable frequency divider!, Electronic first, second and third switches 6, 8, and number 2 detector« Μαβί- If n can be set in the range of integers 3 to 15, then the blocking circuit 4, the electronic first, second and third switches 6 and 8 and the detector number 2 can be omitted in Fig. 3. In terms of universality, for example for a monolithic circuit, 1 or 3.

Connection of programmable frequency divider type n;

(n + l) / l in conjunction with the _A q 231126 programmable frequency divider base module wiring · ® ^with the programmable module to create a fractional split ratio in the universal frequency divider according to AO 231128

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This wiring of a programmable universal frequency divider allows the upstream of several programmable type 10 splitters; (11) / 1 (data in BCD code) or type 16 (17) / 1 (<ata in binary code). The type of programmable divider is independent of the lowest weight distribution of the digit, which corresponds to a certain frequency grid of the output signal of the synthesizer. This allows very simple programming of the lowest digits without interfering with the programming of the higher digit. Therefore, the multi-feedback frequency divider system can be considered as the most modern and at the same time the most versatile in the world.

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OBJECT OF THE INVENTION

Claims (1)

Connection of programmable frequency divider type n; (n + 1) / l, characterized in that it consists of a programmable divider (1), a coincidence circuit (2), a first auxiliary flip-flop (3), a blocking circuit (4), a first electronic switch (5), a second electronic switch (6), a number detector (7), a third electronic switch (8), a second auxiliary flip-flop (9) and a gate (10), the input of the programmable frequency divider being connected simultaneously to the first input (41) of the interlock circuit (4), a first input (31) of the first auxiliary flip-flop (3), a first input (91) of the second auxiliary flip-flop (9), and a first input (11) of the programmable divider (1) (35) a first auxiliary flip-flop (3), a third input. (53) a first electronic switch (5), a first input (61) of a second electronic switch (6) and a first input (8I) of a third electronic switch (8), the third input (13) of the programmable divider (1) being connected at the same time a second input (42) of the interlock circuit (4), a third input (33) of the first auxiliary flip-flop (3), a third input (63) of the second electronic switch (6), a third input (83) of the third electronic switch (8) an input (101) of the gate (10) and an output (94) of the second auxiliary flip-flop (9), the second input (92) of which is connected to the output (84) of the third electronic switch (8). a second input (62) of the electronic switch (6), a second input (52) of the first electronic switch (5), a fourth input (34) of the first auxiliary flip-flop (3) and an output (7n + l) of the number detector (7) whose first input (71), the second input (72), the third input (73), the nth input (7n) is simultaneously connected to the first data input (1), the second data input (2), and the third data input (2), to the third data input input (3), except nth data input (n) and fourth input (14), fifth input (15), sixth input (16), up to nth input (ln) of the programmable divider (1) whose first output (ln + 1), second output (ln + 2), third output - 8 231 127 (ln + 3), until the th-th output (ln + k) is connected to the first input (21), the second input (22), the third input (23) to the nth input (2n) of the co-current circuit (2), the output (2n + 1) of which is connected to the second input (32) of the first auxiliary flip-flop (3), the output (43) of the locking circuit (4) being connected to the first input (51) of the first electronic switch ), whose output (54) is connected to the output f of the programmable frequency splitter, its sync output SY is connected to the output (64) of the second electronic switch (6) and its feedback input ZV _in is connected to the second gate input (102). 10), whose output (103) is connected to the third input (93) of the second auxiliary flip-flop (9) · 4 drawings 230 137 <0 SY h ‘ D Ct «o 9 $ cJ La CE PL π! Sl A B C D 1§ / a and CL · -j _ ___ = ^L 5.4 Bad Ί8 kJ i i___ JO [JO A BCJ> FIG 231 127