CS229798B1 - Connexion of i/o controlling circuit especially for inteligent terminals - Google Patents

Description

The invention relates to the connection of input and output control circuits, in particular for an intelligent terminal.

One of the basic functions of the smart terminals is the program control of the internal and external peripheral devices, which are optionally connected to the smart terminal via input and output control circuits. The connection of those input and output control circuits is therefore crucial both for the performance of the entire intelligent terminal and for its complexity and thus the cost of the device.

The known connections of the input and output control circuits have a number of disadvantages. The control circuits for a medium computer or minicomputer are so extensive that their use in small devices such as intelligent terminals is not possible. There are also input / output control circuits used, for example, in program calculators or intelligent terminals. However, these types of control circuits use special high integration circuits that are designed for a particular I / O control system and cannot be realized on smaller production runs because they require disproportionately high equipment costs. It is also known to connect the input and output control circuits, which are realized from small and medium integration circuits and which are still used for intelligent terminals. This wiring has the disadvantage that all input and output control commands are provided by autonomous means, without the support of the microprocessor functions of the processor, which leads to greater scope and complexity of the control circuits.

These drawbacks are eliminated by the connection of input and output control circuits, especially for the intelligent terminal according to the invention, which is based on the fact that the first input of the third two-input logic product negation circuit is connected to the third input of the sixth three input logic product negation circuit. The first and eighth type D flip-flops together form the eighteenth wiring input, the second input of the third two-input logic product negation circuit is connected to the data input of the eighth type D flip-flop whose one output is connected to the word selection inputs with the memory and at the same time form the seventeenth input circuit, the output of the third two-input circuit of the negation of the logical product is connected to the first input of the second two-input circuit of the negation of the logical product the logic product negation circuit, the output of which is connected to the clock input of the fourth quadruple dual-input multiplexer with memory, the output of the second dual input logic product negation circuit is connected to the clock inputs of the first to third quadruple dual-input multiplexer with memory the memory multiplexer is connected via the twenty-fourth resistor to the zero voltage terminal, on the other hand through the twenty-third resistor to the positive voltage terminal and is connected to the first input and output bus output, the second input of the first multiplexer of the first quadruple dual input memory multiplexer is connected to the first data output and the first data input of the first bidirectional inverting bus driver and simultaneously form the first wiring input, the first input of the second multiplexer of the first quadruple 2-input multiplexer with memory is connected through the twenty-second resistor to the neutral terminal * through the twenty-first resistor to the positive voltage terminal and second input and output bus, second input of the second multiplexer of the first quadruple dual-input memory multiplexer is connected to the third input the eighth three-input logic product negation circuit, the second data output and the second data input of the first bidirectional inverting fieldbus driver and simultaneously form the second wiring input, the first third multiplexer input of the first quadruple dual-input memory multiplexer connected to the zero voltage terminal firstly through the nineteenth resistor to the positive voltage terminal, secondly to the third output of the input and output bus, the second input of the third multiplexer of the first quadruple dual-input multiplexer with memory is p connected to the third data output and to the third data input of the first bidirectional inverting bus driver and forming the third wiring input, the first input of the fourth multiplexer of the first quadruple dual input multiplexer with memory is connected via the eighteenth resistor to the fourth input of the input and output bus, the second input of the fourth multiplexer of the first quadruple dual input multiplexer with memory is connected to the third addressing input of the eight-channel multiplexer for the data function, to the first input of the first converter from BCD to one of ten a data output and a fourth data input of the first bidirectional inverting bus driver and simultaneously form the fourth wiring input, the first input of the first multiplexer of the second quadruple dual-input multiplexer with memory The third input of the first multiplexer of the second quadruple dual input multiplexer with memory is connected to the second address input of the eight-channel multiplexer for the function the first input of the first converter from BCD to the code one of ten, to the first data output and to the first data input of the second bidirectional inverting bus driver and simultaneously form the fifth wiring input, the first second multiplexer input of the second quadruple dual input multiplexer with memory on the one hand through the fourteenth resistance to the terminal of zero voltage, on the other hand through the thirteenth resistance to the terminal of positive voltage, on the other hand to the sixth output of the input and output bus, the second input of the second multiplexer The memory jumper is connected to the first address of the eight-channel multiplexer for data selection, to the third input of the first converter from BCD to one in ten, to the second data output and to the second data input of the second bidirectional inverting bus driver. , the first input of the third multiplexer of the second quadruple dual-input multiplexer with the memory is connected via the twelfth resistor to the neutral terminal, through the eleventh resistor to the positive voltage terminal, and to the seventh input and output bus output, is connected to the fourth input of the first converter from the BCD code to the code one of ten, to the third data output and to the third data input of the second bidirectional inverting bus driver and forms the seventh wiring input, the first input of the fourth multiplexer of the second quadruple dual-input multiplexer with memory is connected through the tenth resistor to the zero voltage terminal, through the ninth resistor to the positive voltage terminal, and to the eighth input and output bus output. to the first input of the second converter from BGD code to the code one of ten, to the fourth data output and to the fourth data input of the second bidirectional inverting bus driver and forming the eighth wiring input, the first input of the first multiplexer of the third quadruple two-input multiplexer with memory inverter to the first data input of an 8-channel multiplexer for data selection, both through the eighth resistor to the zero voltage terminal, through the seventh resistor to the positive voltage terminal, and the ninth output input and output bus, the second input of the first multiplexer of the third quadruple dual-input multiplexer with memory is connected to the second input of the second converter from BCD to code one of ten, to the first data output and to the first data input of the third bidirectional inverting bus driver; connection, the first input of the second multiplexer of the third quadruple two-input multiplexer with memory is connected both through the sixth resistor to the zero voltage terminal, through the fifth resistor to the positive voltage terminal, and to the tenth output I / O bus. the memory is connected to the third input of the second converter from the BCD code to the code of one in ten, to the second data output and to the second data input of the third bidirectional inverting bus driver and simultaneously form the tenth wiring input, the first input of the third multiplexer of the third quadruple two-input multiplexer with memory is connected through the fourth resistor to the neutral terminal, through the third resistor to the positive voltage terminal, and to the eleventh input and output bus, second input of the third multiplexer third quadruple two-input the memory multiplexer is connected to the third data output and to the third data input of the third bidirectional inverting bus driver and constitutes simultaneously the eleventh wiring input, the first fourth multiplexer input of the third quadruple dual input memory multiplexer is connected via a second resistor to the neutral terminal resistance to the positive voltage terminal, first to the twelfth input and output bus, the second input of the fourth multiplexer of the third quadruple dual-input multiplexer-with memory is connected to the fourth data output and to the fourth data input of the third bidirectional inverting bus driver and simultaneously form the twelfth wiring input, the first inputs of the first to fourth multiplexers of the fourth quadruple dual-input memory multiplexer are connected via a thirty-third resistor to the positive voltage terminal; the quadruple dual-input memory multiplexer is connected to the first data output and to the first data input of the fourth bidirectional inverting bus driver and also forms the thirteenth wiring input, the second input of the second quadruple dual input multiplexer is connected to the second data output and the second data input bi-directional inverting bus driver and simultaneously form the fourteenth wiring input, the second input of the third multiplexer of the fourth quadruple dual input The memory multiplexer is connected to the third data output and the third data input of the fourth bidirectional inverting bus driver and simultaneously forms the fifteenth wiring input, the second fourth multiplexer input of the fourth quadruple dual input memory multiplexer is connected to the fourth data output and the fourth data input of the fourth bidirectional the input inputs of the first to fourth quadruple dual-input memory multiplexer are connected to the positive voltage terminal, while their ground inputs are connected to the neutral voltage terminal, the first multiplexer output of the first quadruple dual-input memory multiplexer is connected to the input of the first inverter and at the same time form the first wiring output, the output of the second multiplexer of the first quadruple dual-input multiplexer with memory is connected to the input of the second inverter and simultaneously forming the second wiring output, output of the third multiplexer of the first quadruple. two-input memory multiplexer connected to the input of the third inverter and simultaneously forming the third wiring output and simultaneously form the fourth wiring output, the first multiplexer output of the second quadruple two-input memory multiplexer is connected to the fifth inverter input and simultaneously form the fifth wiring output, the second multiplexer output of the second quadruple two-input memory multiplexer is connected to the sixth inverter input and wiring output, third mul tiplexer output of the second quadruple dual-input multiplexer with memory is connected to the input of the seventh inverter and forms simultaneously the seventh wiring output, the fourth multiplexer output of the second quadruple two-input memory multiplexer is connected to the eighth inverter input and simultaneously forms the eighth wiring output, the first multiplexer output of the third quadruple two-input memory multiplexer is connected to the ninth inverter input the third quadruple dual-input multiplexer with memory is connected to the input of the tenth inverter and simultaneously forms the tenth wiring output, the third multiplexer output of the third quadruple two-input multiplexer with memory is connected to the the memory is connected to the input of the twelfth inverter and simultaneously forms the twelfth output of the wiring, the output of the first The fourth quadruple dual-input multiplexer with memory is connected to the input of the thirteenth inverter and forms simultaneously the thirteenth wiring output, the second multiplexer output of the fourth quadruple two-input multiplexer with memory is connected to the input of the fourteenth inverter. s memory is connected to the input of the fifteenth inverter and simultaneously forms the fifteenth output of the circuit, the output of the fourth multiplexer of the fourth quadruple two-input multiplexer with memory is connected to the input of the sixteenth inverter the output of the second inverter is connected to the second input and output bus, the output of the third inverter is connected to the third input and output bus input, fourth inverter output is connected to input and output bus fourth input, fifth inverter output is connected to input and output bus fifth input, sixth inverter output is connected to input and output bus sixth input, seventh inverter output is connected to the seventh input and output bus input, the eighth inverter output is connected to the eighth input and output bus input, the ninth inverter output is connected to the input and output bus ninth input, the tenth inverter output is connected to the input and output bus tenth input, the eleventh inverter output is connected to the eleventh input and output bus input, the output of the twelfth inverter is connected to the twelfth input and output stage of the bus, the output of the thirteenth inverter is connected to the third eleventh input and output bus, the output of the fourteenth in * ve rtor is connected to the fourteenth input and output bus input, the fifteenth inverter output is connected to the fifteenth input and output bus input, the sixteenth inverter output is connected to the sixteenth input and output bus input, power inputs of the first to fourth bidirectional inverting bus driver are connected to terminal the first input and output data terminals of the first bidirectional inverting bus driver are connected to the first input and output bus terminals, the second input and output data terminals of the first bidirectional inverting bus driver is connected to the second input / output bus terminal, the third input / output terminal of the first bidirectional inverting bus driver is connected to the third input / output terminal The first bidirectional inverting bus driver data input terminal is connected to the input / output bus fourth input and output terminal, the second bidirectional inverting bus driver data input terminal is connected to the fifth input / output terminal bus, the second input and output data terminal of the second bidirectional inverting bus driver is connected to the sixth input and output terminal of the input and output bus, the third data input and output terminal of the second bidirectional inverting bus driver is connected to the seventh input and output terminal of the output bus, the fourth input and output data terminal of the second bidirectional inverting bus driver is connected to the eight input and output bus input and output terminals, the first input and output terminal pu and the data output of the third bidirectional inverting driver the bus is connected to the ninth input / output bus terminal, the second input / output data terminal of the third bidirectional inverting bus driver is connected to the tenth input / output bus terminal, the third data input / output terminal of the third bidirectional inverting bus driver is connected to the eleventh input and output bus terminal, the fourth input and output terminal 8 of the third bidirectional inverting bus driver is connected to the twelfth input and output bus terminal, the first data input and output terminal of the fourth bidirectional inverting bus driver is connected to the thirteenth input and output bus terminal, the second input and output data terminal of the fourth bidirectional inverting bus driver is connected to the fourteenth input and output terminal of the input and output bus ce, the fourth input and output bus driver data input and output terminal is connected to the fifteenth input and output bus input terminal, the fourth input and output bus driver data input and output terminal is connected to the 16th input and output bus input terminal , the eight-channel multiplexer power input for the view function is connected to the positive voltage terminal, while its ground input is connected to the zero voltage terminal and its trip input to the zero voltage terminal, the one-way eight-channel multiplexer for the view function is connected to the first flip type D circuit, whose one output is connected to the second input of the first four-input total product gate and whose zero output is connected to the third input of the first four-input total product gate, the first output p The first output from the BCD to one in ten code is connected to the first input of the first three-input logic product negation circuit and to the input of the eighteenth inverter whose output is connected to the fourth input of the second four-input summation gate. code one of ten is connected to the input of the twenty-first inverter whose output is connected to the second input of the twenty-two logic product negation circuit, the third output of the first converter from BCD to code one of ten is connected to the input of the nineteenth inverter whose output is connected to the second input of the seventeenth two-input logical product negation circuit and to the second input of the twenty-first two-input logical product negation circuit, the fourth output of the first BCD to one in ten converter is connected to the twenty inverter input whose output is connected to the second input of the twelfth two-input logical product negation circuit and to the second input of the fourteenth two-input logical product negation circuit, the fifth output of the first BCD to one in ten converter is connected to the first input of the second three-input ¹ the logic product negation circuit, the output of which is connected to the second input of the sixth two-input logic product negation circuit, the seventh output of the first BCD to one in ten code converter is connected to the third inputs of the first and second three-input logic product negation circuit input of the fourth two-input logic product negation circuit whose output is connected to the second input of the tenth two-input logic product negation circuit and to the second input of the ninth two-input logical product negation circuit, the eighth output of the first BCD to one in ten converter the second input of the fourth two-input logic product negation circuit, the second input of the second three-input logic product negation circuit, and the second input of the first three-input logical product negation circuit, the output of which is connected to the second input of the fifth logic product negation circuit, to the second input of the second four-input summation gate and to the second input of the third four-summation gate, the tenth output of the first converter from BCD to one in ten is connected to the input of the 22nd inverter whose output is connected to the second input of the eighteenth two-input logic product negation circuit and the second input of the nineteenth two-input logic product negation circuit, the power inputs of the first and second converters from BCD to one in ten are connected to the positive voltage terminal while their ground inputs are connected to terminal the first output of the second converter from the BCD code. to code one in ten is connected to the input of the twenty-third inverter whose output is connected to the first input of the seventeenth two-input circuit of the negation of the logical product, the second output d the BCD to one in ten code converter is connected to the 24th inverter input whose output is connected to the first input of the fifth two-input logic product negation circuit and the first input of the tenth two-input logic product negation circuit, the third output of the second converter from the code BCD to code one in ten is connected to the first input of the first four-input sum product gateway, whose output is also the twenty-first wiring output, the fourth output of the second converter from BCD to code one of ten is connected to the fourth input of the first four input summation gate. the output of the second converter from BCD to code one in ten is connected to the first input of the third 10 th three-input logic product negation circuit, the output of which is connected to the third input of the second four-input summation gate, the sixth output of the second the BCD to one in ten code converter is connected to the second input of the third * 3-input logic product negation circuit, the seventh output of the second BCD to one in ten code converter is connected to the third input of the third three-input logic product negation circuit , the eighth output of the second converter from BCD to code one of ten is connected to the input of the twenty-fifth inverter whose output is connected to the first input of the second four-input summation gate, to the first input of the twelfth two-input logic product negation circuit and the first input of the twenty-first two-input logic product negation circuit, the twenty-ninth inverter input is connected to the fourth data input of the eight-channel multiplexer for the view function, the twenty-seventh input and output bus inputs the output of the 27th inverter is connected to the first input of the seventh two-input circuit of the negation of the logical product whose output is connected to the first-input of the ninth three-input circuit of the negation of the logical product, the input of the 26th inverter is connected twenty-seventh resistor to positive voltage terminal, both through twenty-eight resistor to zero voltage terminal, and thirteenth input and output bus output, twenty-sixth inverter output is connected to the first input of the twenty-second two-input logic product negation circuit and to the second input of the ninth three-input the logic product negation circuit, the output of which is also the twentieth output of the circuit, the output of the fifth two-input logic product negation circuit is connected to the first input of the fourth three-input logic negation circuit the output of which is connected to the sixth input of the eight-channel multiplexer for the view function, to the second input of the seventh two-input logic product negation circuit, and to the first input of the fifth three-input logic negation circuit ¹ product, the output of the sixth two-input circuit is connected to the third input of the fifth three-input circuit of the negation of the logical product, the output of which is connected to the third input of the fourth three-input circuit of the negation of the logical product and to the input of the thirty inverter bus, the second input of the sixth three-input logic product negation circuit simultaneously forms the twenty-fifth input wiring, the output of the sixth three-input logic product negation circuit is connected to the second input of the Fourth three-input logical product negation circuit whose output is connected to the second input of the twenty-second two-input circuit of the negation of the logical product, the output of the twenty-second two-input circuit of the negation of the logical product is connected to the first The input of the eighth two-input logic product negation circuit and the third input of the ninth three-input logic product negation circuit, the output of the second four-input sum gate product is connected to the setting input of the second D-type flip-flop. The D input of the second D-type flip-flop is connected to the zero-voltage terminal, while its zero output is connected to the thirty-first inverter input whose output is connected to the twentieth the first input of the input and output bus, the input of the 27th inverter is connected to the second input of the seventh three-input circuit of the negation of the logical product, to the second input of the fifth three-input circuit of the negation of the logical product of the sixth input of the I / O bus and the 30th input of the wiring, the 27th inverter output is connected to the third and fourth inputs of the third four-input summation gate, the output of which is connected to the zero input of the second D-type flip-flop the logical product is connected to the first input of the eleventh two-input logic product negation circuit, the output of which is connected to the second trigger input of the first monostable flip-flop, the second input of the eleventh two-input logical product negation circuit is connected via the twenty-ninth resistor to the positive voltage terminal across the thirty resistor to the zero voltage terminal and simultaneously form the nineteenth wiring input, the first trigger inputs of the first and second monostable flip-flop are connected to the zero voltage terminal, n The first output of the first monostable flip-flop circuit. is connected to the second input of the second 2-input logic product negation circuit and to the second trigger input of the second monostable flip-flop whose zero output is connected to the clock input of the second flip-flop type D between the external capacity input and external resistance input and first capacitance input a monostable flip-flop is connected with a second capacitor and a thirty-first resistor is connected between its input for external resistance and capacitance and an external resistor input, a first capacitor is connected between its external capacitance input and an external resistor input and capacitance external resistance and capacitance input and external resistance input is connected to the thirty-second resistor, the output of the twelfth two-input logic product negation circuit is connected to the first input of the thirteenth two-input logic product negation circuit whose output is connected to the thirty-second input the output of the thirty-second inverter is connected to the twenty-second input and output bus input, the output of the fourteenth two-input circuit of the negation of the logical product type is connected to the third input of the seventh three-input circuit of the negation of the logical product type. the output is connected to the second input of the thirteenth two-input circuit of the negation of the logical product, the data input of the third flip-flop type D simultaneously forms the 28th wiring input, the one output of the third flip-flop type D is connected to the thirty-third inverter input whose output is connected to the seventeenth input input and output bus, zero output of the third D type flip-flop is connected to inputs for selecting the first to fourth bidirectional inverting bus driver circuits, data input of the fourth type D flip-flop simultaneously form the 27th wiring input, the one-way output of the fourth D-type flip-flop is connected to the 3-way flow control inputs of the first to fourth bidirectional inverting bus drivers and forms the seventeenth wiring output; an inverter whose output is connected to the eighteenth input and output bus input, the output of the 17th two-input logic product negation circuit is connected to the twenty-third input and output bus input, the first input of the fifteenth two-input logic product negation circuit is connected to the first input of the eighth three-input circuit logic product negation, on the first input of the sixteenth two-input circuit logic product negation, on the first input of the sixth three-input logic product type the first wiring input, the second input of the fifteenth two-input logic product negation circuit simultaneously forms the twenty-fourth wiring input, the output of the fifteenth two-input logic product negation circuit is connected to the data input of the fifth D-type flip-flop the output of which is connected to the nineteenth input and output bus input, the second input of the eighth three-input circuit simultaneously forms the twenty-third wiring input, the output of the eighth three-input logic product negation type is connected to the data input of the sixth type D flip-flop first input of the sixth two-input logic product negation circuit, to the first input of the twelfth two-input logic product negation circuit, to the first input of the twenty-two logical product negation circuit input, to the first The input of the fourteenth two-input logic product negation circuit, the first input of the third four-input logic product negation circuit and the first input of the ninth two-input logical product negation circuit, the output of which is connected to the second input of the first two-input logical product negation circuit. the logic product negation circuit simultaneously forms the twenty-second wiring input, the output of the sixteenth logic product negation two-input circuit is connected to the data input of the seventh D-type flip-flop whose one output is connected to the fourth input of the second converter from BCD to one of ten the twenty-eighth inverter input is the twenty-sixth input wiring, the twenty-eighth inverter output is connected to the clock inputs of the third to seventh D-type flip-flop, the eighteenth two-input circuit output logic product negation type is connected to the twenty-fourth input and output bus input, the output of the nineteenth two-input logic product negation circuit is connected to the twenty-fifth input and output bus input, the twenty-two logical product negation type output The first two-input logic product negation circuit also forms the nineteenth wiring output.

By connecting the input and output control circuits, in particular for the intelligent terminal according to the invention, it is achieved that while maintaining or improving the functional properties, the connection is substantially simplified, the number of logic elements is reduced, the cost is reduced and maintenance of the whole device is simplified. This is accomplished in that all control functions of the internal and external peripheral devices are performed by means of common circuits controlled from the processor control memory or its arithmetic and logic unit, thus maximizing the simplification of all wiring circuits.

An example of the connection of the input and output control circuits, especially for the intelligent terminal according to the invention, is shown in the attached drawings, in which Fig. 1 represents a block diagram, Figs 2a to 2e diagram of the input and output control circuits. Figure 4 shows a time source time diagram.

The first input of the third two-input logic product negation circuit 158 for the TC signal is connected to the third input of the sixth three-input logic product negation circuit 182, to the clock inputs 289, 336 of the first and eightth flip-flop 112, 334 wiring for connection to a processor controller not shown. The second input of the third dual-input logic-type negation circuit 158 for the OUT signal is connected to the data input 335 of the eight-way D-type flip-flop 334 whose one output is connected to inputs 70, 82, 94, 228 to select the first to fourth quadruple two-input multiplexer 101 to 104 with memory and at the same time form the 17th wiring input 17 for connection to the processor controller. The output of the third two-input logic product negation circuit 158 is connected to the first input of the second two-input logic product negation circuit 157 and to the first input of the first two-input logical product negation circuit 156 whose output is connected to the clock input 226 of the fourth quadruple dual-input multiplexer 104 The output of the second dual-input logic-type negation circuit 157 is connected to the clock inputs 68, 80, 92 of the first to third quadruple dual-input multiplexer 101-103 with memory. The first input 60 of the first multiplexer of the first quadruple two-input multiplexer 101 with the memory for the signal ((0) is connected via the twenty-fourth resistor 211 to the neutral voltage terminal 330 and the twenty-third resistor 210 to the positive voltage terminal 329 The second input 61 of the first multiplexer of the first quadruple dual-input multiplexer 101 with the memory for the DC signal is connected to the first data output 063 and to the first data input 231 of the first bidirectional inverting bus driver 105. arithmetic and logic unit (not shown). The first input 62 of the second multiplexer of the first quadruple dual-input multiplexer 101 with the memory for signal E (1) is connected via the twenty-second resistor 209 to the neutral voltage terminal 330, through the twenty-first resistor 208 to the positive voltage terminal 329 and and the output bus 333 ' The second input 63 of the second multiplexer of the first quadruple dual-input multiplexer 101 with the memory D ' is connected to the third input of the eighth three-input logic product negation circuit 184, the second data output 064 and the second data input 232 of the first bidirectional inverting driver 105 the bus and form a second wiring input 2 for connection to an arithmetic and logic unit. The first input 64 of the third multie plexer of the first quadruple two-input multiplexer 101 with memory for the signal E (?) Is connected via a resistor 207 to a neutral voltage terminal 330, a nineteenth resistor 206 to a positive voltage terminal 329 The second input 65 of the third multiplexer of the first quadruple dual-input multiplexer 101 with memory for the Ϊ52 signal is connected to the third data output 065 and to the third data input 233 of the first bidirectional inverting bus driver 105. and a logical drive. The first input 66 of the fourth multiplexer of the first quadruple dual input multiplexer 101 with the memory for signal E '(3) is connected via the 18th resistor 205 to the neutral voltage terminal 330, through the 17th resistor 204 to the positive voltage terminal 329 and The second input 67 of the fourth multiplexer 67 of the first quadruple dual-input multiplexer 101 with memory for signal D1 is connected to the third address input 272 of the eight-channel multiplexer 109 for the data selection function, to the first input 276 of the first converter 110 from BCD to one of ten. to the fourth data output 066 and to the fourth data input 234 of the first bidirectional inverting bus driver 105 and at the same time form the fourth wiring input 6 for connection to the arithmetic and logic unit. The first input 72 of the first multiplexer of the second quadruple two-input multiplexer 102 with the memory for the signal E (4) is connected via a 16th resistor 203 to an opium voltage terminal 330, through a 15th resistor 202 to a positive voltage terminal 329 and output bus 333 ' The second input 73 of the first multiplexer of the second quadruple dual-input multiplexer 102 with memory for signal D4 is connected to the second addressing input 271 of the eight-channel multiplexer 109 for data selection function; to the first data output 067 and to the first data input 239 of the second bidirectional inverting bus driver 106 and at the same time form a fifth wiring input 2 for connection to an arithmetic and logic unit. The first input 74 of the second multiplexer of the second quadruple two-input multiplexer 102 with memory for the signal E (5) is connected via the 14th resistor 201 to the neutral voltage terminal 330, through the 13th resistor 200 to the positive voltage terminal 329 The second input 75 of the second multiplexer of the second quadruple two-input multiplexer 102 with memory for the D5 signal is connected to the first address input 270 of the eight-channel multiplexer 109 for the data function, to the third input 278 of the first converter 110 from BCD to one of ten the second data output 068 and the second data input 240 of the second bidirectional inverting bus driver 106 and simultaneously form the sixth wiring input for connection to the arithmetic and logic unit. The first input 76 of the third multiplexer of the second quadruple two-input multiplexer 102 with the memory for the signal E (δ) is connected both via the twelfth resistor 199 to the neutral voltage terminal 330 and through the eleventh resistor 198 to the positive voltage terminal 329 and to the seventh output

028 input and output bus 333 «The second input 77 of the third multiplexer of the second quadruple two-input multiplexer 102 with the memory for the D6 signal is connected to the fourth input 279 of the first converter 110 from BCD'to one of ten; the input 241 of the second bidirectional inverting bus driver 106 and at the same time forms the seventh wiring input for connection to the arithmetic and logic unit. The first input 78 of the fourth multiplexer of the second quadruple two-input multiplexer 102 with the memory for signal E (7) is connected via the tenth resistor 197 to the neutral voltage terminal 330, through the ninth resistor 196 to the positive voltage terminal 329 output bus 333 »The second input 79 of the fourth multiplexer of the second quadruple two-input multiplexer 102 with memory for the signal D7 is connected to the first input 282 of the second converter 111 from BCD to code one of ten, to the fourth data output 070 and to the fourth data input 242 of the second bidirectional the inverting bus driver 106 and at the same time forms the eighth wiring input 8 for connection to the arithmetic and logic unit. The first input 84 of the first multiplexer of the third quadruple dual-input multiplexer 103 with memory for the signal E (8) is connected via the seventeenth inverter 137 to the first data input 262 of the 8-channel data multiplexer 109 via the seventh resistor 194 to the positive voltage terminal 329 and to the ninth output 030 of the input and output bus 333. The second-input 85 of the first multiplexer of the third quadruple dual-input multiplexer 103 with D8 memory is connected to the second input 283 of the second converter 111 code one of ten, to the first data output 071 and to the first data input 246 of the third bidirectional inverting bus driver 107, and simultaneously forms the ninth input 9 for connection to the arithmetic and logic unit. The first input 86 of the second multiplexer of the third quadruple two-input multiplexer 103 with the memory for the signal E (9) is connected both via the sixth resistor 193 to the neutral voltage terminal 330 and the fifth resistor 192 to the positive voltage terminal 329 The second input 87 of the second multiplexer of the third quadruple two-input multiplexer 103 with memory for the signal D ^ is connected to the third input 284 of the second converter 111 from the BCD code to one of ten, to the second data output 072 and to the second data input 247 inverting bus driver 107 and simultaneously form the tenth input 10 for connection to the arithmetic and logic unit. The first input 88 of the third multiplexer of the third quadruple dual input multiplexer 103 8 of the memory for signal E (10) is connected via the fourth resistor 191 to the neutral voltage terminal 330, through the third resistor 190 to the positive voltage terminal 329 and to the eleventh output 032 The second input 89 of the third multiplexer of the third quadruple dual-input multiplexer 103 with the memory for the D10 signal is connected to the third data output 073 and to the third data input 248 of the third bidirectional inverting bus driver 107 and constituting simultaneously the eleventh wiring input 11 for connection to arithmetic and logic unit. The first input 90 of the fourth multiplexer of the third quadruple two-input multiplexer 103 and the memory for the signal ΤΪΪΤΪΪ7 are connected via the second resistor 189 to the neutral voltage terminal 330, through the first resistor 188 to the positive voltage terminal 329 and to the twelfth output 033 of the input and output bus 333. The second input 91 of the fourth multiplexer of the third quadruple two-input multiplexer 103 with memory for the signal D1 is connected to the fourth data output 074 and the fourth data input 249 of the third bidirectional inverting bus driver 107 and constitutes simultaneously the twelfth wiring input 12 for connection to the arithmetic and logic unit. The first inputs 96, 98, 100, 224 of the first to fourth multiplexers of the fourth quadruple dual-input memory multiplexer 104 are connected through the thirty-third resistor 220 to the positive voltage terminal 329. The second input 97 of the first multiplexer of the fourth quadruple dual-input multiplexer 104 with the memory for the signal D1? it is coupled to the first data output 075 and to the first data input 255 of the fourth bidirectional inverting bus driver 108 and simultaneously forms the thirteenth wiring input 13 for connection to the arithmetic and logic unit. The second input 99 of the second multiplexer of the fourth quadruple two-input multiplexer 104 with the memory for the signal D1? It is connected to the second data output 076 and to the second data input 256 of the fourth bidirectional inverting bus driver 108 and simultaneously forms the fourteenth wiring input 14 for connection to the arithmetic and logic unit. The second third multiplexer input 223 of the fourth quadruple two-input multiplexer 104 with memory for the D14 signal is coupled to the third data output 077 and the third data input 257 of the fourth bidirectional inverting bus driver 108 and forms the fifteenth wiring input 15 for connection to the arithmetic and logic unit. The fourth fourth multiplexer input 225 of the fourth quadruple two-input multiplexer IO4 with signal memory is connected to the fourth data output 078 and the fourth data input 258 of the fourth bidirectional inverting bus driver 108 and forms the 16th input 16 for connection to the arithmetic and logic unit. Power Inputs 71, 83, 95 »

The first to fourth quadruple dual-input memory multiplexers 101 to 104 with memory are connected to the positive voltage terminal 329, while their ground inputs 69, 81, 93, 227 are connected to the zero voltage terminal 330. The output 047 of the first multiplexer 19 of the first quadruple dual-input multiplexer 101 with memory for the T0 signal is connected to the input of the first inverter 121 and at the same time forms the first output 01 of the circuitry for connection to the arithmetic and logic unit. The second multiplexer output 048 of the first quadruple two-input multiplexer 101 with memory for the signal T1 is connected to the input of the second inverter 122 and at the same time forms the second circuit output 02 for connection to the arithmetic and logic unit. The third multiplexer output 049 of the first quadruple two-input multiplexer 101 with memory for the signal ΤΣ is coupled to the input of the third inverter 123 and simultaneously forms the third output 03 of the circuitry for connection to the arithmetic and logic unit. The fourth multiplexer output 050 of the first quadruple dual-input multiplexer 101 with TT memory is connected to the fourth inverter input

124 and simultaneously form the fourth wiring output 04 for connection to the arithmetic and logic unit. The output 051 of the first multiplexer of the second quadruple dual-input multiplexer 102 with the memory for the signal 14 is connected to the input of the fifth inverter

125 and simultaneously form the fifth output 05 for connection to the arithmetic and logic unit. The second multiplexer output 052 of the second quadruple two-input multiplexer 102 with memory for signal 15 is connected to the input of the sixth inverter 126 and simultaneously forms the sixth output 06 of the wiring for connection to the arithmetic and logic unit. The third multiplexer output 053 of the second quadruple two-input multiplexer 102 with memory for the signal Ύζ is connected to the input of the seventh inverter 127 and simultaneously forms the seventh output 07 of the wiring for connection to the arithmetic and logic unit. The fourth multiplexer output 054 of the second quadruple two-input multiplexer 102 with memory for the TT signal is connected to the input of the eighth inverter 128 and simultaneously forms the eighth output 08 of the wiring for connection to the arithmetic and logic unit. The output 055 of the first multiplexer of the third quadruple two-input multiplexer 103 with memory for the T0 signal is connected to the input of the ninth inverter 129 and simultaneously forms the ninth output 09 of the circuit for connection to the arithmetic and logic unit. The second multiplexer output 056 of the third quadruple two-input multiplexer 103 with memory for the Ϊ9 signal is connected to the input of the tenth inverter 130 and simultaneously forms the tenth output 010 of the circuitry for connection to the arithmetic and logic unit. The third multiplexer output 057 of the third quadruple multiplexer 103 with signal memory 110 is connected to the input of the eleventh inverter 131 and simultaneously forms the eleventh circuit output 011 for connection to the arithmetic and logic unit. The fourth multiplexer output 058 of both the third and quadruple dual-input multiplexer 103 with memory for the signal ΙΪ1 is connected to the input of the twelfth inverter 132 and forms the twelfth output 012 of the circuit for connection to the arithmetic and logic unit. The first multiplexer output 059 of the fourth quadruple two-input multiplexer 104 with memory for the signal ΙΪ2 is connected to the input of the thirteenth inverter 133 and simultaneously forms the thirteenth wiring output 013 for connection to the arithmetic and logic unit. The output 060 of the second multiplexer of the fourth quadruple two-input multiplexer 104 with memory for the signal ΧΪ3 is connected to the input of the fourteenth inverter. 134 and simultaneously form the fourteenth wiring output 014 for connection to the arithmetic and logic unit. The third multiplexer output 061 of the fourth quadruple two-input multiplexer 104 and the memory for the signal ΪΪ4 are connected to the input of the fifteenth inverter 135 ^and simultaneously form the fifteenth output 015 of the circuit for connection to the arithmetic and logic unit. The fourth multiplexer output 062 of the fourth quadruple two-input multiplexer 104 with memory for the signal ΪΪ5 is connected to the input of the sixteenth inverter 136 and simultaneously forms the sixteenth output 016 of the wiring for connection to the arithmetic and logic unit. The output of the first inverter 121 for the signal V (0) is connected to the first input 31 of the input and output bus 333. The output of the second inverter 122 for the signal V (1) is connected to the second input 32 of the input and output bus 333. V (2) is connected to third input 33 of output and output bus 333. Output of fourth inverter 124 for signal V (3) is connected to fourth input 34 of input and output bus 333. Output of fifth inverter 125 for signal V (4) is connected to the fifth input and output bus 333. The output of the sixth inverter 126 for the V signal (5) is connected to the sixth input 36 of the input and output bus 333. The output of the seventh inverter 127 for the V signal (6) is connected to the seventh input 37 The output of the eighth inverter 128 for the V signal (7) is connected to the eighth input 38 of the input and output bus 333. The output of the ninth inverter 129 for the V signal (8) is at connected to the ninth input 39 of the input and output bus 333. The output of the tenth inverter 130 for the V signal (9) is connected to the tenth input 40 of the input and output bus 333. The output of the eleventh inverter

131 for signal V (10) is connected to eleventh input 41 of output and output bus 333. Output of twelfth inverter 132 for signal V (11) is connected to twelfth input 42 of input and output bus 333. Output of thirteenth inverter 133 for signal V (12) ) is connected to thirteenth input 43 of output and output bus 333. Output of fourteenth inverter 134 for V signal (13) is connected to fourteenth input 44 of input and output bus 333. Output of fifteenth inverter 135 for V signal (14) is connected to fifteenth input The output of the 16th inverter 136 for the V signal (15) is connected to the 16th input 46 of the input and output bus 333. The power inputs 235, 243. 250, 259 of the first to fourth bidirectional inverting drivers 105 and 108 are connected. to the positive voltage terminal 329, while their grounding inputs 237. 245. 252,

261 are connected to the zero voltage terminal 330. First clamp

307 of the input and output data of the first bidirectional inverting fieldbus driver 105 for the EXT (O) signal is connected to the 035 input and output bus input and output terminal 333 «Second terminal

The data input and output terminal 308 of the first bidirectional inverting bus driver 105 for the EXT signal (l) is connected to the second input and output bus terminal 036 of the input and output bus 333. The third data input and output terminal 309 of the first bidirectional inverting bus driver 105 for the EXT signal 4) is connected to the third I / O terminal 037 of the I / O bus 333. The fourth I / O data terminal 310 of the first bidirectional inverting bus driver 105 for the EXT signal (3) is connected to the fourth I / O terminal 038 of the I / O bus 333. The first data input and output terminal 311 of the second bidirectional inverting bus driver 106 for the EXT signal (4) is connected to the fifth input and output terminal 039 of the input and output bus 333. (5) is connected to the sixth input terminal 040 The third input and output data terminal 313 of the second bidirectional inverting bus driver 106 for the EXT signal (6) is connected to the seventh input and output bus terminal 041. The fourth input and output terminal 314 of the second the bi-directional inverting bus driver 106 for the EXT signal (7) is connected to the eight input and output I / O bus terminals 333. The first input and output data terminal 315 of the third bi-directional inverting bus driver 107 for the EXT signal (8) is connected. to the ninth input / output bus terminal 043. The second input / output data terminal 316 of the third bidirectional inverting bus driver 107 for the EXT signal (9) is connected to the tenth input / output bus terminal 044. third terminal 317 data input and output of the third bidirectional inverting driver 107 s The EXT signal box (10) is connected to the 11th I / O terminal 333 of the I / O bus 333 »The fourth input and output data terminal 318 of the third bidirectional inverting bus driver 107 for the EXT signal (11) is connected to the 12th I / O terminal 046 input and output bus 333 »The first input and output data terminal 319 of the fourth bidirectional inverting driver 108 for the EXT signal (12) is connected to the thirteenth input and output terminal 047 of the input and output bus 333» the bus driver 108 for the EXT signal (13) is connected to the fourteenth input and output terminal 048 of the input and output bus 333. The third input and output data terminal 321 of the fourth bidirectional inverting bus driver 108 for the EXT signal (14) is connected to the fifteenth terminal 049 and output and output bus 33 3 »The fourth input and output data terminal 322 of the fourth bidirectional inverting bus driver 108 for the EXT signal (15) is connected to the sixteenth input and output bus terminal 050 333. The power input 275 of the eight-channel multiplexer 109 for data selection is connected to the terminal. 329 of the positive voltage, while its ground input 274 is connected to the neutral voltage terminal 330 and its trip input 273 to the zero voltage terminal 330. The one output 079 of the eight-channel data multiplexer 109 is coupled to data input 288 of the first D-type flip-flop 112, whose one output 096 is coupled to the second input of the first four-input sum gate product 185 and zero output 097 is connected to the third input of the first four input. The first output 080 of the first converter 110 from BOD to code one in ten is connected to the first input of the first three-input logic product type 177 and to the input of the eighteenth inverter 138 whose output for the XO signal is connected to the fourth input of the second a four-input total product gate 186. The second output 081 of the first converter 110 from the BCD code to the one in ten code is connected to the input of the twenty-first inverter

1411 whose output for signal XI is connected to the second input of the twenty-two logic product negation circuit 175. The third output 082 of the first BCD to one in ten converter 110 is connected to the input of the nineteenth inverter 139, whose output for the X2 signal is connected to the second input of the 17th input logic negation circuit 172 and the second input of the 21st type negation of a logical product. The fourth output 083 of the first BCD to one in ten converter 110 is connected to the input of the twenty inverter 140 whose output for the X3 signal is connected to the second input of the twelve logic product negation circuit 167 and the second input of the fourteenth negation circuit 169 input. logical product. The fifth output 084 of the first BCD to one in ten converter 110 is connected to the first input of the second three-input logic product negation circuit 178, whose output for the X467 signal is connected to the second input of the sixth logic product negation circuit 161. The seventh output 085 of the first BCD to one in ten converter 110 is connected to the third inputs of the first and second three-input logic product negation circuits 177 &apos; and to the first input of the fourth two input logic product negation circuit 159 whose X67 signal output is connected to the second input of the tenth two-input logic product negation circuit 165 and to the second input of the ninth two-input logic product negation circuit 164. The 086 output of the first BCD to one in ten converter 086 is connected to the second input of the fourth two-input logic product negation circuit 159, the second input of the second three-input logic product negation circuit 178 and the second input of the first three-input logic negation circuit 177 a product whose output for the X067 signal is connected to the second input of the fifth two-input logic product negation circuit 160, to the second input of the second four-input sum gate product 186 and to the second input of the third four-input sum gate product 187. to code one of ten is connected to the input of the twenty-second inverter 142 ₁ whose output for the X9 signal is connected to the second input of the eighteenth two-input logic product negation circuit 173 and to the second input of the nineteenth two-input logic negation circuit 174 product. The power inputs 280, 286 of the first and second transducers 110, 111 from BCD code to code one of ten are connected to the positive voltage terminal 329, while their ground inputs 281, 287 are connected to the zero voltage terminal 330. The first output 088 of the second converter 111 from the BGD code to the code one of ten is connected to the input of the twenty-third inverter 143, whose output for the CLC signal is connected to the first input of the 17th logic product negation circuit 172. The second output 089 of the second converter 111 from BOD to one in ten is connected to the input of the twenty-fourth inverter 144. whose output for the STF signal is connected to the first input of the fifth two-input logic product negation 160 and the first input of the tenth two-input negation of a logical product. The third output 090 of the second transducer 111 from BCD code to code one of ten for the SFC signal is connected to the first input of the first four-input sum gate product 185, whose output for the 10F signal simultaneously forms the twenty-first wiring output 021 for connection to the processor controller. The fourth output 091 of the second converter 111 from BCD to code one of ten for the SFS signal is connected to the fourth input of the first four-input sum gate product 185. The fifth output 092 of the second converter 111 from BCD to code one of ten is connected to the first input of the third three-input The logic product negation circuit 179 whose output for the MLO signal is connected to the third input of the second four-input summation gate 186. The sixth output 093 of the second B11 to code one of ten is connected to the second input of the third logic negation circuit 179 product. The seventh output 094 of the second transducer 111 from the BCD code to the code one of ten is connected to the third input of the third three-input logic-type negation circuit 179. The eighth output 095 of the second converter 111 from BCD to code one of ten is connected to the input of the twenty-fifth inverter 145. whose output for the STC signal is connected to the first input of the second four-input summation gate product 186, to the first input of the twelfth to the first input of the eighteenth two-input logic product negation circuit 173 and to the first input of the twenty-first two-input logic product negation circuit 176. The input of the twenty-ninth inverter 149 for the KSTOP signal is connected to the fourth data input 265 of the eight-channel multiplexer 109 for the data selection function, the twenty-seventh input 57 of the input and output bus 333, and simultaneously the twenty-ninth wiring input 29 for connection to a keyboard (not shown). The output of the twenty-ninth inverter 149 is connected to the second. the input of the seventh two-input circuit 1624-33, the output of which is connected to the first input of the ninth three-input logic circuit type 264. V The input of the 26th inverter 146 for the P signal is connected via the 27th resistor 214 to the positive voltage terminal 329, through the 28th resistor 215 to the zero voltage terminal 330, and to the 13th output 034 of the input and output 3 bus 333 » the inverter 146 is connected to the first input of the twenty-second logic product negation circuit 266 and the second input of the nine-logical product negation circuit 264, whose output for the FRER signal simultaneously forms the twenty output 020 of the circuit for connection to the processor controller. The output of the fifth two-input logic product negation circuit 160 is connected to the first input of the fourth three-input logic product negation circuit 180 whose output for the PREB1 signal is connected to the sixth input 267 of the eight-channel data multiplexer 109 the negation of the logic product and the first input of the fifth three-input circuit 181 of the negation of the logic product. The output of the sixth two-input circuit 161 is connected to the third input of the fifth three-input logic product negation circuit 181, the output of which is connected to the third input of the fourth three-input logic product negation circuit 180 and the thirty inverter 150 input. The second input of the sixth three-input logic product negation circuit 182 for the K1 signal simultaneously forms the twenty-fifth wiring input 25 for connection to the processor controller. The output of the sixth three-input logic product negation circuit 182 is connected to the second input of the fourth three-input logic product negation circuit 180 and to the second input of the eighth two-input logical product negation circuit 163 whose output is connected to the second input of the twenty-second product. The output of the twenty-second two-input logic product negation circuit 266 is connected to the first input of the eighth two-input logic product negation circuit 163 and to the third input of the ninth three-input logical product negation circuit 264. The output of the second four-input cumulative gate 186 is connected to the setting input 269 of the second flip-flop 113 of type 0, whose one output 098 for the RBIT1 signal is connected to the second input 263 of the eight-channel multiplexer 109 for the data selection function. The seventh input 268 of the eight-channel multiplexer 109 for the SHIFT signal selection function simultaneously constitutes the twenty wiring input 20 for connection to a keyboard (not shown). The data input 290 of the second type D flip-flop 113 is connected to the neutral voltage terminal 330, while its neutral output 099 is connected to the input of the thirty-first inverter 151. whose output for the RBIT signal is connected to the twenty-first input 51 of the input and output bus 333. The 27th inverter 147 for the NUL signal is connected to the second input of the seventh three-input logic negation circuit 183, to the second input of the fifth three-input logic negation circuit 181, to the 26th input 56 of the input and output bus 333 < wiring for connection to processor controller. The output of the 27th inverter 147 is connected to the third and fourth inputs of the third four-input summation gate 187, the output of which is connected to the reset input 292 of the second D-type flip-flop 113. the logic product negation circuit 166, the output of which is connected to the second trigger input 304 of the first monostable flip-flop 119. The second input of the eleventh two-input logic product negation circuit 166 for the INPUT signal is connected via the twenty-ninth resistor 216 to the positive voltage terminal 329. across a thirty resistor 217 to the zero voltage terminal 330 and simultaneously form the nineteenth wiring input 19 for connection to a cassette tape memory (not shown). The first trigger inputs 303, 305 of the first and second monostable flip-flops 119 > 120 are connected to the zero voltage terminal 330. Zero output 0107 of first monostable flip-flop 119 is coupled for V011Š signal to second input of second two-input logic-type negation circuit 157 and second trigger input 306 of second monstable flip-flop 120, whose zero output 0108 is connected to clock input 291 of second flip-flop 113 type D.

A second capacitor 222 is connected between the external capacitance input 323 and the external resistor input 324 and the capacitance of the first monostable flip-flop 119, and the thirty-first resistor 218 is connected between its external resistor input and capacitance 324 and the external resistor input 325. for external capacity and input

327 for the external resistor and capacity of the second monostable flip-flop 120 is connected to the first capacitor 221 and thirty-second resistor 219 is connected between its input 327 for external resistance and capacity and input 328 for the external resistor 219. The output of the twelfth logical product negation type 167 is connected to the first input of the thirteenth two-input logic product negation circuit 168, whose output for the R03 signal is connected to the input of the thirty-second inverter 152, and to the first input of the seventh three-input logic product negation circuit 183. The output of the thirty-second inverter 152 for the ROJ signal is connected to the twenty-second input 52 of the input and output bus 333. The output of the fourteenth two-input logic negation circuit 169 is connected to the third input of the seventh three-input logic negation circuit 183 input of the thirteenth two-input logic product negation 168. The data input 293 of the third D-type flip-flop 114 for the CS signal simultaneously forms the 28th wiring input 28 for connection to the processor controller. The one-way output Q1QQ of the third D-type flip-flop 114 is connected to the input of the thirty-third inverter 153, whose output for the DMA signal is connected to the 17th input and output bus 333. inputs 230, 238, 253, 254 for selecting a circuit of the first to fourth bidirectional inverting drivers 105 to 108 of the bus. The data input 295 of the fourth D-type flip-flop 115 for the INP signal simultaneously forms the 27th wiring input 27 for connection to the processor controller. The one-way output 0102 of the fourth D-type flip-flop 115 for the ED signal is connected to the flow direction 236, 244, 251, 260 to control the data flow direction of the first to fourth bidirectional inverting fieldbus drivers 105-108. logical unit. Zero output 0103 of the fourth D-type flip-flop 115 is connected to the input of the thirty-fourth inverter 154, whose output for the DCE signal is connected to the eighteenth input 48 of the I / O bus 333. The first input of the fifteenth two-input logic product negation circuit 170 for the DEC signal is connected to the first input of the eighth three-input logic product negation circuit 184, to the first input of the sixteenth 28-input logic product negation circuit 171, the first input of the sixth three-input logic product negation circuit 182 and at the same time forms the twenty-first wiring input 21 for connection to the processor control unit, the second input of the fifteenth two-input logic product negation circuit 170 for the K5 signal same time the twenty-fourth 24 input circuit for connection to the controller processor. The output of the fifteenth two-input logic-type negation circuit 170 is connected to the data input 297 of the fifth D-type flip-flop 116, whose neutral output 0104 is connected to the input of the thirty-fifth inverter 155. 333 The second input of the eighth three-input signal circuit 184 simultaneously forms the twenty-third wiring input 23 for connection to the processor controller. The output of the eight-input logic product negation circuit 184 is coupled to the data input 299 of the type D sixth flip-flop 117 whose null output 0105 for the CLF signal is connected to the first input of the six-input logical product negation circuit 161 to the first input of the nineteenth two-input circuit 174 of the logic product negation type, the first input of the logic product negation 175, the first input of the 14th logic product negation 169, the first input of the third four-input sum gate product 187 and the first input of the ninth logic negation two input 164 the output of whose output for the V121R signal is connected to the second input of the first two-input logic-type negation circuit 156. The second input of the 16th logic product negation circuit 171 of the K1 signal simultaneously forms the twenty second wiring input 22 for connection to the processor controller. The output of the 16th dual-input logic negation circuit 171 is connected to the data input 301 of the seventh D-type flip-flop 118, whose one output 0106 for the FA signal is connected to the fourth input 285 of the second converter 111 from BCD to one of ten. The input of the twenty-eight inverter 148 for the TB signal also forms the twenty-sixth wiring input 26 for connection to the processor controller. The output of the twenty-eight inverter 148 is connected to clock inputs 294. 296, 298. 300. 302 of the third to seventh type D flip-flops 114 to 118. The output of the eighteenth two-input logic product type 173 for 8TC9 signal is connected to the twenty-fourth input 54 input. and output 29 of bus 333. The output of the nineteenth logical product negation circuit 174 for CLF9 signal is connected to two Fifth and fifth input 55 of the input and output bus 333. The output of twenty-two logical product negation circuit 175 for XO5 signal simultaneously forms the eighteenth output 018 for connection to an indication control circuit (not shown). The output of the twenty-first two-input logic product negation circuit 176 for the BEEP signal simultaneously forms the nineteenth wiring output 019 for connection to an audio control circuit (not shown).

The wiring consists of an input and output register 331, an input and output controller 332, and an input and output bus 333 (FIG. 1). The wiring is connected to the processor system and is coupled to the controller by means of TG, TB signals representing the timing input signals for the controller timing, OUT, representing the input signal for transcribing data to the input and output registers 331 _t INP as input signal for setting. direction of bus drivers, CS, as input signal to open bus drivers, IOF, indicating output status signal, DEC, as input signal for format switch, PREŘ, as constants notifying processor interrupt request, Κΐ, Z2, K5, Κδ ” , which represent control bits for adjusting the phases FA, C'LF for fast channel control and interrupt. It is connected to the arithmetic and logic unit by signals DO to Dl $ representing data input to the input and output register 331> to the bus drivers and the input of the operation code to the input and output controllers 332, 0 to ΪΪ 5 representing data output from the input and output register 331 to the arithmetic and logic unit, ES, as the output signal for opening the data bus in the arithmetic and logic unit. All internal and external peripheral devices are connected to the input and output bus 333. In addition to the input and output bus 333, X05 signals, representing the output signal to control the light indication, BEEP, are intended as an output signal to control the acoustic signal, INPUT, representing an input signal for a tape cassette memory request, SHIFT, as an input signal for reporting a keyboard status.

The control circuits control the input and output bus 333 to which they transmit data from the arithmetic and logic unit and to the arithmetic and logic unit via the input and output registers 331 and which they control via the input and output controllers 332 based on microinstruction coming from the processor control unit. Furthermore, it controls all input and output units that are part of the intelligent terminal, ie the tape cassette, display, keyboard and indication circuits. Contact with the processor is provided by input signals D0 to D15, i.e., sixteen signals that come from the data bus in the arithmel; and logic unit via input and output register 331 to peripheral devices, via V (0) to V (15) signals, or via EXT (0) to EXT (15) fast channel signals. Furthermore, the output signals TO to ΤΪ5 are applied to the data bus in the arithmetic and logic unit. The input signals ΚΓ, Z2 ^- , K5, Kn, INP, CS, OUT, DEC come from the microprogram memory, which is part of the processor control unit, which stores the microprograms for operating the input and output control circuits. By invoking the appropriate microprogram in the processor controller, the input and output controller 332 performs the desired operation with the peripheral device. The PRER signal notifies the processor of the interrupt request required by the P signal, and the PREB signal notifies all peripheral units that the processor is interrupted. Contact with the processor time source in the processor controller is effected by input signals TB, TC, which determine the individual steps of the microprogram in the processor controller and thereby also determine the time intervals at which the respective input or output operation in the control circuits is to be performed. The internal contact between the input and output controllers 332 and the input and output registers 331 is via the VOTTS signal for transmitting information from the input and output bus 333 'to the input and output registers 331, the V121E signal for resetting the peripheral device address. inverting fieldbus drivers 105 to 108 with output signals EXT (0) to EXT (15) and a ED signal to open data paths between the arithmetic and logic unit and the input and output register 331. To control the internal input and output units cassette tape memory, SHIFT for keypad status reporting, BEEP for audio signal control, and COD5 for indication control. Control of peripheral devices is done via signals on the input and output bus 333 ·. Sixteen output signals V (0) to V (15) are used to transmit data, commands, and addresses from the input and output registers 331 to peripheral devices. Twelve input signals E (0) to E (11) are used to transmit data and states from peripheral devices to input and output register 331, input signal Ě (8) reports from peripheral devices to input and output controller 332 that this facility has ceased its activity. The input signal P transmits an interrupt request from the peripheral devices to the input and output controllers 332. The PREB output signal reports from input and output controller 332 to the peripheral device that the processor interrupt is blocked. RBIT is a control bit that determines the validity period of data, commands, and addresses given by V (0) to V (15) signals. The Ó3 signal modifies the Tó) to É (11) signals when the interrupt is operated. The CLC2, 3TC9, CLF9 signals control control bits in peripheral devices. The NUL signal supplied simultaneously to the input and output controllers 332 sets the initial state. The K3T0P signal forcibly shuts down the peripheral device. The operation of the fast channel is controlled by a DMA signal that opens three-way bidirectional inverting drivers 105 to 108 for the EXT (0) to EXT (15) signals in the appropriate peripheral device and in the input and output register 331, and a DČČ signal that sets the data transfer direction to bidirectional inverting fieldbus drivers 105 to 108 of the fast channel EXT (0) to EXT (15) signals, and a DMA3 signal that determines the validity period of the data on the fast channel buses. The reset signal is reset to zero. The stimulus for any input or output operation is given from the processor by means of the DEC, ΚΪ, K2, K5, K6 signals, which are generated by microprogramming, as well as the OUT, INP, GS signals (Fig. 3). The combination of the DEC.K1 signals starts the FA phase given by the signal of the same name, the DEC.K2.D1 phase CLF given by the same signal and the DEC.K5 DMAS phase given by the same signal. Simultaneously with the arrival of these signals, an input and output operation consisting of data signals D3 to D9 coming from the data buses of the arithmetic and logic unit comes from the processor. This code is decoded by converters 110, 111 from BCD to code one in ten and applied to the input logic circuits of the input and output controller 332, which already generate either directly or via memory the resulting input and output bus signals 333, i.e. signals RBIT, PREB, Ř03, ČLG2, DMAŠ, ŠŤCŠ, W. Furthermore, internal signals VOIIS and VI215R are generated to control the input and output register 331. These signals, together with the OUT signal from the microprogram memory, control the input and output register 331 and thereby and the output bus for signals V (0) to V (15). The fast channel is also controlled by the microprocessor of the processor via the INP, CS signals coming from the microprocessor memory in the processor controller. The CS signal will open bi-directional inverting field drivers 105 to 108 of the EXT (0) to EXT (15) signals in the After sending or receiving data to an external peripheral device or sending control signals, the processor terminates execution of the respective microprogram and the circuit returns to the initial state while the processor continues to perform operations that are not related to the input operation. and output controller 332 without waiting for peripheral devices to shut down. When this peripheral unit terminates the requested operation, it will report its readiness BUC signal E (8) or the signal F. The signal E (S) is input to the eight channel multiplexer 109 selects data, from other circuits via a ^one IOI signal to the arithmetic and logic unit , where this condition is tested and when it is set to logic 1, another microprogram is started to perform the input or output operation. The signal F is applied to the input of the twenty-sixth inverter 146 and to the ninth three-input logic-type negation circuit 264 from where it arrives as the PEER signal to the arithmetic and logic unit, where it is evaluated and arithmetic and logic unit interrupt handling, which includes setting the FA phase and then setting the PREB signal, which notifies the peripheral units that the processor is handling the interrupt. Once the processor has processed the interrupt request, the new operation is started as described above and the process is repeated. The wiring activity is further evident from the microinstruction composition (Fig. 3) and the time source time diagram (Fig. 4). For better clarity, a positive representation of some signals is used in the timing diagram.

The I / O control circuits of the present invention can be used in desktop computers and in particular in intelligent terminals.

Claims (1)

Connection of input and output control circuits, in particular for an intelligent terminal, characterized in that the first input of the third two-input logic product negation circuit (158) is connected to the third input of the sixth three-input logic product negation circuit (182) to clock inputs (289,336) a first and eighth type D flip-flop (112,334) and simultaneously form an eighteenth wiring input (18), the second input of the third two-input logic product negation (158) is connected to the data input (335) of the eighth type D flip-flop (334) the one output (0109) is connected to the inputs (70,82,94,228) for selecting the words of the first to fourth quadruple dual-input multiplexer (101-104) with memory and simultaneously form the seventeenth input (17) wiring, output of the third dual-input circuit (158) the negation of the logic product is connected to the first input of the second two-input negation logic circuit (157) and to the first input of the first two-input logic product negation circuit (156), the output of which is connected to the clock input (226) of the fourth quadruple two-input memory multiplexer (104), connected to the clock inputs (68,80,92) of the first to third quadruple dual-input memory multiplexers (101 to 103), the first input (60) of the first multiplexer to the first quadruple dual input memory multiplexer (101) being connected via the twenty-fourth resistor (211) ) to the zero voltage terminal (330) through the twenty-third resistor (210) to the positive voltage terminal (329) and to the first output (022) of the input and output bus (333) and the second input (61) of the first multiplexer of the first quadruple two-input a multiplexer (101) with memory connected to the first data output (063) and to the first data input (231) The first multiplexer input (62) of the first quadruple dual-input memory multiplexer (101) is connected to the terminal (330) via a twenty-second resistor (209). the voltage across the twenty-first resistor (208) to the positive voltage terminal (329) and the second output (023) of the input and output bus (333) and the second input (63) of the second multiplexer of the first quadruple dual input multiplexer (101). it is connected to the third input of the reed three-input logic product negation circuit (184), to the second data output (064) and to the second data input (232) of the first bidirectional inverting bus driver (105). the third multiplexer input (64) of the first quadruple dual-input multiplexer (101) with memory is connected to the first twenty a resistor (207) to the zero voltage terminal (330), through a nineteenth resistor (206) to the positive voltage terminal (329), to a third output (024) of the input and output bus (333), a second input (65) of the third multiplexer of the first the quadruple dual-input memory multiplexer (101) is connected to the third data output (065) and the third data input (233) of the first bidirectional bus driver (105) and simultaneously form the third wiring input (3), first input (66) of the fourth multiplexer the first quadruple dual-input memory multiplexer (101) is connected via the 18th resistor (205) to the zero voltage terminal (330), through the 17th resistor (204) to the positive voltage terminal (329), and to the fourth output (025) of the input and the output bus (333), the second input (67) of the fourth multiplexer of the first quadruple dual-input memory multiplexer (101) is connected to the third address vs tup (272) of the eight-channel multiplexer (109) for the view function, to the first input (276) of the first converter (110) from the BCD code to one of ten, to the fourth data output (066) and to the fourth data input (234) a bidirectional inverting bus driver (105) simultaneously forming a fourth wiring input (4), the first first multiplexer input (72) of the second quadruple dual-input memory multiplexer (102) being connected via a 16th resistor (203) to the zero voltage terminal (330) on the one hand through the fifteenth resistor (202) to the positive voltage terminal (329), on the other hand to the fifth output (026) of the input and output bus (333), the second input (73) of the first multiplexer the address input (271) of the eight-channel multiplexer (109) for the view function, to the second input (277) of the first converter (110) from the BCD code to, the code one of ten, to the first d the output (067) and the first data input (239) of the second bidirectional inverting bus driver (106) and at the same time form the fifth wiring input (5), the first second multiplexer input (74) of the second quadruple dual input multiplexer (102) on the one hand through the fourteenth resistor (201) to the zero voltage terminal (330), on the other hand through the thirteenth resistor (200) to the positive voltage terminal (329) and, on the other hand, to the sixth resistor.  the input and output bus tup (333), the second second multiplexer input (75) of the second quadruple dual-input memory multiplexer (102) is coupled to the first address input (270) of the eight-channel multiplexer (109) for the view function, to the third input (278) a first transducer (110) from BCD code to code one of ten, to a second data output (068), and to a second data input (240) of a second bidirectional inverting bus driver (106), forming a sixth wiring input (6); the first input (76) of the third multiplexer of the second quadruple dual-input multiplexer (102) with the memory is connected via the twelfth resistor (199) to the zero voltage terminal (330) and through the eleventh resistor (198) to the positive voltage terminal (329) the seventh output (028) of the input and output bus (333), the second input (77) of the third multiplexer of the second quadruple dual-input multiplexer (102) with only to the fourth input (279) of the first converter (110) from the BCD code to one of ten, to the third data output (069) and to the third data input (241) of the second bidirectional inverting bus driver (106); 7) wiring, the first input (78) of the fourth multiplexer of the second quadruple dual-input memory multiplexer (102) is connected via the tenth resistor (197) to the zero voltage terminal (330) and through the ninth resistor (196) to the positive terminal (329) the second input (79) of the fourth multiplexer of the second quadruple dual-input memory multiplexer (102) is connected to the first input (282) of the second converter (111) from the BCD code to the code one of ten, to the fourth data output (070) and to the fourth data input (242) of the second bidirectional inverting bus driver (106) and simultaneously forms the eighth wiring input (8) , the first input (84) of the first multiplexer of the third quadruple dual-input multiplexer (103) with the memory is connected via the 17th inverter (137) to the first data input (262) of the eight-channel multiplexer (109) to the zero voltage terminal (330) through the seventh resistor (194) to the positive voltage terminal (329) and to the ninth output (030) of the input and output bus (333) and the second input (85) of the first multiplexer of the third quadruple two-input multiplexox (103) with memory is connected to the second input (283) of the second converter (111) from the BCD code to one of ten, to the first data output (071) and to the first data input (246) of the third bidirectional inverting bus driver (107) and simultaneously form the ninth input (9) of the wiring, the first input (86) of the second multiplexer of the third four -36-fold dual-input memory multiplexer (103) a sixth resistor (193) to the zero voltage terminal (330), through a fifth resistor (192) to the positive voltage terminal (329) and to a tenth output (031) of the input and output bus (333) and a second input (87) of the second the third quadruple dual-input multiplexer (103) with memory is connected to the third input (284) of the second converter (111) from the BCD code to one of ten, to the second data output (072) and to the second data input (247) of the third bidirectional inverting The bus drivers (107) form at the same time the tenth input (10), the first third multiplexer input (88) of the third quadruple dual-input memory multiplexer (103) is connected via a fourth resistor (191) to the zero voltage yard (330) a third resistor (190) to the positive voltage terminal (329), to the eleventh output (032) of the input and output bus (333), and the second input (89) of the third multiplexer to the third quadruple A common two-input memory multiplexer (103) is connected to the third data output (073) and the third data input (248) of the third bidirectional inverting bus driver (107), and simultaneously forms the eleventh wiring input (11), the first input (90) of the fourth the third quadruple dual-input multiplexer (103) with memory is connected via the second resistor (189) to the zero voltage terminal (330), through the first resistor (188) to the positive voltage terminal (329) and to the twelfth output (033) and an output bus (333), the second fourth multiplexer input (91) of the third quadruple dual-input memory multiplexer (103) is coupled to the fourth data output (074) and the fourth data input (249) of the third bidirectional inverting bus driver (107). simultaneously twelfth input (12) wiring, first inputs (96,98,100,224) of the first to fourth multiplexer fourth quad the dual-input memory multiplexer (104) is connected via a thirty-third resistor (220) to the positive voltage terminal (329), the second input (97) of the first multiplexer fourth quadruple dual-input memory multiplexer (104) is connected to the first data output (075) and to the first data input (255) of the fourth bidirectional inverting bus driver (108) and simultaneously form the thirteenth wiring input (13), the second second multiplexer input (99) of the fourth quadruple dual-input memory multiplexer (104) connected to the second data output. 076) and to the second data input (256) of the fourth bidirectional inverting bus driver (108) and simultaneously form the fourteenth wiring input (14), the second third multiplexer input (223) of the fourth quadruple dual input memory multiplexer (104) connected to the third data output (077) and the third data input (257) of the fourth bidirectional inverting bus driver (108) and simultaneously form the fifteenth wiring input (15), the second fourth multiplexer input (225) of the fourth quadruple dual-input memory multiplexer (104) connected to the fourth data the output (078) and the fourth data input (258) of the fourth bidirectional inverting bus driver (108) and simultaneously form the sixteenth wiring input (16), power inputs (71,83,95,229) of the first to fourth quadruple dual input multiplexer (101 to 104) with memory they are connected to the positive voltage terminal (329), while their ground the inputs (69,81,93,227) are connected to the zero voltage terminal (330), the first multiplexer output (047) of the first quadruple dual input multiplexer (101) with memory is connected to the input of the first inverter (121) and simultaneously form the first output (01) the second multiplexer output (048) of the first quadruple two-input multiplexer (101) is connected to the input of the second inverter (122) and simultaneously forms the second output (02) of the third multiplexer of the first quadruple two-input multiplexer (101) the memory is connected to the input of the third inverter (123) and simultaneously forms the third wiring output (03), the fourth multiplexer output (050) of the first quadruple two-input memory multiplexer (101) is connected to the input of the fourth inverter (124) a fourth wiring output (04), a first multiplexer output (051) of a second quadruple two input mul the memory tiplexer (102) is connected to the input of the fifth inverter (125) and simultaneously forms the fifth wiring output (05), the second multiplexer output (052) of the second quadruple dual-input memory multiplexer (102) is connected to the sixth inverter (126) input; at the same time forming the sixth circuit output (06), the third multiplexer output (053) of the second quadruple two-input memory multiplexer (102) is connected to the input of the seventh inverter (127) and simultaneously forming the seventh circuit output (07), output (054) of the fourth multiplexer the quadruple dual-input memory multiplexer (102) is connected to the input of the eighth inverter (128) and simultaneously forms the eighth wiring output (08), the output (055) of the first multiplexer of the third quadruple dual-input memory multiplexer (103) is connected to the input of the ninth inverter ) and simultaneously form the ninth output output (09), the output (056) of the second multiplexer in the third quadruple dual-input memory multiplexer (103), it is connected to the input of the tenth inverter (130) and simultaneously forms the tenth output (010), the third multiplexer output (057) of the third quadruple dual-input memory multiplexer (103) is connected to the input of the eleventh inverter (131) and simultaneously form the eleventh wiring output (011), the fourth multiplexer output (058) of the third quadruple dual-input memory multiplexer (103) is connected to the input of the twelfth inverter (132) and simultaneously form the twelfth wiring output (059) ) the first multiplexer of the fourth quadruple dual-input memory multiplexer (104) is connected to the input of the thirteenth inverter (133) and simultaneously form the thirteenth wiring output (013), the output (060) of the second quadruple dual-input memory multiplexer (104) 14th inverter (1 34) and at the same time form the fourteenth wiring output (014), the third multiplexer output (061) of the fourth quadruple dual-input memory multiplexer (104) is connected to the fifteenth inverter (135) input and simultaneously form the fifteenth wiring output (015), output (062) the fourth multiplexer of the fourth quadruple dual-input multiplexer (104) with memory is connected to the input of the 16th inverter (136) and simultaneously forms the 16th wiring output (016), the output of the first inverter (121) is connected to the first input (31) ), the output of the second inverter (122) is connected to the second input (32) of the input and output bus ¢ 3. 33), the output of the third inverter (123) is connected to the third, the input (33) of the input and output bus (333), the output of the fourth inverter (124) is connected to the fourth input (34) of the input and output bus (333) the inverter (125) is connected to the fifth input (35) of the input and output bus (333), the output of the sixth inverter (126) is connected to the sixth input (36) of the input and output bus (333) to the seventh input (37) input and output bus (333), the output of the eighth inverter (128) is connected to the eighth input (38) of the input and output bus (333), the output of the ninth inverter (129) is connected to the ninth input (39) input and output bus (333), output of tenth inverter (130) is connected to tenth input (40) of input and output bus (333), output of eleventh inverter (131) is connected to eleventh input (41) of input and output bus (333) ), output twelve the thirteenth inverter (133) is connected to the thirteenth input (43) of the input and output bus (333), the output of the fourteenth inverter (134) is output to the thirteenth inverter (133) is connected to the fourteenth input (44) of the input and output bus (333), the output of the fifteenth inverter (135) is connected to the fifteenth input (45) of the input and output bus (333), the output of the sixteenth inverter (136) is connected to the 46) input and output buses (333), power inputs (235,243, 250,259) of the first to fourth bidirectional inverting bus drivers (105 to 108) are connected to the positive voltage terminal (329), while their ground inputs (237,245,252,261) are connected to the terminal (330) zero voltage, the first input and output data terminal (307) of the first bidirectional inverting bus driver (105) is connected to the first input and output terminal (035) the input / output bus stage (333), the second input / output data terminal (308) of the first bidirectional inverting bus driver (105) is connected to the second input / output bus terminal (036), the third terminal (309) the input and output data of the first bidirectional inverting bus driver (105) is connected to the third input and output bus (333) input and output terminals (333), the fourth input and output data terminal (310) of the first bidirectional inverting bus driver (105) is connected to a fourth input and output bus (333) input and output terminal (333), a first data input and output terminal (311) of the second bidirectional inverting bus driver (106) coupled to the fifth input and output bus input and output terminal (039) (333), the second data input and output terminal (312) of the second bidirectional inverting bus driver (106) is connected to the sixth terminal (040Z input) the input and output bus terminals (313), the third input and output data terminal (313) of the second bidirectional inverting bus driver (106) is connected to the seventh input and output bus terminal (041), the fourth input terminal (314) and the data output of the second bidirectional inverting bus driver (106) is connected to the eighth input and output bus terminal (042), the first data input and output terminal (315) of the third bidirectional inverting driver (107) is connected to the the ninth input and output bus (333) input and output terminals (333), the second input and output data terminal (316) of the third bidirectional inverting bus driver (107) is connected to the input and output bus (333) input and output terminals (044) ), the third data input and output terminal (317) of the third bidirectional inverting bus driver (107) is connected to the eleventh terminal (045) the input / output bus (333) input and output, the fourth input / output / output data terminal (318) of the third bidirectional inverting bus driver (107) is connected to the twelfth input / output bus (333) terminals ), the first input and output data terminal (319) of the fourth bidirectional inverting bus driver (108) is connected to the thirteenth input and output bus terminal (047), the second input and output terminal (320) of the fourth bidirectional inverting data the bus driver (108) is connected to the input and output bus (333) input and output terminal (048), the third input and output data terminal (321) of the fourth bidirectional inverting bus driver (108) is connected to the input 15 input terminal (040) and an input and output bus output (333), a fourth input and output data terminal (322) of a fourth bidirectional inverting exciter (108) ) the bus is connected to the 16th input and output bus terminal (050), the power input (275) of the eight-channel multiplexer (109) for the data selection function is connected to the positive voltage terminal (329), while its ground input ( 274) is connected to the neutral voltage terminal (330) and its trip input (273) to the neutral voltage terminal (330), the one output (079) of the eight-channel multiplexer (109) for data selection is connected to the data input (288) of the first flip-flop (112) of type D, whose one output (096) is connected to the second input of the first four-input summation gate (185) and whose zero output (097) is connected to the third input of the first four-input summation gate (185), first output (080) ) the first converter (110) from BCD code to code one in ten is connected to the first input of the first three-input circuit (177) of the an input of an eighteenth inverter (138) whose output is connected to a fourth input of a second four-input summation gate (186), a second output (081) of a first converter (110) from BCD to one of ten is connected to an input of the twenty first inverter ), the output of which is connected to the second input of the twenty-two logic product negation circuit (175), the third output (082) of the first converter (110) from the BCD code to one of ten is connected to the input of the nineteenth inverter (139) is connected to the second input of the seventeenth two-input logic product negation circuit (172) and to the second input of the twenty-second two-input logic product negation circuit (176), the fourth output (083) of the first converter (110) from BCD to one of ten connected to the input of the twentieth inverter (1401), the output of which is coupled to the second input of the twelve n and to the second input of the fourteenth two-input circuit (169) of the type of negation of the logical product, the fifth output (084) of the first converter (110) from the code.  A BCD to code one of ten is coupled to the first input of the second three-input logic product negation circuit (178), the output of which is connected to the second input of the sixth logic product negation two input circuit (161), the seventh output (085) of the first converter (110) from BCD to code one of ten is connected to the third inputs of the first and second three-input circuit (177,178) of the negation of the logical product and to the first input of the fourth two-input circuit (159) of the negation of the logical product of its output (165) of the logic product negation type and the second input of the ninth two-input circuit (164) of the logic product negation type, the eighth output (086) of the first converter (110) from BCD to code one of ten is connected to the second input of the fourth two input circuit (159) of the logic product negation type, to the second input of the second three-input logic negation circuit (178) and to the second input of the first three-input logic product negation circuit (177), the output of which is connected to the second input of the fifth two-input logic product negation circuit (160), to the second input of the second four-input sum gate product (186) and the third four-input total product gate (187), the tenth output (087) of the first converter (110) from BCD to one in ten is connected to the input of the twenty-second inverter (142) whose output is connected to the second input of the eighteenth two-input circuit ) of the logic product negation type and the second input of the nineteenth two-input logic product negation circuit (174), the power inputs (280,286) of the first and second converters (110,111) from the BCD code to one of ten are connected to the positive voltage terminal (329). whereas their ground inputs (281,287) are connected to the neutral voltage terminal (330), first The output (088) of the second converter (111) from the BCD code to the code one in ten is connected to the input of the twenty-third inverter (143), the output of which is connected to the first input of the seventeenth 089) of the second converter (111) from BCD to code one of ten is connected to the input of the twenty-fourth inverter (144), the output of which is connected to the first input of the fifth two-input 42 circuit the logic product negation circuit (165), the third output (090) of the second converter (111) from BCD to code one of ten is connected to the first input of the first four-input sum product gate (185), whose output is simultaneously the twenty-first output (021) ), the fourth output (091) of the second converter (111) from the BCD code to the code one of ten is connected to the fourth input of the first a four-input total product gate (185), the fifth output (092) of the second converter (111) from BCD to one of ten is connected to the first input of the third three-input logic product negation circuit (179) four input I / O gate (186), sixth output (093) of second converter (111) from BCD to one in ten is connected to second input of third three-input logic product negation circuit (179), seventh output (094) of second converter (111) 111) from BCD to code one of ten is connected to the third input of the third three-input logic product negation circuit (179), the eighth output (095) of the second converter (111) from BCD to code one of ten is connected to the twentieth input a fifth inverter (145), the output of which is connected to the first input of a second four-input total product gate (186), to the first input of two the first input of the eighteenth two-input logic product negation circuit (173) and the first input of the twenty-first two logic product negation circuit (176), the input of the twenty-ninth inverter (149) is connected to a fourth data input (265) of the eight-channel multiplexer (109) for the view function, to the twenty-seventh input (57) of the input and output bus (333) simultaneously forming the twenty-ninth wiring input (29), the twenty-ninth inverter (149) output the first input of the seventh two-input logic product negation circuit (162), the output of which is connected to the first input of the ninth three-input logic product negation circuit (264), the input of the twenty-sixth inverter (146) is connected via the twenty-seventh resistor (214) the positive voltage terminal (329) through the twenty-eight resistor (215) to the terminal (330) 13) the output (034) of the input and output bus (333), the output of the twenty-sixth inverter (146) is connected to the first input of the twenty-second two-input logic product type (266) and to the second input of the ninth three-input43 the logic product negation circuit (264), the output of which is at the same time the twentieth output (020) of the circuit, the output of the fifth two * logic product negation input circuit (160) is connected to the first input of the fourth logic product negation the output is connected to the sixth input (267) of the eight-channel multiplexer (109) for the view function, to the second input of the seventh two-input logic product negation circuit (162) and to the first input of the fifth three-input logic product negation circuit (181) The circuit (161) is connected to a third input of a fifth three-input circuit (181) of the logic product negation type, the output of which is connected to the third input of the fourth three-input logic product negation circuit (180) and the input of the 30th inverter (150), the output of the 30th inverter (150) is connected to the 20th input (50) output bus (333), the second input of the sixth logic product negation circuit (182) is simultaneously the twenty-fifth wiring input (25), the output of the sixth logic product negation circuit (182) is connected to the second input of the fourth three-input circuit (180) of the logic product negation type and to the second input of the eighth two-input logic product negation circuit (163) whose output is connected to the second input of the twenty-second two-input logic product negation circuit (266) it is connected to the first input of the eighth two-input circuit (163) of the logic product negation type and at the third input of the ninth three-input logic product negation circuit (264), the output of the second four-input cumulative product gate (186) is connected to the adjusting input (269) of the second type D flip-flop the output (098) is connected to the second input (263) of the eight-channel multiplexer (109) for the view function, the seventh input (268) of the eight-channel multiplexer (109) for the view function simultaneously comprises the twentieth input (20) of wiring, data input (290) the second D-type flip-flop (113) is connected to the neutral voltage terminal (330), while its neutral output (099) is connected to the input of the thirty-first inverter (151), the output of which is connected to the twenty-first input and output bus (333), the input of the twenty-seventh inverter (147) is connected to the second input of the seventh three-input circuit (183) of the input of the fifth three-input logic product (181), to the 26th input (56) of the input and output bus (333), and simultaneously form the 30th input (30) of the wiring, output of the 27th inverter (147) connected to the third and fourth the input of a third four-input summation gate (187) whose output is connected to the reset input (292) of the second D-type flip-flop (113), the output of the tenth two-input logic product negation circuit (165) is connected to the first input of the eleventh two-input circuit ) of the logic product negation type, the output of which is connected to the second trigger input (304) of the first monostable flip-flop (119), the second input of the eleventh two-input logic product negation circuit (166) is connected via terminal 20 (216) to terminal 329 ) of a positive voltage, on the one hand through a thirty resistor (217) to the zero voltage terminal (330) and form including the nineteenth wiring input (19), the first trigger inputs (303, 305) of the first and second monostable flip-flops.  (119, 120) are connected to the zero voltage terminal (330), the zero output (0107) of the first monostable flip-flop (119) is connected to the second input of the second two-input logic-type negation circuit (157) and to the second trigger input (306) of the second monostable a flip-flop (120) whose zero output (0108) is connected to the clock input (291) of the second flip-flop (113) of type D, between the input (323) for external capacity and the input (324) for external resistance and capacity a second capacitor (222) is connected to the circuit (119) and a thirty-first resistor (218) is connected between its input (324) for external resistance and capacity and an input (325) for external resistance and input (326) (327) for the external resistor and capacitance of the second monostable flip-flop (120), a first capacitor (221) is connected, and an external resistor input (328) the thirty-second resistor (219), the output of the twelfth two-input logic product negation circuit (167) is connected to the first input of the thirteenth two-input logic product negation circuit (168), the output of which is connected to the input of the thirty-second inverter (152) and the output of the thirty-second inverter (152) is connected to the twenty-second input (52) of the input and output bus (333), the output of the fourteenth of the two input inputs (169) of the negation of the logical product is connected to the third input of the seventh three-input logic product negation circuit (183), the output of which is connected to the second input of the thirteenth two-input circuit (168) ty45 pu logic product negation, data input (293) of the third D type flip-flop (114) 28) wiring, one output (0100) of the third flip-flop (114) typ for D, it is connected to the input of the thirty-third inverter (153), whose output is connected to the 17th input (-47) of the input and output bus (333), the zero output (0101) of the third type D flip-flop (114) 230,238,253,254) for selecting the first to fourth bidirectional inverting bus driver (105-108) circuit, the data input (295) of the fourth D-type flip-flop (115) is simultaneously the twenty-seventh wiring input (27), one output (0102) of the fourth flip-flop 115) of type D is connected to inputs (236,244,251,260) for controlling the data flow direction of the first to fourth bidirectional inverting bus drivers (105 to 108) and simultaneously form the seventeenth wiring output (017), zero output (0103) of the fourth flip-flop (115) D is connected to the input of the thirty-fourth inverter (154), the output of which is connected to the eighteenth input (48) of the input and output p, the 17th logic product negation 17 input circuit (172) is connected to the 23rd input / output bus (333) input, the 15th logic product negation 17 input circuit (170) is connected to the first input of the eighth three input circuit 184 input (184) ) of the logic product negation type, to the first input of the sixteenth two-input circuit (171) of the logic product negation type, to the first input of the sixth logic product negation type three-input circuit (182) and forming the twenty-first wiring input (21); 170), the logic product negation type is also the twenty-fourth wiring input (24), the output of the 15th logical product negation type input (170) is connected to the data input (297) of the D-type fifth flip-flop (116). is connected to the input of the thirty-fifth inverter (155) whose output it is connected to the 19th input (49) of the input and output bus (333), the second input of the eighth three-input circuit (184) simultaneously forms the twenty-third wiring input (23), the output of the eighth three-input logical product (184) (299) a sixth type D flip-flop (117), whose null output (0105) is connected to the first input of the sixth logic product negation two-input circuit (161), to the first_up of the nineteenth logical product negation two-input circuit (174), input of the twenty-two-input logic product negation circuit (175), to the first input of the fourteenth, two-input logical product negation circuit (169), to the first input of the third four-input total product gate (187) and to the first input of the ninth negation two-input circuit (164) the logic product whose output is connected to the second input of the first two-input circuit at (156) the logical product negation type, the second input of the 16th two-input logic product negation circuit (171) simultaneously forms the twenty-second wiring input (22), the output of the sixteenth two-input logic product negation circuit (171) is connected to the data input (301) a seventh D-type flip-flop (118) whose one output (0106) is connected to the fourth input (285) of the second BCD to one of ten, the input of the twenty-eight inverter (148) simultaneously being the twenty-sixth input ( 26) wiring, output of twenty-eight inverter (148) is connected to clock inputs (294,296,298,300,302) of third to seventh type D flip-flops (114 to 118), output of eighteenth two-input logic product negation circuit (173) is connected to twenty-fourth input ( 54) input and output bus (333), output of nineteenth two-input circuit (174) of logical product negation is connected to the 25th input (55) of the input and output buses (333), the output of the twenty-two logic product negation circuit (175) is simultaneously the 18th output (018), the twenty-first two-input logic negation circuit output (176) simultaneously nineteenth output - (019) wiring.