JPS5834854B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in hardware provided for improving maintainability and availability of an information processing system.

Normally, an information processing device has a main memory and achieves its main purpose by sequentially executing the instructions stored in the main memory, but in addition to the hardware necessary for this purpose. It also has hardware for various purposes such as fault diagnosis, maintenance work, firmware loading, and fault detection.

(Underground In this invention, these are referred to as maintenance/diagnosis hardware.) Efforts have been made to use each type of hardware in common where it can be used, but each hardware has its own purpose and purpose. Because the purposes and control subjects (operators, maintenance personnel, diagnostic programs, etc.) differ, hardware has not necessarily been unified and commonly used as a whole.

This required a large amount of hardware, and it was also difficult to understand that hardware.

The purpose of the present invention is to solve these conventional problems by providing a highly versatile and economical 7%-F" ware configuration system for maintenance and diagnosis that can be commonly used for all purposes. It's about doing.

Specifically, the purpose is achieved in the following manner by integrating the control of the maintenance/diagnosis hardware into a unified design concept and diagnostic commands.

(1) By breaking down the movements that maintenance diagnostic hardware should have into basic and common basic operations and making each one an independent diagnostic command, each diagnostic command can be used commonly for various purposes and applications. It is economical.

(2) Since it has a unified format as a diagnostic command, it is easy to control the receiving, passing, and interpretation of diagnostic commands, and it can be commonly used for all purposes and uses by any control entity.

(3) Since the basic functions for maintenance and diagnosis are controlled through a clear interface called diagnostic commands, it is easy for the control entity to design control procedures, and it is highly economical.

Another object of the present invention is to provide an economical and easy-to-operate means for humans to freely read the internal state of an information processing device and to freely change the internal state of the information processing device. There is a particular thing.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the position of the present invention in an information processing system and how it is connected.

10 is the CPU. 12 is a system controller, 13 is a main storage device, 14 is a channel device, and 15 is an operation console, which constitute a standard multiprocessor configuration.

In this embodiment, the operation console includes a floppy disk device (hereinafter referred to as FDD) 17 for performing so-called firmware loading, a CRT display device 18, a keyboard 19, and an operation processor 16 for controlling them.

The operation processor 16 is one of the microprocessor application devices.
It is made as one.

One of the input/output registers of the microprocessor 100 is a console interface port: CIPlol, and CI Pi 01 has a console interface port 21.
The operating console 15 receives a message to be displayed, and also sends a response input by an operator from a keyboard 19 to the channel device 19 in response to the message.

Reference numeral 11 denotes a diagnostic section including the main parts of the hardware related to the present invention, and is provided in each of CPU+0 and CPU+1.

The operation processor 16 also includes D.
I interface port: DIPl 02 is newly installed by the number of CPUs in the system, and the above-mentioned CIPlol
Similarly, it is connected as an input/output register of the microprocessor 100.

Each DI interface port DIP is connected to the diagnostic section of the corresponding CPU via the DI interface 20.

FIG. 2 is a diagram showing the signal line configuration of the DI interface 20.

The DI interface has a data line capable of bidirectional transmission and three data transfer control lines (5ELECT, BUSY, R/W) that control data transfer on the data line.
), and is an interface in which the operating processor takes the initiative to transfer one byte at a time.

PER1 for reporting to the operating processor if there is a parity error in the data received by the diagnostic unit from the DI interface, and INTER for reporting to the operating processor that an abnormal state has occurred in the CPU.
There are two abnormality reporting lines for RUPT.

FIG. 3 is a diagram showing how to control data transfer on the DI interface 20 using the signal lines shown in FIG.
Next, the situation when 1 byte of data is read from the DIP 102 is shown.

When sending data from the DIP 102 to the diagnostic unit 11, press R.
After setting the /W signal to zero and sending data 31 to the data line, the 5ELECT signal line is set to 1.

Then, after a certain period of time has elapsed, the 5ELECT signal line is set to 0, and data transmission is then stopped.

When reading data from the diagnostic section 11, the R/W signal line is set to 1, and then the 5ELECT signal is set to J.

Thereby, the diagnostic section 11 learns that data transmission is requested, and transmits the data 32 to the data line.

On the DIP102 side, after reading the data one hour later, S
Set the EL and ECT signal lines to O.

This causes the diagnostic unit 11 to stop sending data.

In this way, the DIP 102 takes the initiative to transfer data.

If the diagnostic section 11 is unable to respond immediately when data transfer is requested, the diagnostic section 11 can send the BUSY signal to make the DIP II side wait.

FIG. 3 shows a situation where, when an attempt is made to read data from the diagnostic section 11, the diagnostic section 11 is unable to respond immediately.

5 BUSY in advance before receiving the ELECT signal.
It is also allowed to leave the signal at 1.

This interface 20 is suitable when, as in this embodiment, the operating time of the Di interface circuit in the diagnostic section 11 is much shorter than the time required for the operating processor 16, which has the initiative, to execute one instruction. It is.

Fig. 4 shows the format 1 of the diagnostic command.As shown in Fig. 4a, the basic form of the diagnostic command consists of a command part of 1 byte, an address part of 1 byte, and a data part of 4 bytes. It is.

Then, the operation processor 16 becomes the main control body, and the CPU 1
In the case of moving 0, this diagnostic command is transmitted byte by byte via the DI interface 20 described above.

This diagnostic command is in principle transmitted from the operating processor 16 in the direction of the diagnostic section 11 .

Only the data part of the data reading type diagnostic command is diagnostic part 1.
1 in the direction of the operating processor 16.

In order to shorten the time for transferring diagnostic commands at the DI interface 20, and to reduce the storage capacity required when storing diagnostic commands,
The diagnostic command has a variable length in bytes so that it does not require unnecessary data.

b to f in Figure 4 show this. If the first bit of the command part is zero, the data part does not exist, and if this bit is 1-month, then the value of the last two bits of the command part The length of the data section is specified according to

The numbers stored at the bottom of the diagram representing each byte of the data section are byte numbers.

The details of the diagnostic command will be described later, but the basic function of the diagnostic command is to read the contents of the register specified by the address field and write the obtained information to the register specified by the address field, also in the data field. That's true.

In the case of a diagnostic command in which the leading digit 1- of the command is zero, the lower part of the command is also used to display the atomic number 1/-, as will be described later.

FIG. 5 embodies the invention. : Diagnosis section (Fig. 1 11)
This is a smaller version of the internal configuration of .

The data line of the DI interface 20 shown in FIG. 2 is connected to the output of the driver 41 and the input of the receiver 42.

I) Other signal lines of the I interface are not shown.

The output ZDGZ of the receiver 42 is sent via the selector 47 to command registers: R, DC48, and address registers: R.
DA49, data register: connected to RDD50.

Each of these registers has one action that receives the appropriate portion of the diagnostic command.

The output ZDGX of the selector 47 becomes an input to the driver 41, and also serves as data sent to the DI interface under the control of the control circuit 52.

The circuit described above is basically used to receive diagnostic commands sent from the operating processor 16.
It is the ll-1 road.

With further reference to FIG. 5, the circuitry used to execute diagnostic commands will be described.

The output of the command register 48 is sent to a control circuit 52, and the control circuit 52 sends a control signal according to the diagnostic command to each section inside the diagnostic section and the CPL.

Address register: The outputs of RDA49 and data register 1/register RDD50 are connected to inverters 53 and 5, respectively.
5 to various parts within the CPU.

Note that the subscript attached to the signal name RDD represents the byte number.

In addition, as a circuit for executing a data reading type diagnostic command, data line ZC in the CPU is connected to selector 5.
6 and the diagnostic bus ZDSPY is connected to selector 47.
It is connected to the.

The output ZDGT of the selector 56 is also connected to the selector 47, and as mentioned above, the output of the selector 47 can be sent to the DI interface, so in the end, ZC and ZDSPY can be sent to the DI interface. There is.

This completes the description of the circuit for executing diagnostic commands sent from the operating processor.

The remaining portions of FIG. 5 will be described later, but next we will explain how the diagnostic section 11 is connected to each section within the CPU 10.

FIG. 6 shows the internal connections of the CPU when the present invention is applied to the microprogram type CPU10.

The purpose of this diagram is to show how the diagnostic section of FIG. 5 is connected to various parts within the CPU, so only the necessary parts of the CPU are shown.

Since this CPU employs a microprogram system, it has a control memory 62 for storing microprograms in a control memory unit 60, and its output is sent to a microinstruction register 64 via a selector 63.

The output of the microinstruction register 64 controls various parts within the CPU as microinstructions.

Only the microinstruction decoder 68 in the arithmetic unit 70 is shown, and the control signal path is not shown, but the sixth
All of the circuits shown in the arithmetic unit 70 in the figure are controlled by microinstructions, except for the decoder 69 and selectors 71 and 79.

The arithmetic unit γ0 includes a register 72 and a scratch pad memory 73, both of which are connected to two selectors 7.
The outputs of selectors 75 and 76 are connected to two inputs of an arithmetic logic circuit: ALU 77.

The output of the ALU 77 is sent to the control unit 80 via the selector 78, and can be used to perform operations such as writing calculation results to the main memory.

Further, the output of the ALU 77 becomes an input to the register 72 via the selector γ1, and also serves as an input to the scratch pad memory 73, so that the calculation results of the ALU 77 can be stored in the register 72 and the scratch bed memory 13 again.

The address of the scratch pad memory 73 is the counter: R
CNT7471) et al.

The λ force signal of R, CNT 74, etc. are not shown.

Registers in Figure 5 that store the data portion of diagnostic commands:
The output of the RDD 50 is connected to a selector 63 so that the data portion of the diagnostic command can be written into the microinstruction register 64.

In addition to being connected to the selector 71, the output of the RDD 50 is also sent to other registers that can be written to by diagnostic commands, but these are not shown.

The output control signal of the control circuit 52 of the diagnostic section in FIG. 5 and the output of the address register: RDA 49 are sent to the decoder and diagnostic bus of each part in the CPU, and in FIG. 65. γ9 is shown.

One of the outputs of coder 61 is connected to control selector 63 and microinstruction register 64 so that when a diagnostic command is given to write to microinstruction register 64, the contents of the RDD are passed through selector 63. It has the function of controlling writing to the microinstruction register 64.

Also shown as another output of decoder 61 is a control line activated in response to the diagnostic command ``Write the contents of the microinstruction register to control store.''

The latter command is used during so-called firmware loading.

Next, an example of a circuit provided to execute a diagnostic command to read the contents of a specified register will be described.

The output of microinstruction register 64 is connected to selector 65.

The output of the selector 65 is commonly connected to the output of the selector 79 and the outputs of other selectors (not shown) to form a diagnostic bus ZDSPY.

When a diagnostic command to read the first byte of the microinstruction register 64 is given, the control signal and RD
The corresponding λ force of the selector 65 is selected by A,
The contents of the first byte of the microinstruction register appear on the diagnostic bus ZDSPY.

This is passed through the selector 47 in FIG.
sent to the interface.

Fault diagnosis becomes easier if the contents of any register in the CPU can be read directly to the diagnostic section through the diagnostic bus ZDSPY.
The SPY becomes larger and the cost becomes higher.

All registers and memories that can be sent to the data line ZC under the control of micro-instructions are read from the diagnostic unit via ZC, and a diagnostic bus is not provided for these registers and memories to reduce costs. are doing.

The details of how to successfully implement this will be explained below.

For example, in order to read the contents of register RA72, first, a microinstruction that causes "selector 75 to select RA register 72 as input, ALU 77 to output the Aλ force as it is, and selector γ8 to select ALU 77 as input" It is sufficient to issue a diagnostic command to read the data line ZC after writing it to the microinstruction register 64.

Further, in order to write data to the address pointed to by the RCNT 74 in the scratch pad memory 73, the following procedure may be taken.

First, the data to be written is written into the register RA, 72, which can be written directly by a diagnostic command.

In response to this diagnostic command, the output of the decoder 69 becomes 1, thereby selecting RDD as the input of the selector 71, and by applying a clock pulse to the register RA, 72, this diagnostic command is executed.

Next, the microinstruction register 64 writes “Selector 75 is f”.
(The A register 72 is selected as an input, and the ALU 77
CP
Execute a diagnostic command that moves U one step.

If a human is the controlling entity, steps like this are required.
Moreover, the above method, which requires memorizing appropriate microinstructions, is very inconvenient for humans.

One of the important points of the present invention is to solve this problem as follows and to provide a low-cost means that allows humans to freely read and write the internal registers of the CPU.

The operation processor 16 in FIG. 1 is a microprocessor application system and includes a floppy disk device 17.

Therefore, the procedure for reading and writing the registers as described above and the necessary microinstructions are stored on the floppy disk for all registers.

``When a person keys in the symbolic name of a register that he or she wants to read or write from the keyboard 19, the corresponding procedure and microinstructions are read from the floppy disk and sent to the DI interface 20 as a diagnostic command.
The results are sent to the diagnostic unit 11 via the console 15.
Create a program that will be displayed on the CRT display device 18 of the computer, and write it together on a floppy disk containing the above procedure and microinstructions.

Then, if necessary, a person can load this program from the FDDI 7 into the operation processor 16, and then key in the symbolic name of the register to be read or written from the keyboard 19.

For example, for the two examples in @, you only need to key in as follows.

R/R,A W/R81012345 The first letters R and W above are READ respectively.

It is an abbreviation for WRITE, and 012345 is an octal representation of the content to be written to R and S.

As R/RA's response: RA=76543 The contents of the RA are displayed as octal numbers.

This not only reduces costs, but also greatly improves operability compared to conventional maintenance panels consisting of switches and lamps.

Also, the advantage of having a diagnostic command that reads the data sent to the data line under the control of the microinstruction as described above is in addition to the reduction in the number of circuits for data transfer as described above. Another advantage is that the address part for specifying the register in the diagnostic command is small, so hardware such as an address decoder is also required, making it economical.

In other words, since the inside of a microprogrammed CPU can usually be freely controlled by microinstructions, the microinstruction register 64 and one of the data registers (in this example, RA72) can be controlled from the diagnostic section as described above. By making it possible to write directly and giving microinstructions using the appropriate procedure described above, it is possible to arbitrarily write to the 10-odd registers within the CPU.

Next, with reference to FIGS. 5 and 6, the operation when a diagnostic command is received by the diagnostic section 11 from the DI interface 20 and executed will be described.

First, a case will be described in which the diagnostic command instructs to send 4 bytes of data to the microinstruction register.

The control circuit 52 in standby state is the DI interface 2
When the first byte sent from 0, that is, the command part, is received, it is stored in the command register 48 via the receiver 42 and selector 47.

The first pit of this command part is 1 and the last pit is 2.
Knowing that the bit is O and that it is a write type command, it receives 5 bytes from the DI interface and sequentially sends them to RDA49, RDDo, RDD.
□, RDD2. It is controlled to enter into RDD3.

As a result, the contents of RDA and RDD are changed to inverters 53 and 55.
As shown in FIG. 6, the data is sent to various parts within the CPU.

Next, the control circuit 52 sends the control signal to a decoder 61 (FIG. 6).
A control signal is sent to the selector 63 to select the RDD as a remote control, and a control signal is sent to the microinstruction register 64 to cause the selector 63 to select the RDD.
A control signal is sent to write the output of .

As a result, the 4 messages sent from the DI interface
This means that the byte of data has been written to the microinstruction register 64.

Since the execution of the diagnostic command is now complete, the control circuit 52 returns to the standby state.

Next, a case will be described in which a diagnostic command is given from the operating processor to read the contents of the RCNT 74 as 1-byte data.

The control circuit 52 in the standby state is the DI interface 2.
When the first byte sent from 0, that is, the command part, is received, it is stored in the command register 48 via the receiver 42 and selector 47.

Knowing that the first bit of this command part is 1 and that it is a data read type command, first receive one more byte from the DI interface 20 and write λ to the RDA register 49 in the same way as the command part. After that, it moves on to data reading operation.

That is, the contents of the RDA register 49 point to the RCNT 74, thereby configuring the diagnostic bus ZDSPY.

At this time, only the selector 79 among the selectors is activated, and the outputs of all other selectors are in a high impedance state so that they do not affect the data on the diagnostic bus ZDSPY, and the selector 79 selects the RCNT74 as an input. , operates to put its contents on the diagnostic bus ZDSPY.

While selecting the diagnostic bus ZDSPY as described above, the control circuit 52 controls the selector 74 in FIG.
After writing the constant into the 1.2 byte, the selector 47 was used to select ZDSPY as the λ data, and the driver 41 was activated to output the value of ZDGX, that is, the value previously output on the diagnostic bus. Sends the contents of RCNr 74 to DI interface 20.

While sending the data to the DI interface 20, the control circuit 52 also writes the data to the third byte of the RDD register 50.

(The purpose of sending the data read by the diagnostic command to the operating processor and also writing it to the RDD register 50 will be explained later.

) The above explanation describes the case where the last two bits of the command part of the read type diagnostic command are 3, that is, the case of a diagnostic command that reads 1 byte of data, but generally speaking, the last two bits of the command part are n. In the case of a read-type command, i.e., sending (4-n) bytes of data to the operating processor, the data is written from the nth byte to the third byte of the RDD register 50, and the data is written to the remaining RDD registers. Byte is written with zero.

Next, the operation when reading data from data line ZC will be explained using reading from register RA72 as an example.

In this case, the operating processor 16 includes a two-step procedure: a first step of writing a microinstruction according to its purpose into the microinstruction register 64, and a second step of reading data from the data line ZC. It has already been mentioned that diagnostic commands are sent to the CPU.

Since the operation of the first step (writing to the microinstruction register) has already been explained, here we will explain how the microinstruction that sends the contents of the RA register 72 to the ZC is written to the microinstruction register 64 as described above. Let's start the explanation.

The microinstruction is decoded by decoder 68 and energizes several control lines (not shown), resulting in selector 75 selecting register RA 72 as an input and ALU 77
The λ power, that is, the output of the selector 75 is directly output as the output of the ALU 77, and the selector 78 selects the ALU 77 as an input.

As a result, the contents of the RA register 72 are changed to the selector 78ZC.
is sent out as the output of

Next, the operation processor 16 performs the second step λ
Let us assume that we have entered the stage of issuing a diagnostic command to read the resorter line ZC, and have entered the operation of reading 4 bytes of data from the ZC.

Since the transfer operations of the command section and address section are the same as those for other commands, the explanation will be omitted and the explanation will be given to the operation of data transfer.

Look at the address part stored in the RDA register 49 (RD
(The connection from A register 49 to control circuit 52 is not shown.) Control circuit 52 knows that the diagnostic command is to read ZC and selects selector 56 to select ZCo,1.
and also controls the selector 47 to select ZDGTo.

That is, the RA register 72 that has already appeared on the data line ZC.
The 0th byte of the contents of is copied to the RDD register 50 and driver 41 through the selector 56 and selector 47, and is sent to the DI interface through the driver 41 as the first byte of data. It is also written to the 0th byte of

Next, the selector 47 controls to select ZDGTl, sends the first byte of the contents of the RA register 72 to the DI interface 20, and also writes 1 (the first byte of the DD register 50).

Next, the selector 56 is controlled to select ZC2 and ZC3, and the selector 47 is controlled to select ZDGT o to select the second byte of the contents of the RA register, and then ZDGT. The selector 47 is controlled to select the third byte of the contents of the RA-register, and the third byte of the contents of the RA-register is sequentially sent to the DI interface 20 and written to the corresponding byte 1 of the RDD register 50.

In this way, the contents of any register can be retrieved from the operating processor 16 by using microinstructions to put the contents of any register on the data line, and then by issuing a diagnostic command that reads the data on that data line. I can read it.

In other words, although the two types of snooping commands only directly access two locations in the CPU (microinstruction register and data line ZC), by using appropriate microinstructions and procedures as described above, the CPU internal information can be accessed directly. The contents of the register on the tens side can be read.

Next, we will explain the operation when writing data to the address pointed to by R and CNT 74 of the scratchpad memory 73. Register R
Write to A72.

Step 2: Write a microinstruction instructing "1-Write the contents of the RA register 72 to the scratch pad memory 73" to the micro gospel register.

Step 3: Move the CPU by one step.

This will be carried out in three steps.

It is no longer necessary to explain how the diagnostic commands given by the operation processor 16 to execute the first and second steps are executed, and the command part address part of the diagnostic command for the third step is received. Only the subsequent operation will be explained with reference to FIG.

The control circuit 52 knows that this command does not have a data section because the first bit of the diagnostic command section is zero, and when it completes receiving the address section, the control circuit 52 starts executing the command. Control unit (not shown)
An execution start signal and an execution start signal are both sent to.

In response to this, the main control section generates a clock for l logic and then stops, so the microinstruction given by the second logic is executed, and as a result, predetermined data is written to the scratch pad memory 73. It will be.

The explanation on the ground is RCNTγ in the scratchpad memory 73.
The explanation has been given for the case where the address pointed to by RCNT7jH,: is written, but in order to write to an arbitrary address in the scratchpad memory 73, before executing step 1, write the following to RCNT7jH: The target address may be written in the same manner as steps 1 to 3 above.

In the above explanation, the operation of typical examples of diagnostic commands has been explained in detail, but in this embodiment, the types of diagnostic commands shown in Table 1 are provided, so it is easy to use. Regarding each command in Table 1 below, the unique points of each command will be explained based on the operation description of the typical example.

A typical example of the start CPU command is “
This command is almost the same as the "run the CPU by one step" diagnostic command, but the difference is that the control circuit 52 only sends an execution start signal to the main control circuit.

Therefore, by giving this start CPU command, the operation of the CPU can be started.

The step CPU command is C only for the l-1 step mentioned above.
This is the diagnostic command itself "to move the PU."

It should be noted that this command is also used to stop the CPU in operation.

The main control circuit of the CPU in this example is designed to ignore the execution start signal given during CPU operation, so it can be used in this way.

The details of the operation of the two commands of the CPU 1 and 7" can be found in the test mode register RTM (Fig. 51).
).

The RTM register 51 is a register that determines the general test mode, and can specify address stop mode, single step mode, etc.
It also has the function of specifying that the operation of ``putting the microinstruction stored at the specified address in the control memory into the microinstruction register'' performed in the process of executing the start CPU1 step CPU diagnostic command is to be suppressed.

The above example describes the case where this suppression function is working, and when the suppression function is not working, the microinstruction is executed from the control memory address specified by the command part pits 4 to 8 and the address part of the diagnostic command. After reading out and putting it into the microinstruction register, an execution start signal (and an execution stop signal in the case of a step CPU command) is given to the main control circuit as described above.

(Tess) CPU commands will be explained later.

The microinstruction read command is almost the same as the start CPU command; the difference is that no execution start signal is sent to the main control circuit.

This command is used to read microinstructions from control store 62 and place them into microinstruction register 64.

The data read command operates slightly depending on the values of command part bits 4 to 5.

The operation explained in the above typical example is the normal data read command.

The address portion is used to identify (address) registers, diagnostic buses, data lines, etc.

The registers specified by this command are the registers (including memory) directly connected to the selector 47 or 56 in FIG.
, RTM51.

RPMA, 45, and II (and DMA (not shown)) and a large number of registers within the CPU are read primarily through the data line ZC as described above, so they cannot be specified from the diagnostic command. do not have.

As mentioned above, by not specifying it in the diagnostic command, the cost can be reduced and one of the objects of the present invention can be achieved.

The SBPs in Table 1 have already been explained in connection with FIG.

The register file read command is a command that makes reading convenient by giving the address of a register file (not shown) in the CPU, and can be used for diagnosis after writing a microinstruction to the microinstruction register in advance. Part 1
1 reads its output via the data line ZC, and has no essential difference from a normal data write command.

The normal data write command has already been described as a typical example.

Not only registers but also memory (for example, RPMJ6 in Figure 5)
The control memory 62) in FIG. 5 can also be specified as a target.

Unlike the normal data write command, the RDDtF write command uses the contents of the RDD register 50 as is as data for this command, and does not transfer the data portion on the DI interface.

Used to write data read by a previous data read command to a register (including memory).

When sending data to the DI interface when executing a data read diagnostic command, the data is sent to the RDD at the same time.
This is the purpose of writing to register 50 as well.

The main memory read command differs from the data read command in that after sending a read instruction together with the address to the main memory 13, data transfer is started after waiting for the main memory to complete its operation.

The diagnostic section 11 reads data via the data line ZC.

A part of the main memory address is given from the address part of the command, but the remaining part is given by the address register RDMA,
(not shown).

Before executing the main memory read command, write the necessary address/information to the RDMA register.

When a main memory read command is executed, the RDMA register counts up, making it convenient to read consecutive addresses.

The main memory write command differs from the data write command in that it sends an address and a write instruction for the received data to the main memory.

The commands described above instruct basic operations commonly used in failure diagnosis, maintenance work, firmware loading failure detection, and the like.

Next, we will explain how these diagnostic commands are used for the various purposes mentioned above.

First, regarding fault diagnosis, a so-called micro-diagnosis method has been established for a long time.
Executing the microinstructions (using step CPU commands) and reading the results can be instructed from the operational processor 16 via these diagnostic commands, and the diagnostic procedure can be executed by the operational processor 16 as a microprocessor application device. It is clear that these diagnostic commands are sufficient for the purpose of fault diagnosis.

As mentioned above, maintenance work can also be performed with ease by sending diagnostic commands via the operation processor.

Firmware loading is performed using the microinstruction register 64, control store 62, and control store address register (
It is clear that this can be done using a data write diagnostic command that targets (not shown).

It is also clear that just as fault diagnosis can be implemented using diagnostic commands as described above, fault detection can also be implemented.

Note that RPMJ 6 in FIG. 5 is a memory for storing the failure detection procedure as a diagnostic command string.

Although the case where the control entity of the diagnostic unit is the operating processor has been mainly described above, it will be shown below that other control entities can also be easily connected.

The output of the RPM46 is connected to the selector 41 in FIG. 5, and the output of the selector 56 is connected to the λ power of the RPMJ6. Also, the output of selector 56 is set to RPMA4.
5, the output of the RPMA 45 is connected to the input of the selector 56, respectively.

The control circuit 52 includes one flip-flop FRPM (
(not shown), so that when FRPM is set, the selector 47 selects RPMJ 6 instead of selecting ZDGZ, and also stops waiting for data reception from the DI interface 20 and instead Counter RPMA4
The control circuit 52 is changed to count up 5 and stop operating the driver 41 to send data to the DI interface 20.

The CPU failure detection procedure is stored in RPMJ6 as a string of diagnostic commands, and RPMJ45 is set to a predetermined value (
For example, after setting the FRPM to
When set, a diagnostic command is read from the RPMJ 6 and executed as if it were given by the operating processor 16, and as soon as execution is complete, the next diagnostic command is read from the RPMJ 6 and executed.

In this way the fault detection procedure can be carried out in a short time.

The test CPU commands in Table 1 above are those provided to control this RPMJ 6 and related circuits.

When the stop test command is executed, the control circuit 52 resets the PRPM flip-flop.

This command is used to stop reading diagnostic commands from RPMJ6 at the end of the diagnostic command string stored in RPMJ6.

The intra-test branch command does nothing when the zero detector (not shown) of the CPU detects zero and moves on to reading the next diagnostic command, and when the zero detector (not shown) of the CPU detects zero, it moves to reading the next diagnostic command. The selector 56 is controlled to select registers 4B and 49, and the output of the selector 56 is controlled to RPM.
By controlling to write to J45, RPMtb
The diagnostic command sequence branches at l'5.

This is a command whose main purpose is to determine the presence or absence of a failure, and is, so to speak, a conditional branch instruction in the diagnostic command sequence within the RPM.

When the start test command is executed, the control circuit 52 returns the address of RPMJ6 given as described above to RP.
After writing to MJ45, set the PRPM.

As a result, execution of the diagnostic command string stored in RPMJ6 is started.

This is used to instruct the operation processor 16 to start executing the diagnostic command string in the RPM, and also
It is also used as an unconditional jump for diagnostic commands in the diagnostic command sequence.

In addition to being used to store failure detection procedures, RPMJ6 is also used in the following cases, and has high utility value.

One example is when maintenance must be performed using an oscilloscope, and in this case it is necessary to make CPU10 repeatedly perform the same operation at high speed, but the RP
This can be easily realized by storing a diagnostic command instructing the MJ6 to perform this operation, creating a loop using the unconditional jump command (start test command), and executing it.

Another example is when a fault diagnosis program is applied to faults that occur intermittently, so-called intermittent faults, and a part of the fault diagnosis program is stored in RPMJ6 and the same loop is repeated at high speed. The probability that a splitting fault will be diagnosed can be increased by having the system run.

It is also used when it is necessary to repeatedly execute a part of a fault diagnosis program and observe it with an oscilloscope.

In addition, this embodiment has a small panel (basic panel) that allows a human to operate the diagnostic section even when the DI interface or operation processor fails, and FIG. 5 shows the diagnostic section and basic panel. connections are shown.

The basic panel basically has 2 bytes of switches, 1 byte of display, and 5E of DI interface.
It is equipped with a push button that generates a signal equivalent to the LECT signal.

In this way, it is easy to add and connect a new control entity to this diagnostic unit.

As described above, the present invention provides a highly versatile and economical hardware configuration system that can be commonly used for various purposes to improve maintainability and availability.

Further, the present invention provides a highly operable and economical device for displaying the internal state of an information processing device to a human and changing the internal state of the information processing device according to instructions from the human.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of an information processing system to which the present invention is applied, FIG. 2 is a signal line configuration diagram of an inter-device interface suitable for transferring diagnostic commands related to the present invention, and FIG. Schematic timing diagram of interfaces in Figure 2,
FIG. 4 is a diagram showing the format of a diagnostic command related to the present invention;
FIG. 5 and FIG. 6 are diagrams showing one embodiment of the present invention. 10...CPU, 11...Diagnosis section, 1
5... Operation console, 16... Operation processor, 47° 56... Selector, 48.
...Command register, 49...Address register, 50...Data register, 52.
...Control circuit.

Claims (1)

[Scope of Claims] 1. In a microprogram control type information processing device having a main storage device, a control storage device for storing a microprogram, and a microinstruction register for storing microinstructions read from the control storage device, an interface for connecting to an external processor having the capability of An information processing device comprising means for executing the following steps: writing an arbitrary microinstruction into an instruction register; b. specifying a data line to be used for information processing and reading data on the data line; c. starting information processing. 2. The information processing apparatus according to claim 1, wherein the number of signal lines of the interface through which command signals are transferred from an external processor is smaller than the total number of bits of the command signals. 3. In the information processing according to claim 1, the number of signal lines of the interface through which command signals are transferred from an external processor is smaller than the number of bits of a microinstruction register in the information processing device. Information processing device. 4. In the information processing device according to claim 1, the external processor controls a man-machine interface, and transmits a command signal to the information processing device in response to an instruction issued by a human through the man-machine interface. An information processing device characterized by: 5% Permissible In the information processing device according to claim 4, the external processor is an operation console having a built-in operation processor, and data stored in various devices within the information processing device is read from the operation console. case,
An information processing device characterized in that by keying in a command including a symbolic name of the device to be read from a keyboard device of an operation console, the command is transferred to the information processing device as a command under control of the operation processor. 6% Allowance In the information processing device according to claim 4, the external processor is an operation console incorporating an operation processor, and when writing data from the operation console to various devices in the information processing device, the operation console Information processing characterized in that by keying in a command including a symbolic name of the device to be written and data from a keyboard device, the command is transferred to the information processing device as a command under the control of the operation processor. Device. γ In the information processing device according to claim 1, the information processing device includes a plurality of registers for storing commands transferred via an interface, and a command initially stored in a part of the registers. a control circuit for controlling the information processing device according to the internal state of the data processing unit; a means for storing in the register an address part and a data part to be taken over and transferred via the interface based on the judgment of the control circuit; an information processing apparatus, further comprising means for transferring the data to various registers to which outputs of the register storing the data are connected. 8. In the information processing device according to claim 5, when a write operation is performed on a device that cannot perform a direct write operation by a write command transferred from an external processor, the write operation is first made possible by the write command. writes data to a register, then writes a microinstruction indicating the steps necessary to write the data in the register to the device in a microinstruction register that can be directly written by a write command, and further executes the microinstruction. An information processing device characterized in that the write operation is performed by performing steps. 9% Allowance In the information processing device according to claim 6, the read operation of the device which cannot perform a direct read operation by a read command transferred from an external processor is first performed by a direct write operation by a write command. Write a microinstruction in a capable microinstruction register indicating the steps required to output the contents of the device onto the data line, and then read the outputted data on the data line by a read command and read the outputted data on the data line via the interface. An information processing device characterized by outputting information to an external processor. 10 In the information processing device according to claim 1, the information processing device includes a plurality of registers for storing commands sent from the interface, and a command section initially stored in a portion of the registers. A control circuit that controls the inside of the information processing device in response to the contents, and data in various memories and various registers in the information processing device is transferred onto a diagnostic bus and a data line that are indirectly connected to the interface. An information processing device comprising: means. 11 In the information processing device according to claim 10, if the command signal transferred from the external processor is a read command, the information processing device transfers the command signal onto the diagnostic bus based on the control of the control circuit. An information processing device characterized in that the contents of various registers are read and output to an external processor via an interface. 12 In the information processing apparatus according to claim 2, the information processing apparatus determines the type of command information based on the first command part of the command information transferred from the external processor via the interface. 1. An information processing device, comprising: control means for determining the address to be transferred via the takeover interface and storing the address transferred via the takeover interface in a register within the information processing device. 13. The information processing device according to claim 1, which has a register write command for a plurality of registers storing commands, and sends the read data with the data read command to an external processor and also stores it in the register. . An information processing apparatus, wherein the register write command writes data stored in the register to a device specified by an address field without receiving a data field from an external processor. 14. The information processing apparatus according to claim 1, further comprising: a dedicated memory storing a failure detection procedure in a command format; a counter for counting addresses of the dedicated memory; and a command signal from an external processor. An information processing device comprising: means for activating a dedicated memory; and means for controlling a control storage device to execute a fault detection microprogram by addressing a control storage device with data read from the dedicated memory. .