CS217865B1 - Connection for measuring time, length or other one-dimensional quantities - Google Patents

Abstract

The invention represents a connection for measuring Saš, length or other one-dimensional quantities, especially in single-purpose automatic control systems. The essence of the invention lies in connecting the counter with an additional logic network via a bus connecting individual bit outputs with a system of coincidence circuits equipped with a variable preselection. The actual additional logic network further consists of a system of input memory circuits connected to these coincidence circuits and interconnected via gates with output memory circuits. . The result of the measurement is a logical signal Zjj indicating the inclusion of the measured quantity in the assigned interval delimited in advance by means of the aforementioned preselection.

Description

The present invention relates to a circuit for measuring the sash, length or other one-dimensional quantities with applications in the field of control systems with higher accuracy requirements and with particular demands on the simplicity and clarity of the measurement results displayed by logical signals. This is a digital measurement based on the fact that, for example, the total length measured consists of elementary length units converted into electrical pulses. By adding these pulses the resulting value of the measured quantity is reached.

The known measurement of one-dimensional quantities consists in simple addition of specific pulses corresponding to elementary sections of unit length. The result of the measurement is an accurate digital, eg a several-digit indication of the measured quantity in the decimal system. In automatic control systems, this is not always satisfactory, it is often desirable to provide a simple, for example, a logical signal for immediate decision-making on the next step in the sequence of manufacturing operations, for example resulting from a comparison with a preset value. If the measured value of the preset value is reached, the signal should be formed, for example, in the form of a logical one and the presence of such a signal within a predetermined time interval should release the course of the next sequence of the aforementioned manufacturing operations.

Disadvantages of the known measuring methods are eliminated in the field of use for measuring time, length or other one-dimensional variables according to the invention composed of a counter and an additional logical network, which consists in that the counter outputs of the counter are connected via bus to inputs of coincidence circuits they are connected to the recording inputs of the input memory circuits.

The outputs of the coincidence circuits are further coupled to the lubrication inputs of the input memory circuits such that the output of the second coincidence circuit is coupled to the lubrication input of the first input memory circuit, the output of the third coincidence circuit is coupled to connected to the erase input of the previous memory circuit.

The input memory circuits are provided with direct outputs and inverse outputs associated with the gate inputs, and the outputs of these gateways are connected to the recording inputs of the output memory circuits.

The advantage of wiring to the measurement of time, length or other one-dimensional variables according to the invention is to display the result of a single measurement in the form of a logical signal at the output of the additional logical network. Each measurement is continuously compared with predetermined limit values. and the instantaneous position of the measured quantity within the span of a particular sub-interval is zebraed by a logic signal at the respective output of the additional logical network.

The circuit for measuring time, length or other one-dimensional variables according to the invention is shown in the attached drawing in an exemplary embodiment, wherein Fig. 1 represents the basic form of this circuit, Fig. 2 represents the input memory circuit inputs, and Fig. gates with output memory circuits.

FIG. 1 shows a counter 8 with a working input 8, with a reset input 62, with an output p. The serial outputs of this counter are connected via the bus 6 to the inputs of the first coincidence circuit gj, the second coincidence circuit of the third coincidence circuit, etc., of the next coincidence circuit 51j.

The output of the first coincidence circuit is connected to the recording input of a first input circuit pamělového P ,, the second output of the coincidence circuit ₂ & 3 · ^{P 88} ° 3 ^en recording input * p ₂ of the second input circuit pamělového P _2, the third output of the coincidence circuit is connected to the _three with the recording input 2e _{3 of the} third input memory circuit £ ₃ , etc., the output of the next coincidence circuit is connected to the recording input * of the other input memory circuit £ _N · Recording inputs ² p | . ^ Pn. ^ Pj. ···, ² Pjj pamšlových circuitry £ ,, £ ₂ 2 _3> ··· »· ji ^{in Figure} 1 are unconnected.

In FIG. 2, the outputs of the coincidence circuits K1, K1, K1, ..., Jj are connected to the lubrication inputs Pj. P ₂ . Pj input memory circuits P £ £ _2, £ ₃ so that the output of the second circuit _K2 koincidenřnlho 3® connected both with the recording input * ρ ₂ of the second input circuit pamělového P _2, and with the lubricant entering the first input circuit pamělového £ ,, output third koincidenšního circuit K is connected both with the recording input ^ p ^ third input memory circuit P ^, and with the lubricant inlet ² Pg second input pamělového circuit £ _2, etc., the output of the next koincidenšního circuit to _n is connected both to the recording input ^ p ^ of another input memory circuit P _K , and on the other hand with the erase input ² Pj of the previous, for example, third input memory circuit P ^. The erase input ² p, j of the other input memory circuit Pjj is not connected.

FIG. 2 shows the lubrication inlets ² ?. ² Pg. ^ ^p 3 · ···> eji the input memory circuits Pj, £ ₂ , £ ₃ ..... £ _n connected to the first line Eq · These memory circuits are equipped with

2 2 2 direct outputs P ₁ , ££ ₂ · Pj. .... P _H connected to gate inputs £, flg, ^, ..., _{N N} such that the inverse output ² P prvního of the first input memory circuit j is connected to the first input h h of the first gate ,,. direct output Jj? _Two second input pamělového £ circuit ₂ is connected to a second input of the first gate output inverse H ,, £]? _Two second pamělového circuit £ ₂ is connected to the first input-hg second gate £ _2, the direct output 'p ^ third input pamělo2 2-dumping circuit P ^ is coupled to the second input hg second gate £ ₂ inverse output Pj third input pamělového circuit connected to the first entrance ^hj of the third gate jj, etc.,

2, the direct output Pjj of the next input circuit Pjj is connected to the second input hj of the previous, for example, third gate Hj, the inverse output ² Pjj of the next input memory circuit Pjj 12 is coupled to the first input - ^ N of the next gate. The second input h _{H of the} next gate £ _N is not connected.

The third inputs 31 ' ··· ´ other gates H ,, H ^., ..., £ jj are connected to the second line £ θ.

The output of the first gate £ is connected with the recording input of a first output circuit pamělového R ,, £ output of the second gate ₂ is connected to a recording input * r ₂ of the second output circuit pamělového £ _2, the output of the third gate £ ^ is connected to a recording input 'r ^ of the third output memory circuit R ^, etc., the output of the next gate 6 is coupled to the recording input \ γ _{μ of} another output memory circuit

Lubrication inlets, ² rg. ^The output memory circuits 8, 8, 8, 8, 8 are connected to a third line 8g.

counter £ represents the pulse counter arriving at the working input,. When added to the nominal capacity, a pulse is output at the output of the counter. By applying a signal to the reset input £, the counter then goes to the reset state.

The outputs of individual stages of £ counters, for example, direct and inverse bit outputs of these stages are connected to the bus and £ connected to the inputs of the coincidence circuits JC ,, & ₂ £ 31 ***% ·

The coincidence circuit is essentially a logic product circuit with direct or inverse inputs, supplemented, for example, by a controller for connecting the direct or inverse outputs of the individual counter stages, depending on the logical value of the signals on the individual bit outputs when the preset thresholds are made.

The memory circuit is a flip-flop with a recording input and a lubrication input, for example an R-S flip-flop.

The gate is considered to be a combinational logic circuit with the function of logical sum, based on direct or inverse inputs. For example, in the circuit shown in FIG. 3, the logic function is represented by the equation:

or where ^H i ⁼ ' ^h i ^{&& 3h} i ^H i' ^2p i ^{& 1p} i ₊ i ^{& h} o, (1) (2) i '1.2, 3,

N-1

The function of the wiring to measure time, length or other one-dimensional quantities in the exemplary embodiment according to the attached drawing is as follows: By default, the counter counter is assumed to be zero · During measurement, for example the pulses are input into the working input and the counter 8 gradually reads them. At the time when the counter state shod coincides with the preselection of the individual coincidence circuits 2, 3 3, ^ 3 ´ ··· —N, evaluation pulses are generated at the outputs of these circuits. For example, by numerically distributing the total measurement range by preselecting each coincidence circuit according to the table

- 15

K ₂ - 30

K ₃ - 45 (3) * 11 to 90 obtained after the arrival of the 15 pulses on labor input £, the signal at the output of the first koincidenčnlho circuit, after the arrival of 30 pulses the signal at the output of the coincidence circuit £ _2, after the arrival of the 45 pulses the signal at the output of the third coincidence circuit Kj, etc. upon the arrival of 90 pulses, a signal is output at the output of another coincidence circuit

The signal produced by the evaluation of the state at the output of one of said coincidence circuits (i = 1, 2, 3, ..., N) passes to the recording input * of the connected input memory circuit P1 and causes recording to this memory circuit. Obviously, with continuous counting of the specific pulses, the signals are recorded in sequential order in the individual memory circuits P ^ until the measurement is complete. For example, with the energized state of the first input memory circuit P1 and the energized state of the second input memory circuit Pg at the end of the measurement, the measured quantity is in the range of 30 to 45 units of measurement, i.e.. is within the interval

Of ₂ 5 <15, 45 (4)

Generally, the measured quantity is in the range of the interval Ζ ₄ , if at the end of the measurement the mathematical-logical relation holds:

^Z i “ ^p i ^{& Ρ} Ϊ7, ^{= 1 (5)}

In the circuit shown in FIG. 2, when recording to an individual input memory circuit, the previous input memory circuit is also cleared, since the same recording signal is simultaneously transferred to the erase input of that input memory circuit.

In the circuit of FIG. 3, by applying a signal to the first line, all connected input memory circuits P1 are erased.

Interconnection of the input memory circuits P ^ with the output memory circuits R ^ via gates allows to evaluate the state of the measurement in the form of logic signal 1 of N according to the modified relation (5) as follows or at the end of the measurement as follows: _

Z = R = ² Pi * ¹ P _{i +} , h _{Q (11)}

By applying a signal to the third line, all the connected output memory circuits R1 are deleted.

The distribution of the overall measuring range can be uniform, uneven, with overlap, with selective preselection of selected sub intervals, etc.

Obviously, the result of the measurement, for example at the moment of transition of the individual measured object to the measuring point, immediately results in one logical signal, which also allows an immediate decision on further production process, assignment of the movement path, etc.

The circuitry for measuring the time, length or other one-dimensional quantities according to the invention is used in single-purpose automatic control systems of the production section, for example in rolling mills.

Claims (3)

SUBJECT OF THE INVENTION 1. Circuit arrangement for measuring time, length, or other one-dimensional variables composed of a counter and additional logical network, wherein the order of outputs of the counter (C) are the means of ^six prostřed217865 bus (S) to an input koincideněních circuits (K K₁, K₂, K ^, ..., K ^), whose outputs are connected to the recording inputs ('p ,, ¹ p2, ¹ Pj, ...,' ρΝ) of the input memory circuits (P ,, Pg, P ^, ··· > · 2. Connection according to claim 1, characterized in that the outputs of coincidence circuits (Κ ,, Kg, Kp ..., Kjj) are further connected to the lubrication inputs of the input memory circuits (Ρ ,, Pg, Pj, ..., Pjj) such that the output of the second coincidence circuit (Kg) is connected to the erase input (2pj) of the first input memory circuit (P1), the output of the third coincidence circuit (Kg) is connected to the erase input (pg) ), the second input of the memory circuit (P _2), and etc., a further output of the coincidence pbvodu (Ki) is connected to the input of lubricant prior pamělového circuit. 3. Connection according to claim 1, characterized in that the input memory circuits (Pj, Pg, Pj ..... 112 1 2 2 P _N ) are equipped with direct outputs (P ,, Pg, Pj ..... P _N ) and inverse outputs (P ,, Pg, 2 2 P.}, ..., Pjj) associated with gate inputs (Hj, Hg, Hj, ..., Hjj) and the outputs of these gates are associated with recording inputs ('r ^' rg, 'r ^, ... , 'rjj) output memory circuits (Rp Rg, Rj, .. ·, Rjj) ·