CS201649B1 - Connection of terminal processor - Google Patents

Description

These drawbacks are overcome by the wiring of the terminal processor according to the invention, which is based on the instruction input being connected to a first input of a multiplexer having a peripheral information input and a peripheral status information input, the multiplexer output being connected to the first input of the arithmetic-logical unit. a shift and buffer register input, the output bus of which is connected to the input of the inverter, a register of peripheral control states, a register of peripheral addresses, a flip-flop for controlling peripheral, a flip-flop for generating synchronization pulses of output data, input of program counter buffer register, with lower part of program counter, with first input of higher part of program counter, output of accumulator is connected to data bus connected to fourth input of multiplexer, outputs of lower part STI and an upper portion of the program counter are connected to the address bus to which are connected memory výstupy.zápisníkové fifth input to the multiplexer, the second input of arithmetic logic unit, which is mutually interconnected with the transfer circuit.

It is also advantageous to make the connection arranged between the address bus and the program bus

201 649

The 201 049 counter is connected to the second scratchpad.

The wiring according to the invention is advantageous in that it is fast immersing with considerable simplification. It also allows all operations required for Internet processing.

One embodiment of the circuit according to the invention is shown in the drawing, which is a block diagram of the entire circuit.

The connection is made so that the instruction input 1 is connected to the first input of the multiplaxor 2 / equipped with the input 2 of the peripheral information and the input 2 of the state internals of the peripheral, the output of the multiplexer 6 being connected to the first input of the and a buffer register from which the output bus 22 is connected to the ticket latch 8 and / reg1střen 12 control states of the periphery, with registers · U addresses periphery, and flip · perimeter · 12 for the periphery of the flip · obvoden 12 P ^P ° generating synchronization The output data pulses, with the input of the scratch pad 2, with the input of the buffer register 18 of the program counter 2g. with lower part 12 of the program counter 3.8. with the first input of the upper part 12 of the program counter 28. wherein the output of the inverter 8 is connected to the data bus ly connected to the fourth input of the multiplexer 1, the outputs of the lower part 12 and the higher part 12 of the program counter 21 are connected and the address bus 18 to which they are connected the outputs of the scratchpad 2 * the fifth input of the multiplexer 2 (the second input of the Arctic-Logic unit 2) which is mutually interconnected and the circuit 2 for transmission.

The Hultlplexor 2 further includes Input 1 Instruction, Input 2 Peripheral Information and Input 2 Status Peripheral Information.

The data bus 16 forms an output 21 to the panes and an output 21 to the peripheral. O bus 22 is connected to the registry IQ control states periphery and output 12 to register the case addresses the periphery of the outlet 21 / to klopnénu circuit 12 P ^ro driven the periphery of the outlet 21 / ^to klopnénu circuit 12 for generating a sync pulse output data to the output of 21> the scratchpad input 2 · the scratchpad 2 ^88, for example, stores from sixteen registers divided into two groups of 16-bit addressing to odd registers 201 "211/212/101 / til, tli, 211 · even registers 211 / ifilz tS2 * 212/211 / 211/212 It is also advantageous to connect a modified notebook so that a second scratchpad 2i is connected via the address bus 18 the program counter 21J *.

The wiring works as follows: Type Information selected nultlplexoren 2 ⁸⁸ supplies to the input of the ARM 2 / whose second input is the information from the scratchpad 2 or the program counter 21 · the higher counter 12 and the lower counter 12 and the transmission value stored in the circuit 8 for transmission. The information processed according to the selected function of the arithmetic-logic unit 2 is applied to the input of the shift register Z, which serves both as a buffer register and as a shift register for the same rotation. The output of this register ^{8 of the} output bus 21 is distributed to the inputs of the various wiring blocks: stack 8 / scratchpad 2 / control status register perlfe r11, register of peripheral addresses, buffer register 12, flip-flop 12 for control pe r1fer11, flip-flop 18 for generating synchronization pulses of the output data, the program counter 21 ^{8 of the} higher part 12 of this counter and the lower part 12 of this counter. Data bus output 8 from inverter 8 ⁸ common address bus output 18 of program counter 21> higher part a and lower part 12 and scratchpad 2 are fed as input information to nultlplexer 2 together with resource information from peripheral to input 2 / status sources Information to input ^2/88 source Instruction from keyboard or memory to input 1 of multiplexer 2 ·

201 049

The circuitry can be used to collect, process and sort data, and in particular to control telecommunica- tion processes and others.

Claims (2)

SUBJECT OF THE INVENTION A terminal processor circuit, characterized in that the input (1) of the instruction is connected to a first input of the Z 4 Z multiplexers provided with an input (2 Z of peripheral information) and an input (3) of state information of peripherals, it is connected to the first input of the Z5 Z arithmetic-logic unit, whose output is connected to the input of the Z 7 Z shift and buffer register, whose Z 24 Z output bus is connected to the Z 8 Z inverter input, Z 10 Z register of peripheral control states , with register Z 11 Z of peripheral addresses, with flip-flop Z 15 Z for peripheral control, with flip-flop Z 16 Z for generating synchronization pulses of output data, with notebook entry Z 9 Z, with buffer register Z 12 Z program counter Z 28 Z, with lower part Z 14 Z of program counter Z 28 Z, with first input of higher part Z 13 Z of program counter Z 28 Z, with output of inverter Z 8 Z j connected to the Z 17 Z data bus connected to the fourth input of the Z 4 Z multiplexers, the outputs of the lower part of the Z 14 Z and the higher part of the Z 13 Z of the program counter Z 28 Z are connected to the address bus Z 18 Z. Z 9 Z, the fifth input of the multiplexers Z 4 Z, the second input of the ar1tmet1cko-logic unit Z 5 Z, which is mutually connected with the Z 6 Z circuit for transmission. 2. Terminal processor connection according to claim 1, characterized in that a second scratchpad { Z 27 Z.