CS201591B1 - Connection for releasing the passage of signals - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention relates to a circuit for the release of signals, in systems of electrical, pneumatic or hydraulic logic networks, with particular regard to the variability of this release.

Known connections solve the release of signals from inputs always to assigned outputs, this assignment is determined by the composition and connection of the used logic network. It is for example to release the passage of signals according to the time order of their origin, according to the master and subordinate arrangement of inputs and the like.

The disadvantage of this circuit is a fixed predetermined law of this release, for example the release of only one signal from one input to the assigned circuit output according to the time order, according to the hierarchical arrangement of the inputs by the like.

These drawbacks are eliminated by a circuit for releasing the passage of a set of N inputs and N outputs and a set of K control inputs, where N, K are natural numbers, the nature of which is that the first wiring input is connected to the first gate input whose output it is connected to the first wiring output, the second wiring input is connected to the second gate input, which is connected to the second wiring output, the third wiring input is connected to the third gate input, the output is connected to the third wiring output, etc. another wiring input is coupled to the input of another gate whose output is coupled to the other wiring output, wherein the wiring control inputs are coupled to the control inputs of these gates so that each elementary input of the individual gate control input is coupled to one control input from the set of wiring control inputs.

A gate is a combination logic circuit with an input, an output, and a control input, wherein the selected logic level signal at the control input releases the passage of the selected logic level signal from the input of that gate to its output. It is assumed that the gate control input consists of several elementary inputs of the control input, with the logical coupling of these elementary inputs according to a combination logic function, for example a logic sum function, a logic product function and the like.

The advantage of the circuit for releasing the passage of the signals according to the invention is the flexibility of the release, or the selection of the release achieved by the signals at the control inputs of the circuit. In doing so, each particular form of this connection provides a set of different solutions for this release, and the choice of the individual solution is already made by the particular choice of signals at the control inputs.

In the exemplary embodiment, the wiring for releasing the signals of the invention is shown in the accompanying drawing, where this wiring is shown for N = 8 wiring inputs and K = 6 wiring control inputs.

Inputs Sj, S ₂ , S ₃ , S ₄ , S ₅ , S ₆ , S ₇ , S ₈ are shown, which are connected via gates H _b H ₂ , H ₃ , H ₄ , H ₅ , Hg, H ₇ H ₈ outputs Xi, X _2, X _3, X _4, X _{5, Χ} β, _X7, Xg connections depending on the index of the same order.

The first input S, the wiring is connected to the input h _{4 of the} first gate H ₄ , whose output is connected to the first output X _{4 of the} wiring, the second input S ₂ wiring is connected to the input h _{2 of the} second gate H ₂ , the output is connected to the second output X ₂ connected third input s ₃ is connected with the input of h ₃ of the third gate H ₃ whose output is connected to the third output X ₃ wiring, etc. eighth input s ₈ is connected with the input of h ₈ eighth gate H ₈ whose output is connected to another output X ₈ wiring.

The control inputs _r15 r ₂ , r ₃ , r ₄ , r ₅ , rg, wiring, which are connected to the control inputs κ ₂ , κ ₃ , κ ₄ , κ- "κ ₆ , κ-, κ ₈ , are also shown H _b H ₂ , H ₃ , H ₄ , H ₅ , H ₈ , H ₇ , H ₈ according to the same order index. These control inputs are triple and consist of three elementary control inputs associated with the wiring control inputs, so that each elementary input is connected to one wiring control input.

With the first control input R ₄ circuit is coupled to a first basic input ¹ κ4 control input κ ± first gate H4 first basic input control input κ3 third gate h3 first basic input-5 control input * 5 The fifth AND gate H5, and first basic input ^L x & control input κ8 of the eighth gate H ₈ .

Connected to the second wiring control input r ₂ is the first elementary input b < _{2 of} control input κ _{2 of the} second gate H ₂ , the first elementary input bii of control input κ _{4 of the} fourth gate H ₄ , the first elementary input ⁴ κ6 of control input xg the first elementary input ^χ κ7 of the control input κ _{7 of the} seventh gate H ₇ .

Connected to the third wiring control input r ₃ is the second elementary input ² κ4 of the control input κι of the first gate H1 (the second elementary input ² κ2 of the control input κ _{2 of the} second gate H ₂ , the second elementary input ² κθ of the control input κθ of the sixth gate Hg) input ² κ _{8 of} control input κ _{8 of the} eighth gate H ₈ .

The fourth control input R ₄ circuit is coupled to the second elementary input ² κ3 control input κ3 third gate H3 second elementary input ² κ4 control input κ ₄ fourth gate H _4, a second basic input ² * 5 control input κ5 fifth gate H5, and the second elementary input ² κ7 of control input κ _{7 of} seventh gate H ₇ .

With the fifth control input R ₅ wiring is connected to the third elemental input ³ XT control input κ3 third gate H3 third basic input ³ κ4 control input κ ₄ fourth gate H _4, and the third basic input ³ _κ β control input κ ₆ of the sixth gate Hg.

The sixth control input R ₆ wiring is connected to the third elemental input ³ κ2 control input κ2 second gate H2, third basic input ³ κ5 control input κ ₅ fifth gate _H5, third basic input ³ κ7 control input κ-j seventh gates H7 and the third elementary input ³ κ8 of the control input κ _{8 of the} eighth gate H _s

The functionality of the release of the signals of FIG. 1 is such that in the initial state, the signal at the first input with connections _4, to the third input connections S ₃ and S ₈ eighth input circuit. For gates opened by the logic product of the signals at the elementary inputs of the control inputs of these gates, the passage of the signals from the wiring inputs to the associated wiring outputs is released as follows:

If a single logic signal is present at the first control input r ₍ wiring, at the third wiring control input r ₃ , at the fifth wiring control input r ₅ , this signal is present at the same time on the first elementary input on the second elementary input ² κι and on the third elementary input ³ κ ₄ κι control input first gate signal H _1, and the passage of the first gate ₄ is H for the signal input S of the first wiring ₄ to the first output X ₄ connections open.

When the signals at the wiring control inputs change, namely the loss of the signal at the fifth wiring control input ₅ and the resulting signal at the sixth wiring control input ₆ , the one logic signal acts on the first elementary input ^χ κ8, on the second elementary input ² xg. the third elementary input ³ κ8 of the control input κ _{8 of the} eighth gate H ₈ , and the passage of this eighth gate Hg is open for the signal from the eighth wiring input Sg to the eighth wiring output Xg.

Upon further change of the signals at the wiring control inputs, the loss of signal at the third control input r _{3 of the} wiring, followed by a signal at the fourth control input r _{4 of the} wiring, a re-generation of the signal at the fifth control input r _{5 of} wiring, The rg circuit causes a one logic signal on the first elementary input bi3, on the second elementary input ² κ3, and on the third elementary input ³ κ3 of the control input κ _{3 of the} third gate H ₃ , and the passage of this third gate H ₃ is for the signal from the third input S ₃ wiring to third output X ₃ wiring open.

It will be appreciated that a signal is present at a single wiring output when a suitable combination of signals is provided at the wiring control inputs and when a signal is applied to the associated wiring input.

Depending on the signal combinations on the wiring control inputs, only one gate is released as previously described, or two or more gates pass simultaneously. For example, when a signal is applied to the first wiring control input ,χ, the third wiring control input r ₃ , the fourth wiring control input r ₄ , and the sixth wiring control input r ₆ , opens the logical product of the signals at the elementary inputs ^ 5, ³ xs of the control input. «5 passage of the fifth gate H5 and logical product of the signals at the elementary inputs ² x8, ³ x _{8 of the} control input passage of the eighth gate H _g . It is obvious that the fifth output _X5 engagement signal is present for the duration of the signal on the fifth input S ₅ wiring and the eighth output _X8 engagement signal is present for the duration of the signal on the eighth input S ₈ diagram, in a range of time action signal at the previously mentioned control inputs r _x , r ₃ , r ₄ , r ₆ wiring.

Similarly, in the extreme case when the signals are applied to all control inputs Γχ, r ₂ , r ₃ , r ₄ , r ₅ , r _{6, the} circuit opens the logical product of the signals at the elementary inputs of the control inputs of all the gates.

For gates opened by the logical sum of signals at the elementary inputs of the control inputs of these gates, the signal

Claims (1)

SUBJECT Wiring for enabling the passage of signals composed of a set of N inputs and N outputs and a set of K control inputs, where N, K are natural numbers, characterized in that the first wiring input (Si) is connected to the input (h ₄ ) of the first gate ((χ ), whose output is connected to the first output (Χχ), the second input (S ₂ ) is connected to the input (h ₂ ) of the second gate (H ₂ ), whose output is connected to the second output (X ₂ ), the third input (S ₃ ) is connected to the input (h ₃ ) of the third gate (H ₃ ), the output of which is connected in parallel from the wiring inputs to the associated wiring outputs as follows: If one logic signal is present at the first control input r _{t of the} wiring, the passage of the first gate Ηχ, the third gate H ₃ , the fifth gate H ₅ and the eighth gate Hg opens. Consistent with the assumed initial state in which the signal is on the first input S1 wiring, on the third input S ₃ wiring and on the eighth input Sg wiring there is a signal on the first output Χχ wiring, on the third output X ₃ wiring and on the eighth output X ₈ wiring. When the signals at the wiring control inputs change, ie the signal disappears at the first wiring control input η and the signal at the sixth wiring control input r ₆ opens, the second gate H ₂ , the fifth gate H ₅ , the seventh gate H ₇ and the eighth gate H ₈ , a signal is present at the eighth output X _{8 of the} wiring. The signal release enable circuitry of the present invention has applications in the field of signal release logic networks, selection of signal transfer through control signals, and the like. with a third output (X ₃ ), and an additional input (S ₄ to S ₈ ) is connected to an input (h ₄ to h ₈ ) of another gate (H ₄ to Hg) whose output is connected to another output (X ₄ to X ₈ ), the control inputs (r _b r ₂ , r ₃ , ..., r ₆ ) are connected to the control inputs (χχ, κ ₂ , κ ₃ , ..., κ ₈ ) of these gates (Ηχ, Η ₂ , Η ₃ , ..., Η ₈ ), where each elementary input (bq, ² χχ, ³ χχ) of the single control input (χχ) of the gate (Ηχ) is connected to one control input (r ₄ , r ₃ , r ₅ ) from the set of control inputs (ri, r ₂ , r ₃ , ..., r ₆ ) of the wiring.