CS198482B1 - Two-input synchronous flip-flop circuit with pre-storage - Google Patents

Description

The invention relates to a two-input "flip-synchronous -obvodu -s předpamětí intended ^to receive and encode ^and randomly in providing its ^{y P} much ^of the equipment which ^p Raoui synchronous operating cycle.

Synchronous electronic devices - can receive - some commands only at discrete moments linked to their duty cycle. - Commands issued by other, - independent signal sources, eg human, occur asynchronously. That's why I wutno. to address the reception of such signals individually with respect to - the way - control and the properties - of the device.

It is an object of the present invention to provide a first input signal to an input of a first flip-flop, the auxiliary output of which is connected to an RS-type flip-flop input. Output of the flip-flop is connected -is - an adjusting input of the first flip-flop, whose synchronization ga ^p and simultaneously the sync ga ^p second stack it ^{é é p} n clones of a circuit is supplied synchronization signal. The second input signal. A second flip-flop input is provided, the auxiliary output of which is connected to the RS-type flip-flop setting input. Inverted output of the RS flip-flop is connected to the adjustment H - input of the second ^KL OPN ^eh the circuit. The previously ^{characterized} s'tu ^{P eh} of ^{the LO} n ^eh the circuit at the same ^time with the output of he second ^{e s p} n clones of a circuit as the output of flip-flop are the outputs -dvouvstupového synchronous memory circuit předpamětí.

The characteristics of the two-input flip-flop with pre-biased circuits are described in the truth table:

198 -482

198 482

occurrence of input signal in the interval before synch- <* >> ♦ 1 output variables ro pulse input (11) entrance (12) <»>« ♦ 2 < ²⁵ > n. ¹ No No ⁽ 34 ^{) n} <15) _a ( ² ) ⁿ Yes No 1 1 ’ No Yes 0 1 (25) _n . (34) _n Yes Yes it is not defined

Index n indicates the state before, index n + 1 indicates the state after the moment of the synchronization pulse. The horizontal line above the expression indicates inversion.

The circuit and properties according to the truth table have not been solved yet.

The circuit diagrams of the present invention are shown in the accompanying drawings. Fig. 1 shows the overall circuit diagram of the invention; Fig. 2 shows the first and second flip-flop circuits respectively.

The first flip-flop 10 and the second flip-flop 20 (FIG. 1) are identical in their internal function. Their inputs 11 and 21 represent the inputs of the biased flip-flop. Their synchronization inputs 12 and 22 are connected and a synchronization signal is applied to them. The auxiliary output 13 of the first flip-flop 10 controls an R-S flip-flop 30 by means of the adjusting input 31, the reset input 32 of which is controlled by the auxiliary output 23 of the second flip-flop 60. The setting input 14 of the first flip-flop 10 is controlled by the output 34 of the R-S flip-flop 30. whose inverted output 35 controls the adjusting input 24 of the second flip-flop 60.

On- . FIG. 2 is a schematic of the first and second flip-flops respectively. The input signal 11 is applied to the setting input of the R-S 101 flip-flop circuit. The NAND '102 gate controls its reset of the R-S 101 flip-flop circuit input. The R-S flip-flop output is connected to the second input. 101. while its inverted output is coupled to the clock input of the D-type flip-flop 103. The adjusting input of the D-type flip-flop is the adjustment input 14 of the first flip-flop. The D-type flip-flop output 103. represents the output of the flip-flop 10 flip-flop.

Claims (5)

1. A biased synchronous flip-flop circuit, characterized in that the first input signal is applied to the input (11) of the first flip-flop (10), the auxiliary output (13) of which is connected to the reset input (31) of the RS flip-flop. (30), the output (34) of which is connected to the adjusting input (14) of the first flip-flop (10), to whose synchronization input (12) is connected by the synchronization input (22) of the second. a flip-flop (20) is provided with a synchronization signal, the second input signal being applied to an input (21) of the second flip-flop (20), the auxiliary output (23) of which is connected to the flip-flop adjusting input (32). the inverted 'output (35) is connected to the control input (24) of the second - flop (20) output přičemž- ⁽¹ 5) ^¹H RVN ^p o - ^p n ^to lo ^eh oo ^b water (l ^ ⁰ at the same time with t ^t u ^P em ⁽² 5) of dru ^{HEH kl} o ^p n ^eh of the circuit ⁽² °) and the outlet (34) of the RS type flip-flop (30). twininlet forms the output synchronous. předpamětí circuit. ' 2. A two-input synchronous flip-flop according to claim 1, wherein the first flip-flop (10) is a RS flip-flop (101) whose adjusting input is formed. an input (11) of the first flip-flop (10), wherein the output of the RS flip-flop (101) is coupled to the first NAND gate input. (102), whose. output connected to the reset input ^to lopn ^eh otoodu those of ^P u ^R - ^{S (101)} simultaneously ^- • forming auxiliary bui ^t u ^pp rvníto ^{to LO} Joint circumference. (10), wherein the inverted output of the RS flip-flop (101) is coupled to the clock input of the D flip-flop (103), the output of which is the output (15) of the first flip-flop (10), input D, its adjusting input forming the adjusting input (14) of the first flip-flop (10), while the second gate input of the NAND (102) forms the synchronization input (12) of the first flip-flop (10). 3. The two-input synchronous flip-flop according to claim 1, wherein the second flip-flop (20) is identical to the first flip-flop (10). 4. The two-input synchronous flip-flop according to claim 1, wherein:. between the adjusting input (14) of the first flip-flop (10) and the output (34) of the R-S flip-flop. (30) an integrating RC member is included. 5. The biased synchronous flip-flop according to claim 1, wherein a differentiating member RC is provided between the adjusting input (14) of the first flip-flop (10) and the output (34) of the R-S flip-flop (30).