CO4700362A1 - Metodo para la entrega de ordenes en un sistema computador y la combinacion de medios que lo hacen posible. - Google Patents

Metodo para la entrega de ordenes en un sistema computador y la combinacion de medios que lo hacen posible.

Info

Publication number
CO4700362A1
CO4700362A1 CO92323128A CO92323128A CO4700362A1 CO 4700362 A1 CO4700362 A1 CO 4700362A1 CO 92323128 A CO92323128 A CO 92323128A CO 92323128 A CO92323128 A CO 92323128A CO 4700362 A1 CO4700362 A1 CO 4700362A1
Authority
CO
Colombia
Prior art keywords
subsystem
door
orders
command interface
indicative
Prior art date
Application number
CO92323128A
Other languages
English (en)
Inventor
Francis M Bonevento
Douglas R Chisholm
D Dodds Sammy
M Desai Dhruvkumar
Ernest N Mandese
Neill Andrew B Mc
Richard N Mendelson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CO4700362A1 publication Critical patent/CO4700362A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Storage Device Security (AREA)

Abstract

En un sistema procesador de datos que incluye un sistemacentral, y al menos un subsistema que puede llevar dispositivos unidos a él, la combinación que comprende: una interfase de órdenes para transferir información entre el sistema central y dicho un subsistema, incluyendo dicha interfase de órdenes: una primera puerta para recibir una orden directa o una orden indirecta desde dicho sistema central, las cuales órdenes son indicativas del tipo de operación que ha de realizarse en dicho subsistema o en los dispositivos unidos a él; y una segunda puerta para recibir desde dicho sistema central un código indicativo de cual dichas ordenes directa o indirecta se recibe en dicha primera puerta, y siendo también indicativo de cual de dicho un subsistema o de un dispositivo unido a él, ha de ejecutar la orden recibida en dicha primera puerta". En un sistema computador que incluye un procesador central que tiene una memoria del sistema, y al menos un subsistema inteligente que puede tener dispositivos unidos a él, la combinación que comprende: una interfase de órdenes incluida en cada uno de tales subsistemas para transferir información entre dicho procesador central y dicho un subsistema inteligente, incluyendo dicha interfase de órdenes:una puerta de interfase de órdenes para recibir una orden directa o una orden indirecta proveniente de dicho procesador central, las cuales ordenes son indicativas del tipo de operación que ha de realizarse por el subsistema inteligente o los dispositivos unidos a él; yuna puerta de atención, para recibir desde dicho procesador central, un código que tenga una primera porción que es indicativa de cual de dichas órdenes directas o de dichas ordenes indirectas se recibe en dicha puerta de interfase de órdenes; y una segunda porción que es indicativa de cual de los sistemas inteligentes o de los dispositivos unidos a él ha de ejecutar la orden recibida en dicha puerta de interfase de órdenes".
CO92323128A 1989-06-09 1990-06-01 Metodo para la entrega de ordenes en un sistema computador y la combinacion de medios que lo hacen posible. CO4700362A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/364,931 US5131082A (en) 1989-06-09 1989-06-09 Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block

Publications (1)

Publication Number Publication Date
CO4700362A1 true CO4700362A1 (es) 1998-12-29

Family

ID=23436743

Family Applications (1)

Application Number Title Priority Date Filing Date
CO92323128A CO4700362A1 (es) 1989-06-09 1990-06-01 Metodo para la entrega de ordenes en un sistema computador y la combinacion de medios que lo hacen posible.

Country Status (16)

Country Link
US (1) US5131082A (es)
EP (1) EP0402054B1 (es)
JP (1) JPH0670783B2 (es)
KR (1) KR920008459B1 (es)
CN (1) CN1021380C (es)
AR (1) AR246125A1 (es)
AU (1) AU630699B2 (es)
BR (1) BR9002710A (es)
CA (1) CA2012400C (es)
CO (1) CO4700362A1 (es)
DE (1) DE69031547T2 (es)
GB (1) GB9008084D0 (es)
MY (1) MY105624A (es)
NZ (1) NZ233824A (es)
PE (1) PE34890A1 (es)
PH (1) PH31356A (es)

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US5388218A (en) * 1992-02-14 1995-02-07 Advanced Micro Devices, Inc. Apparatus and method for supporting a transfer trapping discipline for a non-enabled peripheral unit within a computing system
AU4229293A (en) * 1992-05-13 1993-12-13 Southwestern Bell Technology Resources, Inc. Open architecture interface storage controller
US5659690A (en) * 1992-10-15 1997-08-19 Adaptec, Inc. Programmably configurable host adapter integrated circuit including a RISC processor
US5613141A (en) * 1992-10-19 1997-03-18 International Business Machines Corporation Data storage subsystem having dedicated links connecting a host adapter, controller and direct access storage devices
US5794056A (en) * 1993-10-04 1998-08-11 International Business Machines Corporation System for automatic buffering of commands for DASD units
US5630147A (en) * 1993-12-17 1997-05-13 Intel Corporation System management shadow port
EP0811197B1 (en) * 1995-02-24 2003-08-06 Intel Corporation System management shadow port
US5794069A (en) * 1995-12-13 1998-08-11 International Business Machines Corp. Information handling system using default status conditions for transfer of data blocks
US5802546A (en) * 1995-12-13 1998-09-01 International Business Machines Corp. Status handling for transfer of data blocks between a local side and a host side
US5812877A (en) * 1996-03-15 1998-09-22 Adaptec, Inc. I/O command block chain structure in a memory
US5867732A (en) * 1996-03-15 1999-02-02 Adaptec, Inc. Hardware method for verifying that an area of memory has only zero values
US5850567A (en) * 1996-03-15 1998-12-15 Adaptec, Inc. Method for specifying concurrent execution of a string of I/O command blocks in a chain structure
US5974530A (en) * 1996-03-15 1999-10-26 Adaptec, Inc. Integrated PCI buffer controller and XOR function circuit
US5881250A (en) * 1996-03-15 1999-03-09 Adaptec, Inc. Host adapter system including an integrated PCI buffer controller and XOR function circuit
US5923896A (en) * 1996-03-15 1999-07-13 Adaptec, Inc. Method for sequencing execution of I/O command blocks in a chain structure by setting hold-off flags and configuring a counter in each I/O command block
US5892969A (en) * 1996-03-15 1999-04-06 Adaptec, Inc. Method for concurrently executing a configured string of concurrent I/O command blocks within a chain to perform a raid 5 I/O operation
US5758187A (en) * 1996-03-15 1998-05-26 Adaptec, Inc. Method for enhancing performance of a RAID 1 read operation using a pair of I/O command blocks in a chain structure
US5797034A (en) * 1996-03-15 1998-08-18 Adaptec, Inc. Method for specifying execution of only one of a pair of I/O command blocks in a chain structure
US5991861A (en) * 1996-03-15 1999-11-23 Adaptec, Inc. Method of enabling and disabling a data function in an integrated circuit
JPH1097385A (ja) * 1996-09-19 1998-04-14 Toshiba Corp ディスク記録再生装置及び同装置に適用するインターフェース制御装置
KR100512165B1 (ko) * 1998-05-08 2005-11-11 삼성전자주식회사 충전 가능한 배터리의 용량 측정 방법
US7444642B2 (en) * 2001-11-15 2008-10-28 Intel Corporation Method for indicating completion status of asynchronous events
CN100461716C (zh) * 2005-01-28 2009-02-11 华为技术有限公司 基于模拟端口的通信方法
US8719516B2 (en) * 2009-10-21 2014-05-06 Micron Technology, Inc. Memory having internal processors and methods of controlling memory access
US9952801B2 (en) * 2015-06-26 2018-04-24 Intel Corporation Accelerated address indirection table lookup for wear-leveled non-volatile memory
US10318193B2 (en) * 2015-09-14 2019-06-11 Sandisk Technologies Llc Systems and methods of command authorization

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US3787891A (en) * 1972-07-03 1974-01-22 Ibm Signal processor instruction for non-blocking communication between data processing units
US3778780A (en) * 1972-07-05 1973-12-11 Ibm Operation request block usage
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Also Published As

Publication number Publication date
PH31356A (en) 1998-07-31
AU5597890A (en) 1990-12-13
DE69031547D1 (de) 1997-11-13
EP0402054B1 (en) 1997-10-08
BR9002710A (pt) 1991-08-20
AU630699B2 (en) 1992-11-05
CA2012400A1 (en) 1990-12-09
NZ233824A (en) 1992-09-25
AR246125A1 (es) 1994-03-30
CN1048938A (zh) 1991-01-30
CN1021380C (zh) 1993-06-23
EP0402054A2 (en) 1990-12-12
US5131082A (en) 1992-07-14
KR920008459B1 (ko) 1992-09-30
DE69031547T2 (de) 1998-03-26
GB9008084D0 (en) 1990-06-06
CA2012400C (en) 1999-03-30
PE34890A1 (es) 1991-01-18
JPH0670783B2 (ja) 1994-09-07
JPH0322162A (ja) 1991-01-30
EP0402054A3 (en) 1992-08-05
MY105624A (en) 1994-11-30
KR910001557A (ko) 1991-01-31

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