CN85101319A

CN85101319A - Voltage stabilizing didoe

Info

Publication number: CN85101319A
Application number: CN 85101319
Authority: CN
Inventors: 户井田裕俊; 日高俊幸; 坂本久
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1985-04-01
Filing date: 1985-04-01
Publication date: 1987-01-10

Abstract

A voltage stabilizing didoe comprises the layer of semiconductor substrate, between its corresponding main surfaces p is arranged ^-n ^-n ⁺Or n ^-p ^-p ⁺Three layers, substrate has negative ramp structure, and in this structure, the pn knot end and the major surfaces in parallel that form on the substrate are extended, at p ^-n ^-n ⁺In p layer or n ^-p ^-p ⁺In the edge of n layer and a side of substrate acutangulate.Pair of electrodes places respectively on two first type surfaces of substrate.Substrate between two electrodes with a kind of encapsulant crimping.

Description

Voltage stabilizing didoe

The present invention relates to the end structure of the pn knot of a kind of voltage stabilizing didoe, particularly this diode.

Ramp structure in that this pn knot end forms is divided into positive bevel and negative inclined-plane.Positive bevel is corresponding to this situation: on the longitudinal cross-section of the Semiconductor substrate vertical with a pair of first type surface, contain a surface of the Semiconductor substrate of pn knot exposed junction, semiconductor layer on one side the pn knot end higher with impurity concentration becomes the obtuse angle.Negative inclined-plane is corresponding to this situation: the higher semiconductor layer pn on one side of above-mentioned surface and impurity concentration ties the end and acutangulates.The end of pn knot perhaps is exposed to a first type surface of Semiconductor substrate, perhaps is exposed to a side of the Semiconductor substrate that extends between first type surface.Roughlly speaking, the structure that pn knot end is exposed to first type surface is called planarized structure, and the structure that pn knot end is exposed to the side is called meas structure.The Semiconductor substrate that is used for voltage stabilizing didoe has p-n-n ⁺Or p+-p-n three-decker.

In a common voltage stabilizing didoe with meas structure, strengthen the area of pn knot with positive bevel, thereby strengthen the ability of bearing reverse voltage, weaken the electric field of the end, barrier layer that forms on pn knot both sides and (see Fig. 2 and United States Patent (USP) the 3rd, 270, No. 225 11).Therefore, which first type surface pn knot is positioned at wherein near, and the area of this first type surface is just greater than another first type surface.So in the diode manufacture process, if the part of extending from large tracts of land master meter aspect-oriented is broken or cuts away, the constant voltage characteristic of diode can be subjected to very big influence.

In recent years, a kind of polyimide resin that can reduce leakage current is used as the surface passivation agent, is coated in the end of exposing of pn knot.But,, exist the problem that is difficult to form thick resin molding because the viscosity of this resin is low.Particularly, such problem is arranged for the positive bevel structure, i.e. the surface passivated membrane of making by above resin, the pn knot expose the end attenuation, thereby owing to power line leaks and the reason of wet electric resistance difference causes obtaining high-breakdown-voltage.

The object of the present invention is to provide a kind of voltage stabilizing didoe, both made when being broken near the periphery of the large tracts of land first type surface in the Semiconductor substrate first type surface or cutting away, the constant voltage characteristic of this pipe is also unaffected.

Another object of the present invention provides a kind of voltage stabilizing didoe, and this pipe does not need the accurate control of bevel angle, thereby can be suitable for producing in enormous quantities.

A further object of the invention provides a kind of voltage stabilizing didoe, and the puncture voltage of this pipe is unaffected, and wet electric resistance does not reduce yet.

For reaching above purpose, comprise a Semiconductor substrate with negative ramp structure according to voltage stabilizing didoe of the present invention.

Here the voltage stabilizing didoe of indication is a kind of like this diode, when Zener (Zener) puncture is about to take place, the barrier layer (being depletion layer) that pn knot both sides produce on the Semiconductor substrate, in the localized area of p layer and n layer, expand, impurity concentration is linear distribution in this territory, these barrier layers expand to some position with roughly the same width, and on these positions, p layer and n layer have roughly the same impurity concentration.

Fig. 1 is a longitudinal sectional drawing, illustrates according to a kind of voltage stabilizing didoe device of the present invention;

Fig. 2 is a curve chart, the relation between expression Zener (Zener) voltage and barrier width;

Fig. 3 is a curve chart, the impurities concentration distribution on the expression voltage stabilizing didoe silicon substrate;

Fig. 4 is a longitudinal sectional drawing, illustrates according to another kind of voltage stabilizing didoe device of the present invention.

Referring to Fig. 1, the figure illustrates a kind of according to voltage stabilizing didoe device of the present invention.Voltage stabilizing didoe 10 is made up of silicon substrate 11, and substrate comprises three layers, p layer 11a, n layer 11b and n+ layer 11c.Shown in substrate 11 form by following method: the P type is diffused on the large tracts of land N type thin silicon sheet that the order of magnitude is 0.01 Ω CM resistivity from the first type surface of relative silicon chip respectively with N type impurity, with well-known technology (for example sand-blast) the p-n-n+ three-decker is carried out surface treatment, erode then and remain in lip-deep burr in the manufacturing.The remaining area that does not diffuse into P type and N type impurity in the silicon chip is n layer 11b.Before the thin silicon sheet is processed, on each first type surface of silicon chip, form a nickel dam with plating or other similar

approach.Reference number

12a and 12b represent to be retained in the nickel dam on silicon substrate 11 first type surfaces of handling.Silicon chip after treatment, each first type surface of silicon substrate 11 is all rounded, the side surface of substrate 11 tilts, p layer 11a major surface area on one side is less than n+ layer 11c major surface area on one side.The pn knot J and the major surfaces in parallel that form between p layer 11a that faces mutually and n layer 11b are extended.Like this, pn knot J and p layer 11a side on one side acutangulate.The impurity concentration of P layer 11a also is higher than n layer 11b.Therefore, silicon substrate 11 has negative ramp structure.

Two-seater lead-in

wire

14a and 14b join with

nickel dam

12a and 12b with low resistance contact respectively by welding flux layer 13a and 13b.Between the first base part 14aa of lead-in

wire

14a and 14b and 14ba and near on the side of silicon substrate 11, coat surface passivation agent 15.And then, packing matcrial or crimping material 16 between the second base part 14ab and 14bb.For instance, can use epoxy resin as crimping material 16 with the polyimides silicone resin as surface passivation agent 15.

For the structure of this device, be positioned at n+ layer 11C one side and with the periphery of the acutangulate first type surface in side, easily broken or cut away in manufacture process.But, both having made this a part of sensitive for damages, the characteristic of diode is also influenced hardly, because it is irrelevant with pn knot J to be damaged part.

In this voltage stabilizing didoe, the order of magnitude of the resistivity of n layer 11b is 0.01 Ω cm, and its impurity concentration is higher than the impurity concentration of general-purpose diode n layer, and the latter's resistivity is approximately 30 Ω cm.Therefore, when adding reverse voltage, in the P layer 11a on pn knot J both sides and n layer 11b, produce the very little barrier layer of width.For the Zener that is not higher than 30V (Zener) voltage, the barrier layer that produces in P layer 11a and the every limit of n layer 11b is not more than 1 μ m, as shown in Figure 2.Can see from impurities concentration distribution shown in Figure 3, puncture the barrier layer that produces when being about to take place at Zener (Zener), only extend in those localized areas of pn knot both sides, impurity concentration is linear distribution in these zones.In addition, there is roughly the same width on the barrier layer that produces in P layer 11a and N layer 11b, and all extends to the position that P layer and N layer have roughly the same impurity concentration.Therefore the electric field strength in barrier layer roughly equates with electric field strength in another barrier layer.

Therefore, both made this device use negative ramp structure, when the degree of expansion on barrier layer, side at this moment and electric field strength and use positive bevel structure and it makes no odds.In other words, although this device uses negative ramp structure, do not worry to cause reducing of side puncture voltage.Angle between these considerations and side and the first type surface is irrelevant.Therefore, do not need accurately to control bevel angle, thereby be fit to large-scale production.

When each diameter of selecting the first base part 14aa and 14ba is equal to or greater than the maximum gauge of silicon substrate 11 (as shown in Figure 1), the first base part 14aa and 14ba are used as the flow restrictor of surface passivation agent 15, passivator 15 can form a skim, and is thicker near the end of pn knot J.Therefore, both made when using low viscosity material commonly used, also can not cause the reduction of puncture voltage and/or wet electric resistance, and this situation may take place in the positive bevel structure as surface passivation agent 15.

The area of the pn knot J that obtains in the negative ramp structure little than in the positive bevel structure.But this can not cause any problem, because, if strengthen the negative angle of chamfer, because the corresponding minimizing of slip meeting of the junction area that this ramp structure of use causes; If select the volume of silicon substrate 11 to be a bit larger tham the volume of used substrate in the common positive bevel voltage stabilizing didoe, just can obtain with positive bevel structure situation in identical reverse voltage ability to bear.

Fig. 4 illustrates another kind of according to voltage stabilizing didoe device of the present invention.

Referring to Fig. 4, voltage stabilizing didoe 20 is made up of silicon substrate 21, and substrate has three layers, comprises n layer 21a, P layer 21b and p+ layer 21C.Shown in substrate 21 form by following method: with N type and p type impurity as raw material, respectively from being diffused on the large tracts of land P type thin silicon sheet with the silicon chip opposed major surfaces, then, to make the same procedure of device shown in Figure 1, the n-p-p+ three-decker is handled.The substrate of making 21 has negative ramp structure, and substrate 21 is at the first type surface of n layer 21a one side, and its area is less than the first type surface in p+ layer 21c one side, and formed pn knot J and major surfaces in parallel are extended.

Contact conductor

24a and 24b are fixed in the first type surface of silicon substrate 21 respectively by aluminum solder layer 23a and 23b.Contact conductor 24a(24b) comprise the block type electrode 24aa(24ba that makes by molybdenum or tungsten) and be connected copper cash 24ab(24bb on the block type electrode by pressure welding in advance).The glass 25 that will have the surface passivation effect is crimped onto on the silicon substrate 21, and extends to block type electrode 24ba from block type electrode 24aa.Glass 25 is ZnO-B ₂O-SiO ₂Glass, PbO-B ₂O ₃-SiO ₂Glass, perhaps other.

When the silicon substrate 21 with n-P-P+ three-decker adds reverse voltage, the barrier layer that produces in the p layer 21b of pn knot J both sides and n layer 21a extends to some position with roughly the same width, on these positions, these layers have roughly the same impurity concentration, as device shown in Figure 1.Therefore, in this device, adopt negative ramp structure, also can not cause reducing of puncture voltage.Furtherly, p+ layer 21c one side first type surface periphery was broken or cuts away, the characteristic of diode can not be affected yet, because this breakage is difficult to extend to pn knot J.

As explained above, the invention provides a kind of like this voltage stabilizing didoe, both made when being broken near the large tracts of land first type surface periphery of Semiconductor substrate or cutting away, the constant voltage characteristic of pipe is also unaffected.

Claims

1, a kind of voltage stabilizing didoe is characterized in that: comprise in order between a pair of first type surface of Semiconductor substrate, ground floor semiconductor with a kind of conduction type, second layer semiconductor with another kind of conduction type, the impurity concentration of the second layer is lower than ground floor, three-layer semiconductor with above-mentioned another kind of conduction type, its impurity concentration is higher than the second layer, form a pn knot between above-mentioned ground floor and the second layer semiconductor, the pn knot extends along the major surfaces in parallel of above-mentioned Semiconductor substrate, its end exposes to a side that extends in Semiconductor substrate between above-mentioned first type surface, first type surface in the Semiconductor substrate of above-mentioned ground floor semiconductor one side, another first type surface less than three-layer semiconductor one side, first and second semiconductor layers each have an impurities concentration distribution, when Zener (Zener) puncture is about to take place, the barrier layer that forms in above-mentioned first and second semiconductor layers extends to some position with roughly the same width, on these positions, first and second semiconductor layers have roughly the same impurity concentration;

Pair of electrodes is joined with two first type surfaces of low resistance contact and above-mentioned Semiconductor substrate respectively;

A kind of encapsulant extends between the above-mentioned electrode to seal above-mentioned Semiconductor substrate.

2, according to claim 1 described voltage stabilizing didoe, wherein at the above-mentioned electrode of above-mentioned a certain first type surface one side, greater than this first type surface.

3, according to claim 1 described voltage stabilizing didoe, wherein above-mentioned encapsulant also comprises the surface passivation agent of the exposed junction that a kind of pn that is coated in above-mentioned Semiconductor substrate ties.

4, according to claim 1 described voltage stabilizing didoe, wherein second semiconductor layer of above-mentioned Semiconductor substrate has the resistivity that the order of magnitude is 0.01 Ω cm.

5, according to claim 1 described voltage stabilizing didoe, wherein above-mentioned encapsulant is made by glass.

6, according to claim 3 described voltage stabilizing didoes, wherein above-mentioned surface passivation agent is made by the polyimides silicone resin, and above-mentioned encapsulant is made by epoxy resin.