CN2930102Y - Automatic compensation low zero float integrator - Google Patents
Automatic compensation low zero float integrator Download PDFInfo
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- CN2930102Y CN2930102Y CN 200620073017 CN200620073017U CN2930102Y CN 2930102 Y CN2930102 Y CN 2930102Y CN 200620073017 CN200620073017 CN 200620073017 CN 200620073017 U CN200620073017 U CN 200620073017U CN 2930102 Y CN2930102 Y CN 2930102Y
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- switch
- integrator
- resistance
- operational amplifier
- hold circuit
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Abstract
An automatic compensation low null shift integral device comprises a basic integral device and a feedback network composed of a sampling maintenance circuit. The integral device comprises the inverted input resistance of a computational amplifier which is connected with an input voltage or the ground through a selector switch. Four branch circuits connected in parallel are disposed between the inverted input and the output of the computational amplifier. One of the branch circuits is composed of a switch, one composed of an integral capacitor and a switch connected in series, one composed of a resistance and a switch connected in series and the other one composed of a resistance, a switch and a sampling maintenance circuit. The positive input of the computational amplifier is connected with the ground through the positive input resistance. The automatic compensation low null shift integral device can effectively restrain the null shift within certain time.
Description
Technical field:
The utility model relates to integrator.
Background technology:
The long-time integration device is mainly used in the electromagnetic measurement of some devices, and for example in tokamak discharge test process, the output of many electromagnetic measurement diagnostic signals is the micro component of this signal, wants to reduce this signal, needs to use integrator.Along with the continuous development of Tokamak nuclear fusion research, the discharge time of plasma is more and more longer, therefore, also requires more and more longlyer during integration, even requires to reach the kilosecond magnitude.But, because the existence of drift, general analogue integrator can only effectively be worked tens seconds, more senior have a digital integrator, method by AD or VF is converted to digital quantity with analog quantity, finish integral operation through corresponding algorithm process again, convert the result to analog quantity by DA or FV more at last.The precision of digital integrator depends primarily on the resolution of AD or VF, and resolution is high more, and precision is high more, and therefore, digital integrator generally will be selected AD or the VF than high resolution, thereby causes it to cost an arm and a leg.
Summary of the invention:
The utility model is for avoiding above-mentioned existing in prior technology weak point, a kind of analog auto-compensative low drift integrator that can effectively suppress the integration drift within a certain period of time being provided.
The technical scheme that the utility model technical solution problem is adopted is:
Design feature of the present utility model is made up of the feedback network that basic integrator and sampling hold circuit constitute; Comprising:
The operational amplifier IC1 reverse input end resistance R that constitutes integrator is by selector switch K1 or access input voltage ViA, or ground connection;
Between the reverse input end of described operational amplifier IC1 and output, four parallel branches are arranged, article one, by K switch 4 constitute, one by 3 series connection of integrating capacitor C and K switch constitute, the K switch 2 by resistance R _ f and series connection with it constitutes, one is to be made of resistance R _ f and K switch 5 and sampling hold circuit again, and wherein sampling hold circuit is positioned at output one side of operational amplifier IC1;
The positive input of described operational amplifier IC1 is by positive input resistance R ground connection.
The control method of the utility model integrator is to be divided into following two stages chronologically:
First: the preparatory stage, deduct drift and zero clearing integrating capacitor according to the following steps:
A, measurement drift:
K1 ground connection, K2 closure, K3, K4, K5 open, and constitute amplifier, write down the drift amplifying signal of this amplifier output with described sampling hold circuit;
B, compensation drift:
K1 ground connection, K2, K5 closure, K3, K4 open, and sampling hold circuit is the drift value negative feedback of its preservation reverse input end to operational amplifier IC1, the compensation drift;
C, integrating capacitor zero clearing:
K1 ground connection, K3, K4, K5 are all closed, and K2 opens, and before integration begins, remove the electric charge on the integrating capacitor;
Second: integration phase
After the process preparatory stage, K3, K5 closure, K1 meets input signal ViA, and K2, K4 open, and constituting time constant is the integrator of RC, the beginning integration.
The integrator drift of analog integrator mainly is caused by offset voltage V10, offset current I10.The utility model compensates imbalance at input, can suppress integrator drift effectively.The utility model is made of a basic operation amplifier and sampling hold circuit, utilizes sampling hold circuit to note drift, in integration input is compensated, and offsets drift, and this compensation method is in full force and effect being about in the time of 100s.
Compared with the prior art, to be embodied in its scheme simple, easy to implement for the beneficial effects of the utility model.The utility model provides necessary guarantee for the low drift integration of realizing the longer time.
Description of drawings:
Accompanying drawing is the utility model circuit theory schematic diagram.
By the following examples, in conjunction with the accompanying drawings the utility model is further described:
Embodiment:
Referring to accompanying drawing, in the present embodiment, integrator is made up of the feedback network that basic integrator and sampling hold circuit constitute; Comprising:
The reverse input end resistance R that constitutes the operational amplifier IC1 of integrator is passed through selector switch K1 or is inserted input voltage ViA, or ground connection;
Between the reverse input end of operational amplifier and output, four parallel branches are arranged, article one, by K switch 4 constitute, one by 3 series connection of integrating capacitor C and K switch constitute, the K switch 2 by resistance R _ f and series connection with it constitutes, one is to be made of resistance R _ f and K switch 5 and sampling hold circuit again, and wherein sampling hold circuit is positioned at output one side of operational amplifier;
The forward output of operational amplifier is by resistance R ground connection.
As shown in the figure, present embodiment is a kind of reaction type compensation method, and it is made of a basic integrator and sampling hold circuit, utilizes sampling hold circuit to note drift, in integration input is compensated, and offsets drift.Wherein, the resistance R, operational amplifier and the capacitor C that link to each other with K switch 1 constitute basic integrating circuit, and integration time constant is RC; The Rf that links to each other with K switch 2 is used to measure drift, and the sampling hold circuit sampling also keeps drift, and '-' that compensate to operational amplifier by K switch 5 and Rf holds, and sampling hold circuit can directly be realized with sampling holder.
The control method of present embodiment integrator is to be divided into following two stages chronologically:
First: the preparatory stage, deduct drift and zero clearing integrating capacitor according to the following steps:
A, measurement drift
K1 ground connection, K2 closure, K3, K4, K5 open, and constitute amplifier, write down the drift amplifying signal of this amplifier output with described sampling hold circuit;
Because the offset voltage V of operational amplifier
I0, offset current I
I0All very little, so R
f/ R should reach several ten thousand times usually, and their equivalence values of causing just can be amplified to the degree that can measure like this.
B, compensation drift
K1 ground connection, K2, K5 closure, K3, K4 open, and sampling hold circuit is the drift value negative feedback of its preservation reverse input end to operational amplifier, the compensation drift;
By with R
fOnesize resistance, the value that holding circuit is preserved compensates to input, and VoA output at this moment in integral process, constantly to the input compensation, reduces error near zero.
C, integrating capacitor zero clearing
K1 ground connection, K3, K4, K5 are all closed, and K2 opens, and before integration begins, removes the electric charge on the integrating capacitor;
Second: integration phase
After the process preparatory stage, K3, K5 closure, K1 meets input signal ViA, and K2, K4 open, and constituting time constant is the integrator of RC, the beginning integration.
The utility model compensation method is in full force and effect being about in the time of 100s, and the integration for the longer time can carry out, and each section integrated signal is added up in segmentation.
Claims (1)
1, auto-compensative low drift integrator is characterized in that being made up of the feedback network that basic integrator and sampling hold circuit constitute; Comprising:
The operational amplifier IC1 reverse input end resistance R that constitutes integrator is by selector switch K1 or access input voltage ViA, or ground connection;
Between the reverse input end of described operational amplifier IC1 and output, four parallel branches are arranged, article one, by K switch 4 constitute, one by 3 series connection of integrating capacitor C and K switch constitute, the K switch 2 by resistance R _ f and series connection with it constitutes, one is to be made of resistance R _ f and K switch 5 and sampling hold circuit again, and wherein sampling hold circuit is positioned at output one side of operational amplifier IC1;
The positive input of described operational amplifier IC1 is by positive input resistance R ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620073017 CN2930102Y (en) | 2006-04-26 | 2006-04-26 | Automatic compensation low zero float integrator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620073017 CN2930102Y (en) | 2006-04-26 | 2006-04-26 | Automatic compensation low zero float integrator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2930102Y true CN2930102Y (en) | 2007-08-01 |
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ID=38308472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620073017 Expired - Fee Related CN2930102Y (en) | 2006-04-26 | 2006-04-26 | Automatic compensation low zero float integrator |
Country Status (1)
| Country | Link |
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| CN (1) | CN2930102Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845457B (en) * | 2006-04-26 | 2010-05-12 | 中国科学院等离子体物理研究所 | Auto-compensative low drift integrator and its controlling method |
| CN102878917A (en) * | 2012-09-17 | 2013-01-16 | 华中科技大学 | Signal operation device based on Rogowski coil measurement |
| CN103986453A (en) * | 2014-05-15 | 2014-08-13 | 合肥工业大学 | Intelligent error compensation type integrator based on FPGA and error compensation method thereof |
-
2006
- 2006-04-26 CN CN 200620073017 patent/CN2930102Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845457B (en) * | 2006-04-26 | 2010-05-12 | 中国科学院等离子体物理研究所 | Auto-compensative low drift integrator and its controlling method |
| CN102878917A (en) * | 2012-09-17 | 2013-01-16 | 华中科技大学 | Signal operation device based on Rogowski coil measurement |
| CN102878917B (en) * | 2012-09-17 | 2014-11-12 | 华中科技大学 | Signal operation device based on Rogowski coil measurement |
| CN103986453A (en) * | 2014-05-15 | 2014-08-13 | 合肥工业大学 | Intelligent error compensation type integrator based on FPGA and error compensation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |