CN2899111Y - Planar convex-point packing base plate of electronic device - Google Patents
Planar convex-point packing base plate of electronic device Download PDFInfo
- Publication number
- CN2899111Y CN2899111Y CN 200620072876 CN200620072876U CN2899111Y CN 2899111 Y CN2899111 Y CN 2899111Y CN 200620072876 CN200620072876 CN 200620072876 CN 200620072876 U CN200620072876 U CN 200620072876U CN 2899111 Y CN2899111 Y CN 2899111Y
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- CN
- China
- Prior art keywords
- dao
- electronic device
- pin
- saliant
- board
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a planar convex-point packing base plate of electronic device, which comprises base islands (1) and pins (2) and is characterized in that: the base islands (1) and the pins (2) are distributed on the front face of the base plate and take the shape of convex-points; the convex-points are connected by a metallic film (3); the base islands (1) are unit base islands consisting of a plurality of convex points; the pins (2) are single convex point. Inside the packer of single electronic device formed during follow-up packing, the number of the base islands (1) can be one or more, i.e. one unit base island or more unit base islands consisting of a plurality of convex points, and the pins (2) are arrayed at one or two or three sides of the base islands or surround the base islands (1) to form a structure of one or more laps of pins. The utility model has the advantages of high degree of freedom of the packing structure, ideal package reliability, low requirement for package and technique and low material consumption.
Description
Technical field:
The utility model relates to a kind of flat-face saliant-point type packing base-board for electronic device.Belong to electronic devices and components
Technical field.
Background technology:
The planar salient point type base plate for packaging of existing electronic devices and components, the Ji Dao on it is the block of metal shape.It mainly has the following disadvantages:
1, encapsulating structure: chip Ji Dao is corresponding one by one, and requires the basic island size must be greater than chip size, and limitation is very big, is difficult to adapt to the chip of different size size and specification.
2, package reliability:, require high to the material of Ji Dao, evenness, surface quality, clean-up performance etc. because chip is installed on the Ji Dao; Simultaneously because block of metal Ji Dao is easy to generate bigger deformational stress after being heated, so integrity problem such as layering takes place easily, and along with chip size constantly increases, correspondingly can require bigger Ji Dao, the problems referred to above are just more and more serious.
3, packaging cost: along with chip design becomes increasingly complex, the chip size specification is also more and more diversified, the chip of super-long and super-wide constantly occurs, if change basic island size even need redesign lead frame fully along with the continuous variation of chip specification, with high costs.
4, specification requirement: constantly increase with basic island size, the parameters index on Ji Dao plane realizes that the specification requirement of stable control is more and more higher, is difficult to guarantee.
5, material consumption: constantly increase with basic island size, the chip packing-body overall weight rises, and is difficult to adapt to the compact developing direction of encapsulating products.
Summary of the invention:
The purpose of this utility model is to overcome above-mentioned deficiency, provides that a kind of encapsulating structure degree of freedom is big, package reliability good, encapsulation and specification requirement is low, material consumption is few flat-face saliant-point type packing base-board for electronic device.
The purpose of this utility model is achieved in that a kind of flat-face saliant-point type packing base-board for electronic device, comprise Ji Dao and pin, it is characterized in that Ji Dao and pin are convex dot shape and are distributed in substrate front side, there is thin metal layer to link between salient point and the salient point, Ji Dao is the unit Ji Dao that a plurality of salient points are formed, pin is single salient point, in the single electronic devices and components packaging body that when follow-up encapsulation, forms, the quantity of Ji Dao has one or more, be individual unit Ji Dao or a plurality of unit Ji Dao that a plurality of salient points are formed, pin arrangements is in one or both sides or three sides of Ji Dao, or be trapped among Ji Dao around form the structure of a circle or multi-turn pin.
The utility model flat-face saliant-point type packing base-board for electronic device, the front of described pin is provided with metal level.
The utility model flat-face saliant-point type packing base-board for electronic device, the two front of described pin and Ji Dao be or/and the back side is provided with metal level, and the metal level on the Ji Dao is arranged on the part salient point or all salient points in the base island, unit.
The utility model flat-face saliant-point type packing base-board for electronic device, described pin just, the back side of the back of the body two sides and Ji Dao is provided with metal level.
The utility model flat-face saliant-point type packing base-board for electronic device, the front of described pin is provided with the activating substance layer, is provided with metal level on the activating substance layer.
The utility model flat-face saliant-point type packing base-board for electronic device, the two front of described pin and Ji Dao is provided with metal level or/and the back side is provided with the activating substance layer on the activating substance layer.
The utility model flat-face saliant-point type packing base-board for electronic device, described pin just, the back side of the back of the body two sides and Ji Dao is provided with the activating substance layer, is provided with metal level on the activating substance layer.
The utility model flat-face saliant-point type packing base-board for electronic device, have strong adaptability, be convenient to production, with low cost, best in quality, reliability advantages of higher, get rid of puzzlement for follow-up solution repeats to revise base plate for packaging design to adapt in plurality of specifications chip, the encapsulation process in the packaging body problems such as easily layering, thereby optimized the product structure of electronic devices and components and lay a solid foundation for improving reliability of products intensity.Concrete advantage is:
1, encapsulating structure: relatively independent between chip and the basic island, there is not positive connection between basic island size and the chip size, the degree of freedom is bigger, can adapt to the chip of different size size and specification.
2, package reliability: become block of metal Ji Dao that single plane supports unit Ji Dao, discharged the deformational stress of being heated of block of metal Ji Dao better, thereby effectively reduced integrity problem such as layering into a plurality of salient point planar support; And because relatively independent between Ji Dao and the chip, Ji Dao can effectively strengthen the permission of chip, and Ji Dao need not constantly to increase along with the increase of chip size, thereby has reduced the risk of layering.
3, packaging cost: can adapt at present along with chip design becomes increasingly complex, the chip size specification is also more and more diversified, and the chip of the super-long and super-wide that constantly occurs, need not redesign lead frame or change basic island size, save cost, improved efficient, reduced risk.
4, specification requirement: be convenient to technology control, can adapt to the chip requirement of different size, reduce the technology harshness of designing and manufacturing technique to the parameters index of Ji Dao.
5, material consumption: the miniaturization of basic island, help economical with materials consumption, be fit to very much the compact developing direction of encapsulating products.
Description of drawings:
Fig. 1～11 are each example structure schematic diagram of the utility model.
Embodiment:
Embodiment 1:
Embodiment 1 structure such as Fig. 1, Fig. 1 is a flat-face saliant-point type packing base-board for electronic device, comprise basic island 1 and pin 2, base island 1 and pin 2 are convex dot shape and are distributed in substrate front side, there is thin metal layer 3 to link between salient point and the salient point, base island 1 is the unit Ji Dao that a plurality of salient points are formed, pin 2 is single salient point, in the single electronic devices and components packaging body that when follow-up encapsulation, forms, the quantity on base island 1 has one or more, be individual unit Ji Dao or a plurality of unit Ji Dao that a plurality of salient points are formed, pin 2 is arranged in the one or both sides or three sides on basic island 1, or is trapped among the structure that forms a circle or multi-turn pin on every side on basic island 1.
Embodiment 2:
Embodiment 2 structures such as Fig. 2, it is provided with metal level 4 in the front of pin 2 on the basis that is embodiment 1.
Embodiment 3:
Embodiment 4:
Embodiment 5:
Embodiment 5 structures such as Fig. 5, it on the basis that is embodiment 1, pin 2 just, the back side on the back of the body two sides and basic island 1 is provided with metal level 4.
Embodiment 6:
Embodiment 6 structures such as Fig. 6, it on the basis that is embodiment 1, on pin 2 and basic island 1 the two just, back of the body two sides is provided with metal level 4.
Embodiment 7:
Embodiment 7 structures such as Fig. 7, it is on the basis of embodiment 2, before the front of pin 2 plates metal level 4, plates the activating substance layer earlier.
Embodiment 8:
Embodiment 8 structures such as Fig. 8, it is on the basis of embodiment 3, before the two front of pin 2 and basic island 1 plates metal level 4, plates activating substance layer 5 earlier.
Embodiment 9:
Embodiment 9 structures such as Fig. 9, it is on the basis of embodiment 4, before the two the back side of pin 2 and basic island 1 plates metal level 4, plates activating substance layer 5 earlier.
Embodiment 10:
Embodiment 10 structures such as Figure 10, it is on the basis of embodiment 5, pin 2 just, before the back side on the back of the body two sides and basic island 1 plates metal level 4, plate activating substance layer 5 earlier.
Embodiment 11:
Embodiment 11 structures such as Figure 11, it is on the basis of embodiment 6, on pin 2 and basic island 1 the two just, before back of the body two sides plates metal level, plate the activating substance layer earlier.
Above metal level 4 can be located on the part salient point in the base island, unit or on all salient points.Metal level 4 is gold or silver or copper or tin or nickel or nickel palladium, and metal level can be single or multiple lift, or regional area distributes.Above activating substance 5 is nickel or palladium or nickel palladium.
Claims (10)
1, a kind of flat-face saliant-point type packing base-board for electronic device, comprise Ji Dao (1) and pin (2), it is characterized in that Ji Dao (1) and pin (2) are convex dot shape and are distributed in substrate front side, there is thin metal layer (3) to link between salient point and the salient point, Ji Dao (1) is the unit Ji Dao that a plurality of salient points are formed, pin (2) is single salient point, in the single electronic devices and components packaging body that when follow-up encapsulation, forms, the quantity of Ji Dao (1) has one or more, be individual unit Ji Dao or a plurality of unit Ji Dao that a plurality of salient points are formed, pin (2) is arranged in one or both sides or three sides of Ji Dao (1), or is trapped among the structure that forms a circle or multi-turn pin on every side of Ji Dao (1).
2, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 1, it is characterized in that: the front of described pin (2) is provided with metal level (4).
3, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 1, it is characterized in that: the two front of described pin (2) and Ji Dao (1) is or/and the back side is provided with metal level (4).
4, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 1, it is characterized in that: pin (2) just, the back side of the back of the body two sides and Ji Dao (1) is provided with metal level (4).
5, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 2, it is characterized in that: the front of pin (2) is provided with activating substance layer (5), is provided with metal level (4) on activating substance layer (5).
6, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 3, it is characterized in that: the two front of pin (2) and Ji Dao (1) is provided with metal level (4) or/and the back side is provided with activating substance layer (5) on activating substance layer (5).
7, according to the described a kind of flat-face saliant-point type packing base-board for electronic device of claim 4, it is characterized in that: described pin (2) just, the back side of the back of the body two sides and Ji Dao (1) is provided with activating substance layer (5), is provided with metal level (4) on activating substance layer (5).
8,, it is characterized in that metal level (4) on the described Ji Dao (1) is arranged on the part salient point in the base island, unit or on all salient points according to claim 1 or 2,3,4,5,6,7 described a kind of flat-face saliant-point type packing base-board for electronic device.
9,, it is characterized in that described metal level (4) is gold or silver or copper or tin or nickel or nickel palladium, and metal level is a single or multiple lift according to claim 1 or 2,3,4,5,6,7 described a kind of flat-face saliant-point type packing base-board for electronic device.
10,, it is characterized in that activating substance layer (5) is nickel or palladium or nickel palladium layer according to claim 1 or 2,3,4,5,6,7 described a kind of flat-face saliant-point type packing base-board for electronic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620072876 CN2899111Y (en) | 2006-04-13 | 2006-04-13 | Planar convex-point packing base plate of electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620072876 CN2899111Y (en) | 2006-04-13 | 2006-04-13 | Planar convex-point packing base plate of electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2899111Y true CN2899111Y (en) | 2007-05-09 |
Family
ID=38074443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620072876 Expired - Lifetime CN2899111Y (en) | 2006-04-13 | 2006-04-13 | Planar convex-point packing base plate of electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2899111Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681579A (en) * | 2013-12-05 | 2014-03-26 | 江苏长电科技股份有限公司 | Secondary first-corrosion-then-plating metal frame subtraction burying chip obverse-mounting flat foot structure and technology method |
-
2006
- 2006-04-13 CN CN 200620072876 patent/CN2899111Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681579A (en) * | 2013-12-05 | 2014-03-26 | 江苏长电科技股份有限公司 | Secondary first-corrosion-then-plating metal frame subtraction burying chip obverse-mounting flat foot structure and technology method |
| CN103681579B (en) * | 2013-12-05 | 2016-03-30 | 江苏长电科技股份有限公司 | Secondary etching-prior-to-plametal metal frame subtraction buries the flat leg structure of chip formal dress and process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20070509 |
|
| EXPY | Termination of patent right or utility model |