Background technology
The crack is one of common defective of concrete structure, and the general examination criteria contraction of distress in concrete width is 0.2mm to the maximum.The existence in crack and development can make inner material production such as reinforcing bar corrosion usually, reduce the load-bearing capacity of concrete material, influence the serviceable life of buildings, and severe patient will threaten people's life security.Measure the width of distress in concrete quickly and accurately, judge whether it has exceeded specialized range, significant to ensureing concrete structure safety.At home for the measurement of fracture width, most popular is reading microscope at present.Though it is multiple that the type of distress in concrete reading microscope has, they all are equivalent to an easy microscope in fact, and mainly by lens barrel, optical lens and index dial constitute.Optical lens with the crack enlarged image be the eyepiece focus slightly in the place, the operator can see enlarged image and the rule and the vernier in crack by eyepiece, adjust the edge that vernier is positioned at the crack by index dial, and then make vernier be positioned at another edge in crack, read the value on twice the index dial, its difference is the width in crack.The crack reading microscope is owing to its cheap cost of development is used till today with relative simple method for making always, but simultaneously, also there is a lot of shortcomings in this measuring method: 1. reading process is loaded down with trivial details, and efficiency of measurement is low.For example may exist a lot of cracks to need to check on the construction concrete wall surface later, if each measurement point all needs operating personnel to read the width value in crack by the observation of reading microscope, can expend a large amount of time, moreover some place is the crack on the roof for example, and wanting with the reading microscope measurement is unusual difficulty.2. personnel's subjectivity is bigger, and measuring accuracy is low.For the measurement of the width in crack on the every bit, different people can read different width, even same individual also can produce deviation in twice measuring process, moreover because reading process is loaded down with trivial details, task amount is big, is easy to cause testing staff's fatigue, thereby causes the measurement result mistake.
Along with the CCD technology rapid development, the CCD camera has been applied to fields of measurement more and more widely, and is no exception for the measurement of concrete crack width.A kind of crack microscope also appears now, it uses the CCD camera to take the crack pattern picture, the operator only needs two legs of camera measuring head are placed on the crack, can on display screen, can see the crack pattern picture that is exaggerated, rotate camera a little and make the crack vertical, how much read the width value in crack according to the shared scale mark in crack with rule.This instrument more preceding kind of method in operation is convenient, effectively alleviated the drawback that reading microscope exists to a certain extent on measuring, operating personnel do not need to aim at eyepiece and read fracture width, get final product but directly count the shared number of division in crack on display.But this method equally also is artificial reading, does not still fundamentally overcome the problem of efficiency of measurement and personal error.
The utility model content
The purpose of this utility model is to overcome existing concrete fracture width measuring instrument because end user's part work and part study number, thereby cause measuring process loaded down with trivial details, make troubles to operating personnel, cause the shortcoming that the reading resultant error is big, Measuring Time is long, proposed a kind of concrete crack width measuring instrument with automatic interpretation function based on the DSP technology.
The technical solution of the utility model as shown in Figure 1, is characterized in that, comprises camera, image capture module, DSP, image display, display and peripheral circuit; Camera is used for gathering the crack pattern picture of concrete surface, the output analog video signal; Image capture module carries out analog to digital conversion to the analog video signal that receives, and the digital video signal after will changing is then passed to DSP; Behind the DSP receiving digital video signal, the crack image is handled, calculated the width value in crack, the digital video signal that will have the fracture width value is then passed to image display; Image display converts the digital video signal that receives to analog video signal, shows crack pattern picture and width value on display in real time; Being connected to of described image capture module and dsp chip, video a/d converter in the image capture module links to each other with DSP by digital video data signal, video sampling clock signal and video control signal, when gathering vision signal, DSP control of video sampled clock signal and digital video data signal are exported the image information that collects from the image acquisition module; Being connected to of described image display and dsp chip, video d/a converter in the image display links to each other with DSP by digital video data signal, video sampling clock signal and video control signal, after the crack pattern that collects was as processed finishing, the image information after DSP control of video sampled clock signal and digital video data signal will be handled was input to image display; Described peripheral circuit comprises memory circuit, reset circuit, artificial circuit, key circuit, clock circuit, mode selection circuit and power-switching circuit; Memory circuitry is made up of SDRAM and FLASH ROM flash memory, and they are connected with DSP respectively, and reading in and writing out of its data controlled by DSP, and SDRAM is used for storing image data, and FLASH ROM is used for the loading procedure that powers on of storage apparatus; Reset circuit provides reset signal, resets when pressing reset key; Artificial circuit links to each other with DSP, is used for instrument the power on download and the debugging of loading procedure; Key circuit links to each other with DSP, is used to receive external command, makes instrument carry out corresponding instruction on request; Clock circuit is used to provide system clock; Mode selection circuit mainly links to each other with the model selection pin of dsp chip, is used to set the mode of operation of DSP; Power-switching circuit is used for input voltage is converted to operating voltage.
The utlity model has the automatic interpretation function, the operator only need be placed on camera on the crack, on display, can see the crack pattern picture that is exaggerated, press the beginning treatment button on the instrument, the distress in concrete image that can after seeing through collection on the display, handling, draw and the digital displaying value of fracture width.
The special measurement instrument that this concrete crack width measuring instrument is a kind of high precision, robotization, this instrument is the measuring accuracy height not only, avoided personal error, and it is very simple to operate, reduce Measuring Time, improved work efficiency, greatly reduced labor intensity of operating personnel, therefore reduced generation wrong in the concrete crack width surveying work to a certain extent, significant to ensureing concrete structure safety.
Embodiment
Now the utility model is described further in conjunction with Fig. 2-Fig. 9:
A kind of is core with digital signal processor (DSP), concrete crack width measuring instrument with automatic interpretation function, whole instrument comprises camera, image capture module, DSP, image display and reset circuit, artificial circuit, key circuit, clock circuit, memory circuit, mode selection circuit, power-switching circuit and display.
With reference to Fig. 2, native system selects for use the TMS320DM642 dsp chip of TI company as main process chip, this chip internal is integrated three configurable video ports, these video ports provide the seamless interfacing with video a/d conversion chip, thereby need not to add the requirement that CPLD (CPLD) and FIFO (pushup storage) just can satisfy system design.In native system, the VPO port is used for video acquisition, and frequency acquisition is the highest can to reach 80MHz; The VP2 port is used for video and shows that frequency can reach 110MHz.Wherein, data line VP0/2D[9..2] be used to transmit the digital video frequency flow of 8 BT656 form; VP0/2CTL0 links to each other with the horizontal synchronization pin of collection/display module; VP0/2CTL1 links to each other with the vertical synchronization pin of collection/display module; VP0/2CTL2 links to each other with the field synchronization pin of collection/display module; VP0/2CLK0 links to each other with the clock output pin of collection/display module.
With reference to Fig. 3, the DM642 chip has external memory interface, can realize seamless link with multiple external memory.The address bus of DM642 is 64, therefore in this system, select two SDRAM series connection for use, the capacity of each sheet is 4M*32bit, such two are cascaded and just are equivalent to the SDRAM of a slice 4M*64bit, shared address line and control line, TBE[7..0] be the byte enable signal, enable eight bytes.TED[63..0] be the data signal line of external memory storage; TEA[22..3] be the address signal line of external memory storage; Because SDRAM is dispensed on the CE0 space of DM642 in the system, so TCE0 is as chip selection signal, and when it was low level, SDRAM was enabled; TWE is for writing enable signal, and when it was low level, dsp chip can write data among the SDRAM; TSDRAS is for the row gating signal, and when it was low level, dsp chip sent the row address of read-write SDRAM; TSDCAS is the column selection messenger, and when it was low level, dsp chip sent the column address of read-write SDRAM; TSDCKE is the clock enable signal.
The FLASH of this system is used for storing the loading procedure that powers on.FLASH chip model is the AM29LV800B of AMD, and capacity is 1M*8bit, is dispensed on the CE1 space of DM642.The physical circuit schematic diagram is with reference to figure 4: because this chip can be selected with 8 bit data or 16 transmission data, promptly when the BYTE pin is low level, transmit with 8 bit widths, otherwise, when it is high level, selection is transmitted with 16 bit data width, in native system, with BYTE pin ground connection, with 8 transmission, therefore AM29LV800B uses data line TED[7..0], the DQ15/A-1 pin uses as address wire TEA3, the A[18..0 of AM29LV800B] receive the address bus TEA[22..4 of DSP].RESET# receives systematic reset signal.The RY/BY# signal of AM29LV800B and chip selection signal are received on the ARDY signal of DM642 by an OR circuit, like this, when TCE1# is a low level, when being gating CE1 space, if RY/BY# is a low level, expression FLASH chip also is not ready for, if the RY/BY# high level, expression FLASH is in idle condition, and at this moment system just can carry out read-write operation to FLASH.
DM642DSP has the JTAG emulated port that meets the IEEE1149.1 standard, and it is a kind of boundary scan testing mode, the internal resource that can visit DSP by artificial debugging software and emulator.The physical circuit schematic diagram is with reference to Fig. 5: the JTAG emulated port has 13 signal line, need be connected on the 14 pin slots of standard, and wherein the 6th pin is empty.Pin one on the slot is test mode select signal TMS, pin two is test reset signal TRST#, and pin 3 is input signal of test data TDI, and pin 7 is test data output signal TDO, pin one 1 is the clock signal TCK of test, and pin 9 is a clock feedback signal.
With reference to Fig. 6, the DSP clock input circuit is mainly connected to form by the crystal oscillator of 50MHz and the clock multiplier model selection pin of dsp chip.The system clock incoming frequency is 50MHz, the high-low level combination by CLKMODE0 and CLKMODE1, and the frequency of operation of selecting the DM642 innernal CPU is the clock incoming frequency of 1 times, 6 times or 12 times.
With reference to Fig. 7, key circuit mainly is made up of integrated circuit U1, and model is 74HC08, nA in this integrated circuit and nB are input signal, and nY is an output signal, when and if only if nA and nB is high level simultaneously, nY is a high level, as long as one of them is a low level, nY then is a low level.In native system, the 1A of U1,1B, 2A, 2B receive the GPO[9..11 of DM642 respectively], link to each other with external key simultaneously, when the operator pushed button, for example KEY1 was pressed, GPO9 becomes low level, 1Y also becomes low level, and promptly 3B is a low level, and then 3Y is that EXTINT6 is a low level, to cause interruption this moment, carry out corresponding interrupt routine.
With reference to Fig. 8,, therefore reserve some the dirigibility that means can be good at improving system is set, and bring convenience to debugging for different mode of operations because DM642 supports multiple mode of operation.TEA[20:19] high-low level combination determined the clock input mode of EMIFA interface.If TEA20 is a low level, TEA19 also is a low level, and then selecting provides clock signal by the AECLKIN pin for the EMIFA interface; In like manner, if TEA20 is a low level, TEA19 is a high level, and then the clock frequency of EMIFA interface is 1/4th of a CPU frequency of operation; If TEA20 is a high level, TEA19 is a low level, and then the clock frequency of EMIFA interface is the sixth of CPU frequency of operation.In like manner, TEA[21:20] the high-low level combination determined system to adopt any loading mode that powers on, native system is selected external memory interface (EMIF) load mode for use, promptly comes the loading system program by outside spread F LASH.LENDIAN MODE is big small end model selection pin, if low level, system works under big end pattern, otherwise if high level, system works is under little endian mode, native system is selected little endian mode.
With reference to Fig. 9, system reset circuit mainly is made up of integrated circuit U12, and model is 74HC14.The principle of work of this chip is: if nA is a high level, then nY is a low level, otherwise in like manner.When button S9 was pressed, 1A became low level, and then 1Y becomes high level, because 1Y links to each other with lead with 2A, then 2A is a high level also, and 2Y becomes low level, and 3A also is a low level, 3Y, 4A are high level, and then 4Y is that the RESET signal becomes low level, and whole system is in reset mode.
This surveying instrument in use, the testing staff only needs camera is placed on the crack, can see the crack pattern picture that collects on display, presses to begin to handle button, can see the fracture width value that measures.The utility model is simple, convenient, and is practical, can measure the width of distress in concrete fast accurately, has very strong using value.