CN113923458A - Decoder system capable of storing and converting images and applied to new energy automobile - Google Patents
Decoder system capable of storing and converting images and applied to new energy automobile Download PDFInfo
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Abstract
The invention discloses a decoder system capable of storing and converting images, which is applied to a new energy automobile, and comprises: the invention has the advantages of simple structure, capability of detecting external signals, capability of automatically transmitting pictures and good market value.
Description
Technical Field
The invention relates to the field of new energy automobiles, in particular to a decoder system which is applied to a new energy automobile and can store and convert images.
Background
The new energy automobile is the current mainstream automobile model which reduces or abandons the traditional gasoline or diesel oil driven internal combustion engine, not only protects the environment, but also meets the requirements of the petroleum crisis, and the new energy automobile decoder is an important front-end control device, and can enable the front-end device to generate corresponding actions under the control of a host, and only a decoder main control screen can be installed to play images and sound, and the existing new energy automobile decoder restores the information from the coding form to the original form.
Disclosure of Invention
The invention provides a new energy automobile image decoder system which can store and copy pictures and has a self-function aiming at the defects of the existing new energy automobile decoder.
The technical scheme adopted by the invention for solving the technical problems is as follows:
provided is a decoder system capable of storing and converting images, which is applied to a new energy automobile, and comprises: the main control chip circuit respectively performs bidirectional control with the LCD display circuit, the storage circuit, the network interface circuit, the image unit signal acquisition circuit and the digital-to-analog conversion circuit.
Further, the main control chip circuit includes a chip U2, a first lead of pins 82, 127, 172, 49, 23, 62, 72, 103, 114, 149, 159, 36, 15, 91, 136 of the chip U2 is connected to +3.3V voltage, a second lead is respectively connected to ground through capacitors Cd1, Cd2, Cd3, Cd4, Cd5, Cd6, Cd7, Cd8, 171 pins are connected to ground through resistors 8, a resistor Rd 8 is arranged between the pins 136, 171, a first lead of the pin 38 is connected to +3.3V voltage through a resistor Rd 8, a second lead is connected to ground through filters Cd8, a capacitor Rz 8, a filter capacitor is arranged between the pins 36, a capacitor Cd8, a filter capacitor Cd8, a filter tube 29, a capacitor x 3.3V 3, a second lead is connected to ground through capacitors, a capacitor Rd 8, a capacitor x 3, a capacitor, 90. 135 and 37 pins are grounded, a first lead of a 31 pin is connected with +3.3V voltage through a resistor Rd3, a second lead is connected with the ground through a reset key Sr1, a third lead is connected with a 4 pin of an interface SWD1, a1 pin of the interface SDW1 is connected with +3.3V voltage, 2 and 3 pins are respectively connected with 124 and 137 pins and 5 pins of the main control chip U2 are grounded, a first lead of a 166 pin of the main control chip U2 is connected with +3.3V voltage through a resistor Rd1, a1 pin and a 58 pin of a second lead connector pb1 are respectively connected with 3 pins of the connector pb1, 2 and 4 pins of the connector pb1 are grounded, a 6 pin of the main control chip U2 is connected with +3.3V voltage through a diode Dd1, 81 and 125 pins are respectively connected with the ground through filter capacitors Cd17 and Cd17, a base pin 120 is connected with a triode Q1, an emitter of the triode Q1 is grounded, a collector LS1 of the buzzer LS 23, and a collector of the buzzer is connected with 1V 638 and a buzzer 3R 3 +3 through a buzzer 3, the 2 pin connects LED L11's negative pole through resistance R11, LED Ll 1's positive pole connects +3.3V voltage, main control chip U2's model is STM32F20X/STM32F40X-176, interface SWD 1's model is XH2.54-5P, connector pb 1's model is Header2X2, triode Q1's model is 9013, bee calling organ LS 1's model is Bell.
Further, the LCD display circuit comprises an interface P3, wherein pins 1 of the interface P3 are connected with +5V voltage, pins 2 and 32 are connected with ground, pins 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 are respectively connected with FSMC D0, FSMC D1, FSMC D2, FSMC D3, FSMC D4, FSMC D5, FSMC D6, FSMC D7, FSMC D8, FSMC D9, FSMC D10 and FSMC D11 of the main control chip U2, pins of FSMC D12, FSMC D13, FSMC D14 and FSMC D15, 19, 21, 23, 20, 22 and 24 are respectively connected with FSMC 1, FSMC NWE, LCD BLK, FSMC A16, FSMC NOE, LCD RES and pins of the main control chip U2, pins of 25, 26, 27, 28, 29, 30 and 31 are respectively connected with pins KEY0, KEY1, KEY2, KEY3, KEY4, KEY5 and KEY6 of the main control chip U2, and the type of the interface P3 is FPC _1.0_ 32P.
Furthermore, the memory circuit comprises a chip U3, a flash memory card J5 and a USB interface J4, pins 1, 2, 5 and 6 of the chip U3 are respectively connected with pins SPI2-NSS, SPI2-MISO, SPI2-MOSI and SPI2-SCK of the main control chip U2, pins 3 are connected with +3.3V voltage through a resistor Rs7, pins 4 are grounded, a first pin 8 is connected with +3.3V voltage, a second pin is grounded through a capacitor C32, pins 7 are connected with +3.3V voltage through a resistor Rs6, first pins 1, 2, 3, 5, 7, CMD 8 and CMD 11 of the flash memory card J5 are respectively connected with pins SD D2, SD 3, SD CLK, SD 0, SD D1, INSERT pin and a second pin are respectively connected with pins SD 48, R36 49, R50, R72, R45, R72, a capacitor C45 and a capacitor C45 is arranged between the pins 45 and the pins are grounded, and a capacitor C45 is arranged between the pins 3, and the pins are respectively connected with a capacitor R866 and a capacitor C3, a capacitor C, a capacitor is arranged between the pins, a capacitor C, a capacitor is arranged, a capacitor C, a capacitor, a, C36, USB interface J4's 1 pin connects +5.0V voltage, 4 pin ground connections, 2 pins connect through resistance Rs5 the USB FS DM pin of master control chip U2, 3 pins first lead wire connects through resistance Rs4 the USB FS DP pin of master control chip U2, second lead wire connect through resistance Rs1 the projecting pole of triode Q2, triode Q2's base connects +3.3V voltage, the first lead wire of collecting electrode connects through resistance Rs2 +3.3V voltage, the second lead wire connects through resistance Rs3 the USB Power pin of master control chip U2, the model of chip U3 is W25Q128, flash memory card J5's model is MicroSD, triode Q2's model is 0805.
Further, the network interface circuit includes interfaces P4, P5, P50, P6, where 1, 2, 3, 4, 5, 6 of the interface P4 are respectively connected to the main control chip SPI1_ NSS, SPI1_ SCK, SPI1_ MISO, SPI1_ MOSI, W5500 INT, W5500 nRST, the 1 pin of the interface P5 is grounded, the 4 pins are connected to +5.0V voltage, the 2 and 3 pins are connected to +3.3V voltage, the 1 pin of the interface P50 is connected to +9VA, the 3 pin is connected to-9 VA, and the 2 pin is connected to virtual ground AGND, the 1 pin of the interface P6 is connected to-5 VA, the 3 pin is connected to +5VA, the 2 pin is connected to virtual ground AGND, the model of the interface P4 is Header6, the model of the interface P5 is Digit Power, and the model of the interface P6, P50 is a Header model.
Further, the image unit signal acquisition circuit comprises a chip IC5, a flip-flop IC1, an IC2, an IC3, a differential amplifier IC4 and an interface P1, wherein pins 1 and 5 of the chip IC5 are grounded, pins 2, 29 and 33 are grounded to a virtual ground, a first pin 3 is connected with a voltage +5V and a second pin is grounded, a first pin 4 is connected with a voltage +5V and a second pin is connected with a virtual ground AGND through a capacitor C1, a first pin 6 is connected with a voltage +3.3V and a second pin is grounded, a first pin 7 is connected with a pin 2 of the flip-flop IC1 and a pin 4 of the flip-flop IC3, a pin 5 of the flip-flop IC1 is connected with a voltage +3.3V and a pin 3 is grounded, a first pin 4 is connected with a connecting piece JP1 and a resistor R3 is connected with an ADC _ RCK pin of the main control chip 2, a second pin is connected with an IC2 and a pin IC 35 and a pin 3.3 is connected with a voltage + 3V of the flip-flop IC2, the 3 pin is grounded, the 4 pin is connected with the ADC RCK pin of the main control chip U2 through a connecting sheet JP2 and a resistor R3, the 3 pin of the trigger IC3 is grounded, the 5 pin is connected with the +3.3V voltage, the 2 pin is connected with the 3 pin of a resistor W1 and the 1 pin of a second lead wire of a capacitor C7, the 1 pin of the resistor W1 is connected with the +3.3V voltage through a resistor R5, the 2 pin is connected with the ground through a resistor R6, the 2 pin of the capacitor C7 is grounded through a resistor R9 and the second lead wire is connected with the ADC CLK pin of the main control chip U2, the first leads of the pins 11, 12, 13, 14, 15, 16 and 17 of the chip IC5 are respectively connected with the AD 5, R5, AD 3614, AD 5, AD 3614, AD 14, AD 5, AD 14, AD, 14. The first pins 11, 10, 18, 19, 20, 21, 22, 23, 24, 25 are respectively connected with pins AD 7, AD8, AD9, AD 10, AD 11, AD 12, AD 13, AD 14 of the main control chip U2 through resistors R23, R25, R26, R27, R28, R29, R30, R32, the second pins are respectively connected with pins 16, 15, 14, 13, 12, 11, 10, 9 of a chip capacitor RA1, 1, 2, 3, 4, 5, 6, 7, 8 pins of the chip capacitor RA1 are respectively connected with a voltage of +3.3V, the pins 1, 2, 3, 4, 5, 6, 7, 8 pins of the chip RA2 are respectively connected with a voltage of +3.3V, the pins 28 of the IC5 are respectively connected with a voltage of +5, a second pin AGND 28, AGND 31 and AGND 8632 through resistors R23, a virtual capacitor ND 72, a virtual ground connector 368632, a virtual ground, The 1 pin of E6 is connected with the 2 pin of JP3, the 2 pins of capacitors C20 and E6 are connected with virtual AGND, the 35 pin of chip IC5 is connected with virtual AGND through a resistor R31, the 36 pin is connected with virtual AGND through a capacitor C17, the 37 pin is connected with virtual AGND through a capacitor C14, capacitors C18, E5 and 39 pin first lead is connected with virtual AGND through a capacitor C15 and a second lead is connected with the 2 pin of differential amplifier IC4, the 41 pin first lead is connected with virtual AGND through a capacitor C13, the second lead is connected with +5VA through a diode D1, the third lead is connected with virtual ground through a diode D2, the fourth lead is connected with the 1 pin of interface 2, the 2 pin of interface 573J 5 is connected with virtual ground, a resistor R18 is arranged between the 1 pin and the 2 pin, the 42 pin of chip IC5 is connected with virtual AGND through a capacitor C24 and a second lead 599 and the differential amplifier IC 599, the differential amplifier IC4 is characterized in that a 1-pin first lead is connected with virtual ground AGND, a second lead is connected with a 4-pin through a resistor R24, a 2-pin first lead is connected with virtual ground through a capacitor C12, a 3-pin first lead is connected with +5VA, a second lead is connected with virtual ground through a capacitor E3, a third lead is connected with ground through a capacitor C8, an 8-pin is connected with a 1-pin of an interface J1 through a resistor R11, a resistor R7 is arranged between the 5-pin and the 8-pin, a 2-pin of the interface J1 is connected with virtual ground, a resistor R12 is arranged between the 1-pin and the 2-pin, a 1-pin of the interface P1 is connected with a Sensor CLK pin of a main control chip U2 through a resistor R1, a 2-pin and a 3-pin of the main control chip are respectively connected with a Sensor Line pin and a 4-pin ground, the chip IC5 is AD9240, the flip-flop IC1, the IC2 and the IC3 are 74, the RA 8138, the RA 8153 and RA 863-K-type AD 8416 of the interface P2, The model of J1 is A _ IN, and the model of the interface P1 is Header 4.
Furthermore, the digital-analog conversion circuit comprises a chip U1, a DA1 and an interface P2, wherein a2 pin first lead of the chip U1 is connected with +9VA, a second lead of the chip U1 is grounded through a capacitor Cc2, a 4 pin first lead of the chip U1 is connected with +9VA and a second lead of the chip U1 is grounded through a capacitor Cc1, a 6 pin first lead of the chip U355V is connected with Vref 5V voltage, a second lead of the chip DA1 is grounded through a capacitor Cerf1, 8 pins, 1 pins and 2 pins of the chip DA1 are respectively connected with SPI3_ NSS, SPI3_ SCK and SPI3_ MOSI pins of the chip U2, 7 pins are connected with +3.3V voltage, a 6 pin first lead of the chip DA is grounded, a second lead of the chip DA 42 is connected with a 3 pin of an operational amplifier U2, 5 pins and 3 pins of the operational amplifier U37 through a capacitor C25, a 4 pin of the first lead of the amplifier and a resistor R37, 4 pins of the operational amplifier U x2 are connected with-9 VA through 1 pin of a capacitor C30 and 2 pins of a capacitor C31, 2 pins of the capacitor C30 and 1 pin of the capacitor C31 are connected with virtual AGND, 6 pins of the operational amplifier are connected with 2 pins of the operational amplifier through a resistor R39, a 7 pin first lead is connected with +9VA and a second lead is connected with virtual AGND through a capacitor C26, a capacitor C27 is arranged at two ends of the capacitor C26, 2 pins of the operational amplifier U x 1 are connected with 6 pins through a resistor R38, a capacitor C22 is arranged at two ends of the resistor R38, 3 pins of the operational amplifier U x 1 are grounded through a resistor R41, 4 pins are connected with-9 VA through 1 pin of a capacitor C28 and 2 pins of a capacitor C29, 2 pins of the capacitor C28, 1 pin of the capacitor C29 is connected with virtual AGND, 7 pin +9VA is connected with the first lead and the second lead is grounded through a capacitor C23, a capacitor C24 is disposed at both ends of the capacitor C23, 6 pins of the operational amplifier are connected with 1 pin of an interface J3 through a resistor R40, 2 pins of the interface J3 are connected with a virtual ground, 3 pins of the interface P2 are connected with the Sim SNYC pin of the main control chip U2 through a resistor R33, 4 pins are grounded, a1 pin first lead is contacted with the 2 pin of a generator IC9 through a capacitor 21, a2 pin first lead is connected with the 4 pin of a trigger IC11, a second lead is connected with the Sim Line pin of the main control chip U2 through a connector JP9, 4 pins of the trigger IC9 are connected with the Sim CLK pin of the main control chip U2, 3 pins are grounded, 5 pins are connected with a +3.3V voltage, 3 pins of a2 pin resistor W2, 1 pin of the resistor W2 is connected with a +3.3V voltage through a resistor R6, 2 pins are grounded through a resistor R35, 5 pins of the trigger IC 27 are connected with a +3 pins of the trigger IC 73727, and a trigger IC10 pin is connected with a ground voltage, and a trigger IC10 pin is connected with the 3 pin 3 +3 voltage of the trigger IC10, the 2 pins of the trigger IC10 are connected with the Sim Line pin of the main control chip U2, a connector JP8 is arranged between the 2 pins and the 4 pins, the 5 pins are connected with +3.3V voltage, the 3 pins are grounded, the model of the chip U1 is REF5050, the model of the chip DA1 is DAC8801, the model of the interface J3 is A _ OUT, the model of the interface P2 is Header4, the models of the operational amplifiers U1 and U2 are OPA277_ SOP8, and the models of the trigger IC9, the IC11 and the IC10 are 74LVC1G 14.
Compared with the prior art, the invention has the beneficial effects that:
the digital image processing system has two functions of ADC and DAC, can store images through the SD card, can copy analog images into the SD card through the USB interface, and can enable a user to observe the working mode of the whole system through the LCD display circuit.
Drawings
FIGS. 1-4 are schematic diagrams of the circuit structure of the main control chip of the present invention;
FIG. 5 is a schematic diagram of an LCD display circuit according to the present invention;
FIG. 6 is a schematic diagram of a memory circuit according to the present invention;
FIG. 7 is a schematic diagram of a network interface circuit according to the present invention;
FIG. 8 is a schematic diagram of an image unit signal acquisition circuit according to the present invention;
FIG. 9 is a schematic diagram of a digital-to-analog conversion circuit according to the present invention.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. The preferred embodiments of the present invention are shown in the drawings, but the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention is described in detail below with reference to the accompanying fig. 1-9.
The working principle of the invention is as follows:
the MCU generates a trigger clock signal to trigger pixel conversion of the image acquisition unit, the MCU controls the A/D acquisition of the pixel signal of the image acquisition unit and receives a line end signal of the image acquisition unit, the MCU transmits the acquired image data of the whole image acquisition unit to the PC-side software through a network, the number and the frequency of the trigger clock signal generated by the MCU can be set through the PC-side software, and the MCU stores the acquired image data of the whole image acquisition unit into the SD card.
Claims (7)
1. A decoder system capable of storing and converting images and applied to a new energy automobile comprises: the main control chip circuit respectively performs bidirectional control with the LCD display circuit, the storage circuit, the network interface circuit, the image unit signal acquisition circuit and the digital-to-analog conversion circuit.
2. The decoder system of claim 1, wherein the main control chip circuit comprises a chip U2, a first lead of pins 82, 127, 172, 49, 23, 62, 72, 103, 114, 149, 159, 36, 15, 91 and 136 of the chip U2 is connected to +3.3V voltage, a second lead is respectively connected to ground through a capacitor Cd1, Cd2, Cd3, Cd4, Cd5, Cd6, Cd7, Cd8, Cd9, Cd10, Cd11, Cd12, Cd13, Cd14 and Cd14, the pin 171 is connected to ground through a resistor Cd14, a resistor Rd 14 is arranged between the Cd pins and the pin 171, a first lead of the pin 38 is connected to +3.3V voltage through a resistor L14, a second lead is connected to ground through a filter capacitor Cd14, a filter Cz 14, a second lead of the pin 14, a capacitor Cd14, a filter Cz 14, a capacitor Cd14, a filter Cz 14, a second lead of the pin 14 and a filter Cz 14 are connected to ground through a capacitor Cz 14, 29. a resistor Rz1, crystal oscillators Xz1, 126, 48, 22, 61, 71, 102, 113, 148, 158, 14, 90, 135 and 37 are grounded among pins 30, a first lead of the pin 31 is connected with +3.3V voltage through a resistor Rd3, a second lead is grounded through a reset key Sr1, a third lead is connected with 4 pins of an interface SWD1, a1 pin of the interface SDW1 is connected with +3.3V voltage, pins 2 and 3 are respectively connected with pins 124 and 137 of the main control chip U2, a 5 pin is grounded, a first lead of a 166 pin of the main control chip U2 is connected with +3.3V voltage through a resistor Rd1, pins 1 and 58 of a second lead connector pb1 are connected with a 3 pin of the connector pb1, pins 2 and 4 of the connector pb1 are grounded, a 6 pin of the main control chip U2 is connected with +3.3V voltage through a diode Dd1, a voltage 81, a filter pin 125 and a filter pin Cd 3985 are respectively connected with a triode 17, the emitting electrode of the triode Q1 is grounded, the collecting electrode is connected with the 2 pin of the buzzer LS1, the 1 pin of the buzzer LS1 is connected with +3.3V voltage through a resistor R43, the 2 pin is connected with the cathode of the light-emitting diode L11 through a resistor R11, the anode of the light-emitting diode Ll1 is connected with +3.3V voltage, the model of the main control chip U2 is STM32F20X/STM32F40X-176, the model of the interface SWD1 is XH2.54-5P, the model of the connector pb1 is Header2X2, the model of the triode Q1 is 9013, and the model of the buzzer LS1 is Bell.
3. The decoder system capable of storing and converting images applied to a new energy vehicle as claimed in claim 1, wherein the LCD display circuit comprises an interface P3, pins 1 and 2 and 32 of the interface P3 are connected to +5V, pins 2 and 32 are connected to ground, pins 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 and 18 are respectively connected to FSMC D0, FSMC D1, FSMC D2, FSMC D3, FSMC D4, FSMC D5, FSMC D6, FSMC 7, FSMC D8, FSMC D9, FSMC D10, FSMC D11, FSMC D12, FSMC D13, FSMC D14, FSMC D15, pins 19, 21, 23, 20, 22 and 68624 of the main control chip 2, pins FSMC 2, fswe, FSMC D695, FSMC D0, FSMC D8227, FSMC D0, FSMC D27, FSMC D8427, FSMC D27, FSMC 30, FSMC 27 and FSMC 30, FSMC 27 are respectively connected to the main control chip 2, fsu of the interface P9, the interface P21, the interface P interface, the host chip 32, the host chip of the host chip 2, the host chip of the host, KEY1, KEY2, KEY3, KEY4, KEY5 and KEY6 pins, wherein the model of the interface P3 is FPC _1.0_ 32P.
4. The decoder system of claim 1, wherein the storage circuit comprises a chip U3, a flash memory card J5, and a USB interface J4, pins 1, 2, 5, and 6 of the chip U3 are respectively connected to pins SPI2-NSS, SPI2-MISO, SPI2-MOSI, and SPI2-SCK of the main control chip U2, pin 3 is connected to a voltage of +3.3V through a resistor Rs7, pin 4 is grounded, pin 8 is connected to a voltage of +3.3V through a capacitor C32, pin 7 is connected to a voltage of +3.3V through a resistor Rs6, and pin 1, 2, 3, 5, SD 7, 8, and pin 11 of the flash memory card J5 are respectively connected to pins SD 2, SD 3, CMD, CLK, D0, SD 1, SD 7, SD 48, and pin INSERT 48 of the main control chip U2 through a resistor Rs 48, The flash memory card comprises a main control chip U2, a flash memory card and R49, R50, R45, R46, R47, R44, 4 pins are connected with +3.3V voltage, 6 pins are grounded, capacitors C35 and C36 are arranged between the 4 pins and the 6 pins, 1 pin of the USB interface J4 is connected with +5.0V voltage, 4 pins are grounded, 2 pins are connected with a USB FS DM pin of the main control chip U2 through resistors Rs5, a first 3 pin is connected with a USB FS DP pin of the main control chip U2 through resistors Rs4, a second pin is connected with an emitter of a triode Q2 through resistors Rs1, a base of the triode Q2 is connected with +3.3V voltage, a first collector pin is connected with +3.3V voltage through resistors Rs2, a second lead is connected with a USB Power pin of the main control chip U2 through resistors Rs3, the type of the chip U5 is W25Q128, the type of the J5 is a type is a MicroSD type, and the type of the flash memory card is a type 08024 type.
5. The decoder system of claim 1, wherein the network interface circuit comprises interfaces P4, P5, P50 and P6, the interfaces P4 are connected to SPI1_ NSS, SPI1_ SCK, SPI1_ MISO, SPI1_ MOSI, W5500 INT and W5500 nRST respectively at 1, 2, 3, 4, 2 and 3 pins of the interface P5 are connected to ground, the interfaces P50 is connected to +9VA, 3 to-9 VA and 2 to virtual ground AGND, the interfaces P6 is connected to-5 VA, 3 to +5VA and 2 to virtual ground AGND, the interfaces P4 is a Header6, the interfaces P5 is a Header 5, and the interfaces P5963 is a Header 39596, the interfaces P583 is a Header 5 and the interfaces P596 are a Header 39596.
6. The decoder system capable of storing and converting images for a new energy automobile according to claim 1, wherein the image unit signal acquisition circuit comprises a chip IC5, a flip-flop IC1, an IC2, an IC3, a differential amplifier IC4 and an interface P1, pins 1 and 5 of the chip IC5 are grounded, pins 2, 29 and 33 are connected to a virtual ground, a pin 3 is connected to a first pin +5V voltage and a pin second is grounded, a pin 4 is connected to a first pin +5V voltage and a pin second is connected to a virtual ground AGND through a capacitor C1, a pin 6 is connected to a first pin +3.3V voltage and a pin second is grounded, a pin 7 is connected to a pin 2 of the flip-flop IC1 and a pin 4 of the flip-flop IC3, a pin 5 of the flip-flop IC1 is connected to a voltage +3.3V and a pin 3 is grounded, and a pin 4 is connected to a first pin JP1 and a pin R3 of the main control resistor R2 and an ADC K pin of the chip RCU 2, The second lead is connected with the 2 pin of the trigger IC2, the 5 pin of the trigger IC2 is connected with +3.3V voltage, the 3 pin is grounded, the 4 pin is connected with the ADC RCK pin of the main control chip U2 through a connecting sheet JP2 and a resistor R3, the 3 pin of the trigger IC3 is grounded, the 5 pin is connected with +3.3V voltage, the 2 pin is connected with the 3 pin of a resistor W1 and the 1 pin of a second lead is connected with the 1 pin of a capacitor C7, the 1 pin of the resistor W1 is connected with +3.3V voltage through a resistor R5, the 2 pin is connected with ground through a resistor R6, the 2 pin of the capacitor C7 is grounded through a resistor R9 and the second lead is connected with the ADC CLK pin of the main control chip U2, and the first leads of the chips IC5 are connected with the AD chips AD 72, AD chips 13, AD chips AD 72, AD chips 13, AD chips AD 72, 13 and AD chips AD 72D 13, The AD D5, AD D6 pins, the second lead pins are respectively connected with the 16, 15, 14, 13, 14, 11, 10 pins of a patch capacitor RA2, the first lead pins of 18, 19, 20, 21, 22, 23, 24, 25 pins are respectively connected with the AD D7, AD D8, AD D9, AD D10, AD D11, AD D12, AD D13, AD D14 pins and the second lead pins are respectively connected with the 16, 15, 14, 13, 12, 11, 10, 9 pins of a patch capacitor RA1, the 1, 2, 3, 4, 5, 6, 7, 8 pins of the patch capacitor RA1 are respectively connected with a +3.3V voltage, the 1, 2, 3, 4, 5, 6, 7, 8 pins of the patch capacitor RA2 are respectively connected with the AD 3.3V voltage via a virtual lead pin ND 31, 7, 8 pins of the patch capacitor RA1 are respectively connected with the virtual ground of the AGND 31, the virtual lead pin of the virtual chip ND 3631, the virtual lead pin of the virtual lead 5, the virtual lead pin of the AGVA 863, the virtual lead pin of the virtual chip ND 31, a first 32 pin lead is connected with a virtual ground through connectors JP4 and JP5, a second lead is connected with a2 pin of JP3 through a1 pin of capacitors C20 and E6, 2 pins of the capacitors C20 and E6 are connected with a virtual ground AGND, 35 pins of the chip IC5 are connected with a virtual ground AGND through a resistor R31, 36 pins are connected with a virtual ground AGND through a capacitor C17, 37 pins are connected with a virtual ground AGND through a capacitor C14, capacitors C18, E5 and 39 pins are arranged between the pins 36 and 37, a first lead is connected with a virtual ground through a capacitor C15, a second lead is connected with a2 pin of the differential amplifier IC4, a first 41 pin is connected with a virtual AGND through a capacitor C13, a second lead is connected with a +5VA through a diode D1, a third lead is connected with a virtual ground through a diode D2, a fourth lead is connected with a1 pin of an interface J2, a virtual ground is connected between a2 pin of the interface J2, a ground is connected with a second pin 2 pin of the interface J631 and a virtual ground, a second pin of the interface J599, a virtual AGND is arranged between the first pin R9 and the chip C599 and the first lead 599, The second lead is connected with the 5 pin of the differential amplifier IC4 through the 1 pin of a connector JP3 and a resistor R10, the 1 pin of the differential amplifier IC4 is connected with a virtual ground AGND through the first lead, the second lead is connected with the 4 pin through the resistor R24, the 2 pin is connected with a virtual ground through a capacitor C12, the 3 pin of the differential amplifier IC4 is connected with +5VA through the first lead, the second lead is connected with a virtual ground through a capacitor E3, the third lead is connected with the ground through a capacitor C8, the 8 pin is connected with the 1 pin of an interface J638 through a resistor R68692, a resistor R7 is arranged between the 5 pin and the 8 pin, the 2 pin of the interface J1 is connected with the virtual ground, a resistor R12 is arranged between the 1 pin and the 2 pin, the 1 pin of the interface P1 is connected with the Sensor pin CLK of the U2 through a resistor R1, the 2 pin and the 3 pin are respectively connected with the Sensor Line pin and the 4 pin of the main control chip IC5, the type AD model is AD9240, the trigger IC2, the model number of the differential amplifier IC 4624, the model LVAD model number of the differential amplifier IC 8124 and the model number of the differential amplifier IC 4624, the model of each of the patch capacitors RA1 and RA2 is 4K7_5% _ 0402 _16P8R, the model of each of the interfaces J2 and J1 is A _ IN, and the model of each of the interfaces P1 is Header 4.
7. The decoder system capable of storing and converting images applied to a new energy automobile according to claim 1, wherein the digital-analog conversion circuit comprises chips U1, DA1 and an interface P2, the chip U1 has 2 pins with a first lead connected to +9VA and a second lead connected to ground via a capacitor Cc 483 6, the chip U1 has 4 pins with a first lead connected to +9VA and a second lead connected to ground via a capacitor 1, the chip DA1 has 8 pins with 1 and 2 pins with Cc connected to SPI3_ NSS, SPI3_ SCK and SPI 7_ MOSI of the chip U2 respectively, the chip DA has 7 pins with a voltage of +3.3V, the chip DA1 has 8 pins with 1 and 2 pins with Cc connected to ground via a resistor R42, the operational amplifier U2 has 3 pins with 5 and 3 pins connected to 2 pins with 2, 6 pins with 5 and 25 pins with C25 pins with 2, the 4 pins of the first lead wire are connected with Vref 5V, the second lead wire is connected with the 2 pins of an operational amplifier U1 through a resistor R37, the 4 pins of the operational amplifier U2 are connected with-9 VA through the 1 pin of a capacitor C30 and the 2 pins of a capacitor C31, the 2 pins of the capacitor C30 and the 1 pin of the capacitor C31 are connected with virtual ground AGND, the 6 pins of the operational amplifier U are connected with the 2 pins of the operational amplifier through a resistor R39, the 7 pins of the first lead wire are connected with +9VA and the second lead wire are connected with virtual ground AGND through a capacitor C26, a capacitor C27 is arranged at two ends of the capacitor C26, the 2 pins of the operational amplifier U1 are connected with the 6 pins through a resistor R38, a capacitor C22 is arranged at two ends of the resistor R38, the 3 pins of the operational amplifier U1 are connected with ground through a resistor R41, and the 4 pins of the capacitor C28 are connected with the 2 pins of a capacitor C29 and the 2 pins of the capacitor C9-VA and the capacitor C28, A1 pin of the capacitor C29 is connected with virtual ground AGND, a 7 pin of the capacitor C9 is connected with +9VA and a second pin of the operational amplifier is connected with ground through a capacitor C23, a capacitor C24 is arranged at two ends of the capacitor C23, a 6 pin of the operational amplifier is connected with a1 pin of an interface J3 through a resistor R40, a2 pin of the interface J3 is connected with virtual ground, a 3 pin of the interface P2 is connected with a Sim SNYC pin of the main control chip U2 through a resistor R33, a 4 pin of the interface P2 is connected with ground, a1 pin of the operational amplifier is connected with a2 pin of the trigger IC9 through a capacitor 21, a2 pin of the interface P3552 is connected with a 4 pin of the trigger IC11, a second pin is connected with a Sim Line pin of the main control chip U2 through a connector JP9, a 4 pin of the trigger IC9 is connected with a Sim CLK pin of the main control chip U2, a 3 pin of the trigger IC9 is connected with ground, a 5 pin is connected with +3.3V voltage, a2 pin of the resistor W2 is connected with a1 pin of the resistor W2 + 3V voltage through a resistor R34, the 2 pin is grounded through a resistor R35, the 5 pin of the trigger IC11 is connected with +3.3V voltage, the 3 pin is grounded, the 2 pin is connected with the 4 pin of the trigger IC10, the 2 pin of the trigger IC10 is connected with the Sim Line pin of the main control chip U2, a connector JP8 is arranged between the 2 pin and the 4 pin, the 5 pin is connected with +3.3V voltage, the 3 pin is grounded, the model of the chip U1 is REF5050, the model of the chip DA1 is DAC8801, the model of the interface J3 is A _ OUT, the model of the interface P2 is Header4, the model of the operational amplifiers U1 and U2 is OPA277_ SOP8, and the models of the trigger IC9, IC11 and IC10 are 74LVC1G 14.
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