CN214544375U

CN214544375U - MQA-based full-decoding output high-definition audio system

Info

Publication number: CN214544375U
Application number: CN202120930413.5U
Authority: CN
Inventors: 邓自成; 罗广豪
Original assignee: Pawpaw Ic Electronics Co ltd
Current assignee: Pawpaw Ic Electronics Co ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2021-10-29
Anticipated expiration: 2031-04-30

Abstract

The utility model is suitable for an audio frequency decoding technology improves the field, provides a based on MQA decodes output high definition audio system entirely, put module, storage module, power supply conversion module and switching module including audio frequency processing module, analog electronic module, power amplifier/fortune, switching module's output is connected audio frequency processing module's input, audio frequency processing module's output is connected analog electronic module's input, analog electronic module's output is connected the input of module is put to power amplifier/fortune, storage module's output is connected audio frequency processing module's input, power supply conversion module's output is connected audio frequency processing module's input. By utilizing the high resolution and high sampling support of the USB, the structure is simpler, the use is more convenient, and the cost is low. The full decoding is carried out through the single-chip hard MQA, so that the analysis is simpler, the utilization rate is high, and the analysis rate is effectively improved.

Description

MQA-based full-decoding output high-definition audio system

Technical Field

The utility model belongs to the technical improvement field of audio decoding, especially, relate to an output high definition audio system based on MQA decodes entirely.

Background

With the continuous development of the audio field, people pursue higher and higher sound quality. The traditional sound card can already support the transmission of high-specification high-quality audio, but because of the limitation of network bandwidth, the network music streaming list of today can only provide CD-level sound quality, and the Hi-Res audio can be compressed to the size of CD-level sound quality only through MQA coding technology, so that the network streaming Hi-Res becomes possible. Therefore, to realize the network streaming Hi-Res, the sound card device is required to support the transmission of high-specification audio, and the sound card device is also required to have the capability of MQA decoding. Although most products on the market can support MQA decoding, only partial decoding of MQA can be performed, or a decoding chip is added at the later stage for realization.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an output high definition audio system based on MQA decodes entirely, aims at solving foretell technical problem.

The utility model discloses a realize like this, a decode output high definition audio system entirely based on MQA, decode output high definition audio system entirely based on MQA and include that audio processing module, analog electronic module, power amplifier/fortune are put module, storage module, power supply conversion module and switching module, switching module's output is connected audio processing module's input, audio processing module's output is connected analog electronic module's input, analog electronic module's output is connected the input of power amplifier/fortune is put the module, storage module's output is connected audio processing module's input, power supply conversion module's output is connected audio processing module's input.

The utility model discloses a further technical scheme is: the audio processing module comprises a microprocessor, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a resistor R20, a light emitting diode LED 20, a light emitting diode 20, a clock LED 20, a clock output end of the audio processing module, a clock LED 20, a clock output end of the audio processing module, and a clock unit of the audio processing module, the microprocessor comprises a chip U2A, a chip U2B, a chip U2C, a chip U2D and a chip U2E, wherein the 31 st pin of the chip U2A is connected with one end of the resistor R23, the 57 th pin of the chip U2 23 is connected with one end of the resistor R23, the 58 th pin of the chip U2 23 is connected with one end of the resistor R23, the 3 rd pin of the chip U2 23 is connected with one end of the resistor R23, the 4 th pin of the chip U2 23 is connected with one end of the resistor R23, the 5 th pin of the chip U2 23 is connected with one end of the resistor R23, the 7 th pin of the chip U2 23 is connected with one end of the resistor R23, the 112 th pin of the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the 72 th pin of the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the anode of the chip U2 23, the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the anode of the chip 23, the chip U2 23, the chip U72 is connected with the anode of the chip U72 through the anode of the resistor R23, the chip 23, the 84 th pin of the chip U2B is connected to the anode of the LED6 through the resistor R35, the 75 th pin of the chip U2B is connected to the anode of the LED7 through the resistor R36, the 76 th pin of the chip U2B is connected to the anode of the LED8 through the resistor R37, the 77 th pin of the chip U2B is connected to the anode of the LED10 through the resistor R39, the 44 th, 105 th, 6 th, 14 th, 19 th, 29 th, 42 th, 52 th, 67 th, 78 th, 83 th, 92 th, 110 th and 111 th pins of the chip U2C are connected to one end of the capacitor C17, one end of the capacitor C18, one end of the capacitor C19, one end of the capacitor C20, one end of the capacitor C21, one end of the capacitor C22 and one end of the capacitor C23, the pin 103 th pin of the chip U2C is connected to one end of the capacitor C30 and one end of the resistor R7377, the other end of the chip U2, the resistors U24, 36, 3687458, the resistors R73, the resistors R72, the other ends of the resistors 20, 9, the resistors 53, the pins 11, the resistors 53, the pins 11, the pins 14, the resistors 72, the pins 11, the resistors 72, the pins 11, the pins 23, the resistors 72, the pins 11, the pins 14, the pins of the resistors R49, the resistors R23, the pins of the resistors R23, the pins of the resistors R23, the resistors R, One end of a capacitor C11, one end of a capacitor C12, one end of a capacitor C13, one end of a capacitor C14, one end of a capacitor C15, one end of a capacitor C16, one end of a capacitor C24, one end of a capacitor C25, one end of a capacitor C26, one end of a capacitor C27, one end of a capacitor C28 and one end of a capacitor C29, wherein the 124 th pin of the chip U2D is connected with one end of the resistor R13, the 45 th pin of the chip U2E is connected with one end of the resistor R1, and the 48 th pin of the chip U2E is connected with one end of the resistor R2.

The utility model discloses a further technical scheme is: the audio clock unit comprises a crystal oscillator Y1, a capacitor C31, a capacitor C32, a crystal oscillator Y2, a binding post P2, a chip U5, a capacitor C33, a resistor R10, a resistor R11 and a resistor R12, wherein the 4 th pin of the crystal oscillator Y1 is grounded through the capacitor C31, the 3 rd pin of the crystal oscillator Y1 is respectively connected with one end of the capacitor C34, the 3 rd pin of the crystal oscillator Y2 and the 1 st pin of the binding post P2, the 4 th pin of the crystal oscillator Y2 is grounded through the capacitor C2, the 2 nd and 4 th pins of the binding post P2 are respectively connected with the 1 st, 3 rd and 6 th pins of the chip U2, the 8 th pin of the chip U2 is grounded through the capacitor C2, the 7 th pin of the chip U2 is connected with one end of the resistor R2, the 5 th pin of the chip U2 is connected with one end of the resistor R2.

The utility model discloses a further technical scheme is: the storage module comprises a chip U6, a resistor R16, a resistor R14, a resistor R15 and a capacitor C36, wherein the 3 rd pin of the chip U6 is connected with one end of the resistor R15, the 1 st pin of the chip U6 is connected with one end of the resistor R14, the 7 th pin of the chip U6 is used for knowing one end of the resistor R16, and the 8 th pin of the chip U6 is connected with one end of the capacitor C36.

The utility model discloses a further technical scheme is: the analog electronic module comprises a crystal oscillator Y3, a capacitor C35, a chip U7 and a capacitor C37, wherein

pins

1 and 4 of the crystal oscillator Y3 are respectively connected with a power supply 3.3V, a pin 3 of the crystal oscillator Y3 is connected with a pin 125 of the chip U2, pins 124 and 123 of a chip U2D are respectively connected with a pin 1 of the chip U7, and a pin 5 of the chip U7 is grounded through the capacitor C37.

The utility model discloses a further technical scheme is: the patching module comprises a connecting terminal P3, wherein the 9 th pin of the connecting terminal P3 is connected with the 1 st pin of the chip U7.

The utility model discloses a further technical scheme is: the power amplifier/operational amplifier module comprises a chip U8 and a binding post P7-level capacitor C38, wherein the 5 th pin and the 6 th pin of the chip U8 are grounded through the capacitor C38 respectively, and the 4 th pin of the chip U8 is connected with the 1 st pin and the 3 rd pin of the binding post P7 respectively.

The utility model discloses a further technical scheme is: the power supply conversion module comprises a chip U1, a chip U3, a wire holder P1, a capacitor C2, a safety FB1, a capacitor C1, a capacitor C3, a capacitor C4, a light emitting diode LED1, a resistor R6, a chip U4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, an inductor L8 and an inductor L8, wherein the 3 rd pin of the chip U8 is respectively connected with the 3 rd pin of the chip U8 and the 46 th pin of the chip U2 8, the 5 th pin of the chip U8 is respectively connected with the 2 nd pin of the chip U8 and the 47 th pin of the chip U2 8, the 1 st pin of the chip U8 is connected with the 1 st pin of the wire holder P8, the first pin of the wire holder P8 is respectively connected with the positive terminal of the capacitor C8, and the other terminal of the capacitor C8, and the resistor C8, the positive terminal of the resistor C8, the other terminal of the resistor C8, and the other terminal of the resistor C8 are respectively connected with the positive terminal of the resistor C8, The first pin 4 of the chip U7 is connected to one end of the resistor R3, the second pin of the resistor R3 is connected to one end of the diode LED1, one end of the capacitor C8, one end of the resistor R4 and one end of the inductor L1, the third pin 3 of the chip U4 is connected to the other end of the inductor L1, the first pin 1 of the chip U4 is connected to the other end of the resistor R4 and one end of the resistor R7, the third pin 8 of the chip U4 is connected to one end of the resistor R5 and one end of the resistor R5, the fourth pin 6 of the chip U5 is connected to one end of the inductor L5, and the other end of the inductor L5 is connected to the other end of the resistor R5, one end of the capacitor C5 and one end of the capacitor C5.

The utility model has the advantages that: by utilizing the high resolution and high sampling support of the USB, the structure is simpler, the use is more convenient, and the cost is low. The full decoding is carried out through the single-chip hard MQA, so that the analysis is simpler, the utilization rate is high, and the analysis rate is effectively improved.

Drawings

Fig. 1 is a block diagram of an embodiment of the present invention, which provides an output high-definition audio system based on MQA full decoding.

Fig. 2 is a first electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 3 is an electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 4 is a third electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 5 is a fourth electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 6 is an electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 7 is a sixth electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 8 is a seventh electrical schematic diagram of a microprocessor according to an embodiment of the present invention.

Fig. 9 is an electrical schematic diagram of a power supply conversion module according to an embodiment of the present invention.

Fig. 10 is an electrical schematic diagram of a power supply conversion module according to an embodiment of the present invention.

Fig. 11 is an electrical schematic diagram of an audio clock unit according to an embodiment of the present invention.

Fig. 12 is a first electrical schematic diagram of an analog electronic module according to an embodiment of the present invention.

Fig. 13 is an electrical schematic diagram of an analog electronic module according to an embodiment of the present invention.

Fig. 14 is an electrical schematic diagram of a patching module according to an embodiment of the invention.

Fig. 15 is an electrical schematic diagram of a memory module according to an embodiment of the present invention.

Fig. 16 is an electrical schematic diagram of a power amplifier/operational amplifier module according to an embodiment of the present invention.

Detailed Description

As shown in fig. 1-15, the utility model provides an output high definition audio system based on MQA decodes entirely, output high definition audio system includes audio processing module, analog electronic module, power amplifier/fortune and puts module, storage module, power supply conversion module and switching module based on MQA decodes entirely, switching module's output is connected audio processing module's input, audio processing module's output is connected analog electronic module's input, analog electronic module's output is connected the input of power amplifier/fortune is put the module, storage module's output is connected audio processing module's input, power supply conversion module's output is connected audio processing module's input.

The audio processing module comprises a microprocessor, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a resistor R20, a light emitting diode LED 20, a light emitting diode 20, a clock LED 20, a clock output end of the audio processing module, a clock LED 20, a clock output end of the audio processing module, and a clock unit of the audio processing module, the microprocessor comprises a chip U2A, a chip U2B, a chip U2C, a chip U2D and a chip U2E, wherein the 31 st pin of the chip U2A is connected with one end of the resistor R23, the 57 th pin of the chip U2 23 is connected with one end of the resistor R23, the 58 th pin of the chip U2 23 is connected with one end of the resistor R23, the 3 rd pin of the chip U2 23 is connected with one end of the resistor R23, the 4 th pin of the chip U2 23 is connected with one end of the resistor R23, the 5 th pin of the chip U2 23 is connected with one end of the resistor R23, the 7 th pin of the chip U2 23 is connected with one end of the resistor R23, the 112 th pin of the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the 72 th pin of the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the anode of the chip U2 23, the chip U2 23 is connected with the anode of the LED 23 through the resistor R23, the anode of the chip 23, the chip U2 23, the chip U72 is connected with the anode of the chip U72 through the anode of the resistor R23, the chip 23, the 84 th pin of the chip U2B is connected to the anode of the LED6 through the resistor R35, the 75 th pin of the chip U2B is connected to the anode of the LED7 through the resistor R36, the 76 th pin of the chip U2B is connected to the anode of the LED8 through the resistor R37, the 77 th pin of the chip U2B is connected to the anode of the LED10 through the resistor R39, the 44 th, 105 th, 6 th, 14 th, 19 th, 29 th, 42 th, 52 th, 67 th, 78 th, 83 th, 92 th, 110 th and 111 th pins of the chip U2C are connected to one end of the capacitor C17, one end of the capacitor C18, one end of the capacitor C19, one end of the capacitor C20, one end of the capacitor C21, one end of the capacitor C22 and one end of the capacitor C23, the pin 103 th pin of the chip U2C is connected to one end of the capacitor C30 and one end of the resistor R7377, the other end of the chip U2, the resistors U24, 36, 3687458, the resistors R73, the resistors R72, the other ends of the resistors 20, 9, the resistors 53, the pins 11, the resistors 53, the pins 11, the pins 14, the resistors 72, the pins 11, the resistors 72, the pins 11, the pins 23, the resistors 72, the pins 11, the pins 14, the pins of the resistors R49, the resistors R23, the pins of the resistors R23, the pins of the resistors R23, the resistors R, One end of a capacitor C11, one end of a capacitor C12, one end of a capacitor C13, one end of a capacitor C14, one end of a capacitor C15, one end of a capacitor C16, one end of a capacitor C24, one end of a capacitor C25, one end of a capacitor C26, one end of a capacitor C27, one end of a capacitor C28 and one end of a capacitor C29, wherein the 124 th pin of the chip U2D is connected with one end of the resistor R13, the 45 th pin of the chip U2E is connected with one end of the resistor R1, and the 48 th pin of the chip U2E is connected with one end of the resistor R2.

The audio clock unit comprises a crystal oscillator Y1, a capacitor C31, a capacitor C32, a crystal oscillator Y2, a binding post P2, a chip U5, a capacitor C33, a resistor R10, a resistor R11 and a resistor R12, wherein the 4 th pin of the crystal oscillator Y1 is grounded through the capacitor C31, the 3 rd pin of the crystal oscillator Y1 is respectively connected with one end of the capacitor C34, the 3 rd pin of the crystal oscillator Y2 and the 1 st pin of the binding post P2, the 4 th pin of the crystal oscillator Y2 is grounded through the capacitor C2, the 2 nd and 4 th pins of the binding post P2 are respectively connected with the 1 st, 3 rd and 6 th pins of the chip U2, the 8 th pin of the chip U2 is grounded through the capacitor C2, the 7 th pin of the chip U2 is connected with one end of the resistor R2, the 5 th pin of the chip U2 is connected with one end of the resistor R2.

The storage module comprises a chip U6, a resistor R16, a resistor R14, a resistor R15 and a capacitor C36, wherein the 3 rd pin of the chip U6 is connected with one end of the resistor R15, the 1 st pin of the chip U6 is connected with one end of the resistor R14, the 7 th pin of the chip U6 is used for knowing one end of the resistor R16, and the 8 th pin of the chip U6 is connected with one end of the capacitor C36.

The analog electronic module comprises a crystal oscillator Y3, a capacitor C35, a chip U7 and a capacitor C37, wherein

pins

The patching module comprises a connecting terminal P3, wherein the 9 th pin of the connecting terminal P3 is connected with the 1 st pin of the chip U7.

The power amplifier/operational amplifier module comprises a chip U8 and a binding post P7-level capacitor C38, wherein the 5 th pin and the 6 th pin of the chip U8 are grounded through the capacitor C38 respectively, and the 4 th pin of the chip U8 is connected with the 1 st pin and the 3 rd pin of the binding post P7 respectively.

The power supply conversion module comprises a chip U1, a chip U3, a wire holder P1, a capacitor C2, a safety FB1, a capacitor C1, a capacitor C3, a capacitor C4, a light emitting diode LED1, a resistor R6, a chip U4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, an inductor L8 and an inductor L8, wherein the 3 rd pin of the chip U8 is respectively connected with the 3 rd pin of the chip U8 and the 46 th pin of the chip U2 8, the 5 th pin of the chip U8 is respectively connected with the 2 nd pin of the chip U8 and the 47 th pin of the chip U2 8, the 1 st pin of the chip U8 is connected with the 1 st pin of the wire holder P8, the first pin of the wire holder P8 is respectively connected with the positive terminal of the capacitor C8, and the other terminal of the capacitor C8, and the resistor C8, the positive terminal of the resistor C8, the other terminal of the resistor C8, and the other terminal of the resistor C8 are respectively connected with the positive terminal of the resistor C8, The first pin 4 of the chip U7 is connected to one end of the resistor R3, the second pin of the resistor R3 is connected to one end of the diode LED1, one end of the capacitor C8, one end of the resistor R4 and one end of the inductor L1, the third pin 3 of the chip U4 is connected to the other end of the inductor L1, the first pin 1 of the chip U4 is connected to the other end of the resistor R4 and one end of the resistor R7, the third pin 8 of the chip U4 is connected to one end of the resistor R5 and one end of the resistor R5, the fourth pin 6 of the chip U5 is connected to one end of the inductor L5, and the other end of the inductor L5 is connected to the other end of the resistor R5, one end of the capacitor C5 and one end of the capacitor C5.

In this application, the chip of the microprocessor is divided into a plurality of parts for convenience of drawing an electrical schematic diagram, wherein the chips are respectively a chip U2A, a chip U2B, a chip U2C, a chip U2D and a chip U2E, and the structure of the chip is represented by a division method, so that the chip can be easily understood. The model of the chip is XU216-512-TQ128 model, the model of TPD2E001DRLR is adopted by the chip U1, the model of MP2122 is adopted by the chip U4, the model of NC7NZ34K8X is adopted by the chip U5, the model of MX25L4006 is adopted by the chip U6, the model of NCP303LSN09 is adopted by the chip U7, and the model of NC7SZN75 is adopted by the chip U8.

The audio in the computer or the telephone is connected to the system through the switching module, the sound enters the system and is subjected to audio analysis processing through the audio processing module, then the audio signal is converted in the analog electronic module and is output after power amplification/amplification, the amplified signal can be attenuated and reduced, the amplified signal is more stable, the audio processing module can call data parameters in the storage module during working and is used for analyzing the received data information, the power supply conversion module is used for supplying power to the system, and the input voltage is converted into direct current voltages of 1V, 3.3V, 5V and the like according to the requirement of the system. By utilizing the high resolution and high sampling support of the USB, the structure is simpler, the use is more convenient, and the cost is low. The full decoding is carried out through the single-chip hard MQA, so that the analysis is simpler, the utilization rate is high, and the analysis rate is effectively improved.

The device uses USB to connect with host operation system end, after effectively enumerating all information of USB device and MQA audio frequency at host operation system end through USB UAC2.0 protocol, according to MQA coding and decoding requirement, the main control program completes the analysis of USB UAC protocol and MQA algorithm, the main control program completes the audio frequency transmitted by USB to further transmit real-time audio frequency stream to MQA program module for analysis. The main control program realizes the lossless 8-time expansion of the restored MQA audio file, and simultaneously realizes the light weight transmission, storage and high definition playing of the audio file. Real-time audio flow after MQA audio decoding is input to a high-end DAC at the rear level through a master control I2S interface, the high-end DAC realizes 768KHz PCM Line-out analog output, after analog audio output, an operational amplifier/power amplifier is added at the rear level to amplify signals generally, and sound of acoustic units such as a loudspeaker/an earphone is pushed to be output finally. Besides realizing high-definition analysis of MQA audio output, the master control chip also realizes the state indication of the MQA audio playing file and the proportion indication of the MQA file folding and unfolding.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A full decoding output high definition audio system based on MQA, its characterized in that: the MQA-based full-decoding output high-definition audio system comprises an audio processing module, an analog electronic module, a power amplifier/operational amplifier module, a storage module, a power supply conversion module and a switching module, wherein the output end of the switching module is connected with the input end of the audio processing module, the output end of the audio processing module is connected with the input end of the analog electronic module, the output end of the analog electronic module is connected with the input end of the power amplifier/operational amplifier module, the output end of the storage module is connected with the input end of the audio processing module, and the output end of the power supply conversion module is connected with the input end of the audio processing module.

2. The MQA full decoding output high definition audio system according to claim 1, wherein the audio processing module comprises a microprocessor, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor R22, a resistor R22, a light emitting diode LED 22, a light emitting diode emitting light emitting, A resistor R2 and an audio clock unit, an output terminal of the audio clock unit is connected to an input terminal of the microprocessor, the microprocessor includes a chip U2A, a chip U2B, a chip U2C, a chip U2D and a chip U2E, a 31 th pin of the chip U2A is connected to one end of the resistor R23, a 57 th pin of the chip U2A is connected to one end of the resistor R24, a 58 th pin of the chip U2A is connected to one end of the resistor R25, a 3 rd pin of the chip U2A is connected to one end of the resistor R A, a 4 th pin of the chip U2A is connected to one end of the resistor R A, a 5 th pin of the chip U2A is connected to one end of the resistor R A, a 7 th pin of the chip U2A is connected to one end of the resistor R A, a second pin 112 of the chip U2A is connected to an anode of the LED A through the resistor R A, a first pin of the chip U2A is connected to the anode of the LED A through the resistor R A, and the anode of the chip U2A is connected to the anode A through the anode of the resistor R A, the 82 th pin of the chip U2B is connected to the anode of the LED5 through the resistor R34, the 84 th pin of the chip U2B is connected to the anode of the LED6 through the resistor R35, the 75 th pin of the chip U2B is connected to the anode of the LED7 through the resistor R36, the 76 th pin of the chip U2B is connected to the anode of the LED8 through the resistor R37, the 77 th pin of the chip U2B is connected to the anode of the LED10 through the resistor R39, the 44 th, 105 th, 6 th, 14 th, 19 th, 29 th, 42 th, 52 th, 67 th, 78 th, 83 th, 92 th, 110 th and 111 th pins of the chip U2C are connected to one end of the capacitor C17, one end of the capacitor C18, one end of the capacitor C19, one end of the first pin 103 of the chip U2 19, the resistor R36, the first pin of the capacitor C3611, the capacitor C19, the resistor R3611, the first pin of the chip 3611, the capacitor C3611, the first pin of the chip 3611, the capacitor C3616, the first pin of the chip 3611, the capacitor C3611, the chip 3611, the capacitor C3611, the first pin, 56. Pins 60, 73, 80, 81, 87, 101, 102, 120, 126 and 49 are respectively connected to the other end of the resistor R9, one end of a capacitor C11, one end of a capacitor C12, one end of a capacitor C13, one end of a capacitor C14, one end of a capacitor C15, one end of a capacitor C16, one end of a capacitor C24, one end of a capacitor C25, one end of a capacitor C26, one end of a capacitor C27, one end of a capacitor C28 and one end of a capacitor C29, a 124 th pin of the chip U2D is connected to one end of the resistor R13, a 45 th pin of the chip U2E is connected to one end of the resistor R1, and a 48 th pin of the chip U2E is connected to one end of the resistor R2.

3. The MQA full decoding output high definition audio system based on claim 2, the audio clock unit comprises a crystal oscillator Y1, a capacitor C31, a capacitor C32, a crystal oscillator Y2, a post P2, a chip U5, a capacitor C33, a resistor R10, a resistor R11 and a resistor R12, the 4 th pin of the crystal oscillator Y1 is grounded through the capacitor C31, the 3 rd pin of the crystal oscillator Y1 is respectively connected with one end of the capacitor C34, the 3 rd pin of the crystal oscillator Y2 and the 1 st pin of the binding post P2, the 4 th pin of the crystal oscillator Y2 is grounded through the capacitor C32, the 2 nd and 4 th pins of the binding post P2 are respectively connected with the 1 st, 3 rd and 6 th pins of the chip U5, the pin 8 of the chip U5 is grounded through the capacitor C33, the pin 7 of the chip U5 is connected to one end of the resistor R10, the 5 th pin of the chip U5 is connected to one end of the resistor R11, and the 2 nd pin of the chip U5 is connected to one end of the resistor R12.

4. The MQA full decoding output high definition audio system according to claim 3, wherein the memory module comprises a chip U6, a resistor R16, a resistor R14, a resistor R15 and a capacitor C36, wherein the 3 rd pin of the chip U6 is connected to one end of the resistor R15, the 1 st pin of the chip U6 is connected to one end of the resistor R14, the 7 th pin of the chip U6 is connected to one end of the resistor R16, and the 8 th pin of the chip U6 is connected to one end of the capacitor C36.

5. The MQA full decoding output high definition audio system according to claim 4, wherein the analog electronic module comprises a crystal oscillator Y3, a capacitor C35, a chip U7 and a capacitor C37, wherein pins 1 and 4 of the crystal oscillator Y3 are respectively connected to a power supply 3.3V, pin 3 of the crystal oscillator Y3 is connected to pin 125 of the chip U2, pins 124 and 123 of the chip U2D are respectively connected to pin 1 of the chip U7, and pin 5 of the chip U7 is grounded through the capacitor C37.

6. The MQA full decoding output high definition audio system according to claim 5, wherein the switching module comprises a connection terminal P3, and the 9 th pin of the connection terminal P3 is connected with the 1 st pin of the chip U7.

7. The MQA full decoding output high definition audio system of claim 6, wherein the power amplifier/operational amplifier module comprises a chip U8 and a post P7-class capacitor C38, pins 5 and 6 of the chip U8 are grounded through the capacitor C38, and pin 4 of the chip U8 is connected to pins 1 and 3 of the post P7.

8. The MQA full decoding output high definition audio system according to claim 7, wherein the power conversion module comprises a chip U, a wire holder P, a capacitor C, a safety FB, a capacitor C, a light emitting diode LED, a resistor R, a chip U, a capacitor C, a resistor R, an inductor L and an inductor L, wherein the 3 rd pin of the chip U is respectively connected with the 3 rd pin of the chip U and the 46 th pin of the chip U2, the 5 th pin of the chip U is respectively connected with the 2 nd pin of the chip U and the 47 th pin of the chip U2, the 1 st pin of the chip U is connected with the 1 st pin of the wire holder P, the 2 nd pin of the wire holder P is respectively connected with one end of the capacitor C and one end of the safety FB, the other end of the fuse FB1 is connected to one end of the resistor R2, the anode of the capacitor C1, one end of the capacitor C3, one end of the capacitor C4, one end of the capacitor C5, one end of the capacitor C6, and the 2 nd and 7 th pins of the chip U4, the 4 th pin of the chip U7 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to the anode of the LED1, one end of the capacitor C7, one end of the capacitor C8, one end of the resistor R4, and one end of the inductor L1, the 3 rd pin of the chip U1 is connected to the other end of the inductor L1, the 1 st pin of the chip U1 is connected to the other end of the resistor R1, the 8 th pin of the chip U1 is connected to one end of the resistor R1, the 6 th pin of the chip U1 is connected to one end of the inductor L1, and the other end of the resistor L1 is connected to the other end of the resistor L1, One end of the capacitor C9, one end of the capacitor C10, and one end of the capacitor C11.