CN2821598Y

CN2821598Y - Wave form generator circuit

Info

Publication number: CN2821598Y
Application number: CNU2004200858476U
Authority: CN
Inventors: 李利品; 党瑞荣; 宋汐瑾
Original assignee: Xian Shiyou University
Current assignee: Xian Shiyou University
Priority date: 2004-08-20
Filing date: 2004-08-20
Publication date: 2006-09-27
Anticipated expiration: 2014-08-20

Abstract

The utility model relates to a waveform generator used for an induction logging instrument, which comprises an oscillator, a counter, a read only memory, a digital to analog converter, a dial switch and a driving and amplifying circuit. The utility model adopts the method that a sine wave of a 20KHz stabilized frequency is generated by the oscillator and the counter, and the data of a plurality of groups of waveform generators which have different initial phases are previously written in the read only memory; the initial phase of the waveform data can be adjusted through the storing sequence of the data so as to achieve the purpose of adjustable phases, thereby, the utility model realizes phase compensation which is carried out on a phase shift which is caused by the transmission delay of the circuit and the discrete components of the amplifying circuit.

Description

A kind of waveform generator circuit

Technical field

The utility model relates to a kind of waveform generator circuit of induction instrument.

Background technology

The waveform generator that needs a kind of 20KHz of generation sine wave in the induction instrument is in order to launch the inductolog signal to the stratum.When handling to received signal,, be called garbage signal owing to can produce directly coupling between transmitting coil and the receiving coil; And what really need is the induced signal that transmits and produce through the formation currents loop, is called useful signal.To transmit is benchmark, by phase sensitive detection useful signal and garbage signal is distinguished.At present the waveform generator that uses in the induction instrument be by the RC oscillatory circuit behind frequency division, by discrete elements such as inductance, electric capacity the square wave of 20KHz is adjusted to sine wave signal again, because discrete elements such as inductance, electric capacity are relatively more responsive to temperature, thereby the frequency of the sine wave signal that produces in this way is stable inadequately and phase place is unadjustable.

Summary of the invention

The purpose of this utility model is to provide the induction instrument waveform generator that a kind of compared with prior art temperature drift is little and phase place is adjustable circuit.

Realize the technical scheme of the utility model purpose:

A kind of waveform generator circuit that is used for induction instrument, comprise oscillator, counter, ROM (read-only memory), digital to analog converter, DIP switch, deposit in the described ROM (read-only memory) in order to produce the different data of many groups phase place of waveform, it is characterized in that to select to have by the DIP switch one group of data of out of phase.

Least-significant byte Q1～Q8 of counter U2 links to each other with address wire A0～A7 of ROM (read-only memory) U3, U4 respectively; The output of 5 DIP switch S 2 links to each other with address wire A8～A12 of two ROM (read-only memory) U3, U4 respectively, and no address wire A13～A16 links to each other with ground; Since only use that two-way 14 figure place weighted-voltage D/A converter U5 are a road, thereby the input end on another road DB0-P2～DB13-P2 ground connection; DQ0～DQ7 of ROM (read-only memory) U3, DQ0～DQ5 of U4 link to each other with DB0-P1～DB7-P1, the DB8-P1～DB13-P1 of digital to analog converter U5 respectively.

Each of 5 DIP switch S 2 all can toggle it to the position of " 1 " or " 0 ", has 32 kinds of combinations, and the delay of the sinusoidal wave data of 32 kinds of outs of phase in order to compensating circuit itself promptly can be arranged.The sinusoidal wave data of one-period leaves in 256 bytes of ROM (read-only memory) U3, U4 of address wire A0～A7 decision, and the phase differential between adjacent two bytes is 1.40625 °, and promptly the phase differential of each group sinusoidal wave data is up to 1.40625 °.

The square-wave signal that integrated oscillator U1 produces enters counter U2 and carries out frequency division, signal behind the frequency division is as the address gating signal of two ROM (read-only memory) U3, U4, thereby the sinusoidal wave data of depositing in the ROM (read-only memory) is outputed on the data bus, and enter digital to analog converter U5 and be converted to simulating signal, this simulating signal offers well logger after operational amplifier U6 amplifies and drives.

Description of drawings

Fig. 1 is a circuit block diagram of the present utility model.

Fig. 2 is a Waveform generating circuit schematic diagram of the present utility model.

Fig. 3 is driving of the present utility model and amplifying circuit schematic diagram.

Embodiment

Circuit block diagram of the present utility model as shown in Figure 1.The oscillator signal that oscillator produces, at first send into rolling counters forward, the output signal of counter is as the address gating signal of ROM (read-only memory) 1 and ROM (read-only memory) 2, thereby the data that will be stored in two ROM (read-only memory) inside in advance output to the input end of digital to analog converter, and be simulating signal by digital to analog converter with digital signal transition, this simulating signal offers well logger again and uses after amplifying circuit amplifies and drives.

Producing sinusoidal wave data is to write in advance in ROM (read-only memory) 1 and the ROM (read-only memory) 2, wherein ROM (read-only memory) 1 is deposited sinusoidal wave least-significant byte data, ROM (read-only memory) 2 is deposited sinusoidal wave high 6 bit data, the word length that is sinusoidal wave data is 14, and it also is 14 that the word length of selected digital to analog converter requires.

The effect of DIP switch is the initial phase that is used to regulate the 20KHz sine wave that is produced, can select in the ROM (read-only memory) one group of sinusoidal wave data of different initial phases to export by the DIP switch, so that according to because phase compensation is carried out in the phase shift that discrete component causes in transmission delay in the circuit and the amplifying circuit.

Physical circuit schematic diagram of the present utility model such as Fig. 2, shown in Figure 3.U1 is that frequency is the general integrated oscillator of 5.12MHz among the figure, and U2 is 12 binary counter HCC4040BF, and U3 and U4 are ROM (read-only memory) AM29F010, and U5 is digital to analog converter AD9767, and U6 is operational amplifier LF347, and S2 is the DIP switch.

The square wave of the 5.12MHz that U1 produces is as the clock signal of U2, and least-significant byte Q1～Q8 of U2 links to each other with address wire A0～A7 of U3, U4 respectively, and this has just realized 256 frequency divisions to the 5.12MHz frequency signal, and the signal frequency behind the frequency division is 20KHz; Per 256 bytes among U3, the U4 that is determined by A0～A7 are just in time deposited the data of a sine wave period in other words.Because U2 is output frequency division signal on Q1～Q8 pin again and again, thereby 256 data that also just will be stored among U3, the U4 again and again output among the U5.

The sinusoidal wave data word length of being exported to U5 by U3, U4 is 14, U3 storage least-significant byte data wherein, and U4 stores high 6 bit data, thereby DQ0～DQ7 of U3 links to each other with DB0-P1～DB7-P1 of U5, and DQ0～DQ5 of U4 links to each other with DB8-P1～DB13-P1 of U5.

The effect of DIP switch S 2 be in the circuit since the phase shift that transmission delay and amplifying circuit cause compensate.The output of 5 DIP switch S 2 links to each other with address wire A8～A12 of U3, U4 respectively, and no address wire A13～A16 links to each other with ground.Each of S2 all can toggle it to the position of " 1 " or " 0 ", has 32 kinds of combinations, and the delay of the sinusoidal wave data of 32 kinds of outs of phase in order to compensating circuit itself promptly can be arranged.The sinusoidal wave data of one-period leaves in 256 bytes of U3, U4 of address wire A0～A7 decision, and the phase differential between adjacent two bytes is 1.40625 °, and promptly the phase differential of each group sinusoidal wave data is up to 1.40625 °.

U5 is 14 D/A of a kind of two-way, owing to only use one road D/A, so in order to suppress noise, with input end DB0-P2～DB13-P2 ground connection of another road D/A of U5.The work clock CLK1/IQCLK of U5 and write signal WRT1/IQWRT are provided by the output Q1 of U2, the differential signal that the pin IOUTA1 of U5 and IOUTB1 output are represented with current forms, amplify and be converted to the single-ended signal of representing with voltage through U6-A, further drive by U6-C again, to improve load-carrying ability.

The utility model compared with prior art, can eliminate the frequency instability that waveform generator brought that mimic channel constitutes in the existing logging instrumentation, when temperature changes, because discrete elements such as circuit oscillation frequency of the present utility model and resistance, electric capacity are irrelevant, thereby can realize high frequency stability.

Claims

1, a kind of waveform generator circuit, comprise oscillator U1, counter U2, ROM (read-only memory) U3 and U4, digital to analog converter U5, DIP switch S 2, it is characterized in that described ROM (read-only memory) U3 is connected with counter U2 with U4 one end, the other end is connected with digital to analog converter U5, ROM (read-only memory) U3 also is connected with DIP switch S 2 with U4, and can select to have one group of data of out of phase by DIP switch S 2.

2, a kind of waveform generator circuit as claimed in claim 1 is characterized in that least-significant byte Q1～Q8 of counter U2 links to each other with address wire A0～A7 of ROM (read-only memory) U3, U4 respectively; The output of 5 DIP switch S 2 links to each other with address wire A8～A12 of two ROM (read-only memory) U3, U4 respectively, and no address wire A13～A16 links to each other with ground; Since only use that two-way 14 figure place weighted-voltage D/A converter U5 are a road, thereby the input end on another road DB0-P2～DB13-P2 ground connection; DQ0～DQ7 of ROM (read-only memory) U3, DQ0～DQ5 of U4 link to each other with DB0-P1～DB7-P1, the DB8-P1～DB13-P1 of digital to analog converter U5 respectively.

3, a kind of waveform generator circuit as claimed in claim 1 is characterized in that each switch of S2 all can toggle it to the position of " 1 " or " 0 ", has 32 kinds of combinations, and the delay of the sinusoidal wave data of 32 kinds of outs of phase in order to compensating circuit itself promptly can be arranged.