CN109445753A - A kind of data acquisition and active synchronization group frame system based on interaction caching technology - Google Patents
A kind of data acquisition and active synchronization group frame system based on interaction caching technology Download PDFInfo
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Abstract
A kind of data acquisition and active synchronization group frame system based on interaction caching technology, is related to field of data communication；Synthesizer is acquired including n sensor, collector and data；N is the positive integer greater than 0；Wherein, collector includes power supply module, the first data buffer zone and the second data buffer zone；Present invention employs interactive caching technologies of rattling, solve heterologous clock acquisition data and send data rate it is inconsistent caused by data buffer area pointer offset, it avoids the occurrence of data cover or repeats to send, realize the pipeline of data flow seamless buffering and real time access；The time error accumulation of heterologous clock is actively eliminated by data synchronizing signal, it is synchronous with the address pointer of memory block to currently transmitted data field within each caching period, avoid simultaneous asynchronous data transmissions bring buffer area pointer offset；It avoids the occurrence of data cover or repeats to send, realize the pipeline of data flow seamless buffering and real time access.
Description
Technical field
The present invention relates to a kind of field of data communication, especially a kind of data acquisition and active based on interaction caching technology
Synchronization group frame system.
Background technique
The aircraft such as spacecraft, carrier rocket development and take a flight test, data acquisition and Transmission system are winged for obtaining
The working status parameter and environmental data of each system inside row device, for evaluate the performance of aircraft and carry out accident analysis provide according to
According to.The superiority and inferiority of data acquisition and Transmission system performance directly affects the development process and expense of aircraft, influences aircraft performance
Improve.
It acquires and is sent in framework in distributed data, collector acquires data and data acquisition synthesizer sends data
Using respectively different clocks, the accumulation of error caused by heterologous clock not will lead to data acquisition in a short time and send wrong
Accidentally, but in the acquisition of prolonged data and transmission process, the accumulation of error caused by heterologous clock will cause data buffer area and refer to
Needle biasing is capped or repeats to send so as to cause collector output data；Distance between collector and data acquisition synthesizer
The too long data acquisition synthesizer that also results in cannot be sampled in the best time of collector output data, and symbol biasing improves
Data transmission error rate.
Summary of the invention
It is an object of the invention to overcome the above-mentioned deficiency of the prior art, a kind of data based on interaction caching technology are provided
Acquisition and active synchronization group frame system solve the acquisition data of heterologous clock and send the buffer area pointer offset of data, keep away
Exempt from data cover occur or repeat to send, realizes the pipeline of data flow seamless buffering and real time access.
Above-mentioned purpose of the invention is achieved by following technical solution:
A kind of data acquisition and active synchronization group frame system based on interaction caching technology of rattling, including n sensor, adopt
Storage and data acquire synthesizer；N is the positive integer greater than 0；Wherein, collector includes power supply module, the first data buffer zone
With the second data buffer zone；
Sensor: the power supply of power supply module is received；The physical parameter for the measurand that measurement obtains is converted into simulation electricity
Signal is exported to the first data buffer zone and the second data buffer zone；
Power supply module: it powers to n sensor；
First data buffer zone: receiving the data synchronic command that data acquisition synthesizer transmits, the first data buffer zone
Address zero setting；I-th of period, the n analog electrical signal that n sensor transmits is received；To each analog electrical signal successively into
Row filtering, amplification, A/D conversion process, generate n digital quantity signal；Timing is carried out to n digital quantity signal according to predetermined logic
Control, the digital quantity signal after obtaining n sequence；Digital quantity signal after n sequence is deposited according to preparatory chronological order
Storage；The reading clock that data acquisition synthesizer transmits is received, the digital quantity signal after n sequence of storage is sent to data and is adopted
Collect synthesizer；Access clock is generated simultaneously；Access clock is sent to data acquisition synthesizer；I is the odd number more than or equal to 1；
Second data buffer zone: receiving the data synchronic command that data acquisition synthesizer transmits, the second data buffer zone
Address zero setting；In the i+1 period, the n analog electrical signal that n sensor transmits is received；Successively to each analog electrical signal
It is filtered, amplifies, A/D conversion process, generating n digital quantity signal；When being carried out according to predetermined logic to n digital quantity signal
Sequence control, the digital quantity signal after obtaining n sequence；Digital quantity signal after n sequence is carried out according to preparatory chronological order
Storage；The reading clock that data acquisition synthesizer transmits is received, the digital quantity signal after n sequence of storage is sent to data
Acquire synthesizer；Access clock is generated simultaneously；Access clock is sent to data acquisition synthesizer；I is the surprise more than or equal to 1
Number；
Data acquire synthesizer: issuing data synchronic command to the first data buffer zone and the second data buffer zone；It sends
Clock is read to the first data buffer zone and the second data buffer zone；The first data buffer zone and the second data buffer zone is received to pass
Digital quantity signal after the n sequence come；Receive the access clock that the first data buffer zone and the second data buffer zone are transmitted；It will
Access clock is compared with reading clock, generates the digital quantity signal after latching；Latched digital amount signal is converted to serially
Signal, and serial signal is sent to external modulation transmitting equipment.
In a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling, the n
A sensor includes temperature sensor, four seed type of shock transducer, vibrating sensor and pressure sensor；Wherein, temperature passes
Sensor measurement obtains the temperature of testee；Shock transducer measurement obtains the impact acceleration of testee；Vibrating sensor
Measurement obtains the vibration acceleration of testee；Pressure sensor measurement obtains the pressure of testee.
In a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling, the sensing
The voltage for the analog electrical signal that device generates is greater than 0V, and is less than or equal to 5V.
It is described predetermined in a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling
Logic is successively according to temperature digital amount signal, impact acceleration digital quantity signal, vibration acceleration digital quantity signal and pressure
Digital quantity signal sequence is ranked up.
It is described preparatory in a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling
Chronological order be successively according to the temperature digital amount signal after sequence, the impact acceleration digital quantity signal after sequence, sequence after
Vibration acceleration digital quantity signal and sequence after pressure on the number amount signal sequence.
In a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling, the access
The frequency of clock is identical as the reading frequency of clock.
In a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling, described first
Data buffer zone and the first data buffer zone send data address zero setting, realize the first data buffer zone and the second data buffering
Area carries out receiving or sending data in the same address of synchronization.
In a kind of above-mentioned data acquisition and active synchronization group frame system based on interaction caching technology of rattling, the data
The method that acquisition synthesizer is compared reading clock and clock of fetching are as follows: when reading clock is consistent with the access phase of clock
When, the digital quantity signal after sequence is latched to read the failing edge of clock, generates the digital quantity signal after latching；When reading clock
When inconsistent with the phase of access clock, the digital quantity signal after sequence is latched with the failing edge for clock pulses of fetching.
The invention has the following advantages over the prior art:
(1) present invention employs interactive caching technology of rattling, heterologous clock acquisition data is solved and send data rate
Data buffer area pointer offset caused by inconsistent avoids the occurrence of data cover or repeats to send, it is seamless to realize data flow
The pipeline of buffering and real time access；
(2) present invention actively eliminates the time error accumulation of heterologous clock by data synchronizing signal, in each caching week
It is synchronous with the address pointer of memory block to currently transmitted data field in phase, avoid simultaneous asynchronous data transmissions bring buffer area pointer
Biasing；
(3) present invention, which devises, eliminates clock phase flip module to carry out data latch, solve data collection system away from
From the problem of the overturning of reading clock phase, avoiding the symbol biasing of output transmission, reduce data caused by too long
Transmission error rates；
(4) default insertion word is added in the present invention in data frame format, is detected by the default insertion word to designated position,
Data integrity judgment criterion is enhanced, avoids that data are more insufficient and no abnormalities were found, is improved complete to data
The accuracy rate of whole property judgement.
Detailed description of the invention
Fig. 1 is data of the present invention acquisition and active synchronization framing system schematic.
Specific embodiment
The present invention is described in further detail in the following with reference to the drawings and specific embodiments:
The present invention is actively eliminated the time error accumulation of heterologous clock, is devised and taken using interactive caching technology of rattling
Number clocks carry out data latch, solve heterologous clock acquisition data and send data rate it is inconsistent caused by data buffer storage
Area's pointer offset realizes the pipeline of data flow seamless buffering and real time access, reduces data transmission error rate.
It is as shown in Figure 1 data acquisition and active synchronization framing system schematic, as seen from the figure, one kind is based on table tennis interaction
The data acquisition of caching technology and active synchronization group frame system, including n sensor, collector and data acquire synthesizer；N is
Positive integer greater than 0；Wherein, collector includes power supply module, the first data buffer zone and the second data buffer zone；N sensing
Device includes temperature sensor, four seed type of shock transducer, vibrating sensor and pressure sensor；Wherein, temperature sensor is surveyed
Measure the temperature of testee；Shock transducer measurement obtains the impact acceleration of testee；Vibrating sensor measures
To the vibration acceleration of testee；Pressure sensor measurement obtains the pressure of testee.
Sensor: the power supply of power supply module is received；The physical parameter for the measurand that measurement obtains is converted into simulation electricity
Signal is exported to the first data buffer zone and the second data buffer zone；The voltage of analog electrical signal is greater than 0V, and is less than or equal to 5V.
Power supply module: it powers to n sensor.
It is configured with mutual independent first data buffer area, the second data buffer area inside collector, is cached at first
Period, by the data flow cache of input into the first data buffer area；In second caching period, selected by input data single
The switching of member by the data flow cache of input into the second data buffer area, while will previously be stored in the first data buffer area
Data are sent to subsequent module by output data selection unit and are handled；In third caching period, switch data is defeated again
Enter output data selection unit, input traffic is cached to the first data buffer area, while will previously be stored in the second data and delay
The data for depositing area, which are sent by output data selection unit to subsequent module, to be handled；Friendship is repeated according to the process later
For handover operation.
First data buffer zone: receiving the data synchronic command that data acquisition synthesizer transmits, the first data buffer zone
Address zero setting；I-th of period, the n analog electrical signal that n sensor transmits is received；To each analog electrical signal successively into
Row filtering, amplification, A/D conversion process, generate n digital quantity signal；Timing is carried out to n digital quantity signal according to predetermined logic
Control, the digital quantity signal after obtaining n sequence；Predetermined logic is successively according to temperature digital amount signal, impact acceleration number
Word amount signal, vibration acceleration digital quantity signal and pressure on the number amount signal sequence are ranked up.By the digital quantity after n sequence
Signal is stored according to preparatory chronological order；Preparatory chronological order is successively according to the temperature digital amount signal after sequence, row
The vibration acceleration digital quantity signal after impact acceleration digital quantity signal, sequence after sequence and the pressure on the number amount letter after sequence
Number sequence.The reading clock that data acquisition synthesizer transmits is received, the digital quantity signal after n sequence of storage is sent to
Data acquire synthesizer；Access clock is generated simultaneously；Access clock is sent to data acquisition synthesizer；I is more than or equal to 1
Odd number.
Second data buffer zone: receiving the data synchronic command that data acquisition synthesizer transmits, the second data buffer zone
Address zero setting；First data buffer zone and the first data buffer zone send data address zero setting, and it is slow to realize the first data
Area and the second data buffer zone is rushed to carry out receiving or sending data in the same address of synchronization.In the i+1 period, n is received
The n analog electrical signal that a sensor transmits；Each analog electrical signal is successively filtered, is amplified, A/D conversion process, it is raw
At n digital quantity signal；Timing control is carried out to n digital quantity signal according to predetermined logic, the digital quantity after obtaining n sequence
Signal；Digital quantity signal after n sequence is stored according to preparatory chronological order；Receive what data acquisition synthesizer transmitted
Clock is read, the digital quantity signal after n sequence of storage is sent to data acquisition synthesizer；Access clock is generated simultaneously；
The frequency of access clock is identical as the reading frequency of clock.Access clock is sent to data acquisition synthesizer；I be more than or equal to
1 odd number.
Collector eliminated according to the data synchronizing signal that receives data acquisition synthesizer crystal oscillator, collector crystal oscillator when
Between the accumulation of error, after the rising edge for detecting data synchronizing signal, to the ground of the first data buffer area, the second data buffer area
Location pointer is reset and is reset together, same to the address pointer of currently transmitted data field and memory block within each caching period
Step selects the memory block and transmission area of suitable first data buffer area, the second data buffer area as current acquisition data, number
It is emptied after being sent according to the data for sending buffer area；Collector exports same with the phase of data in output data
Step, the identical access clock of code rate, access clock are identical as reading clock frequency.
Collector is accumulated using the time error that data synchronic command periodically eliminates heterologous clock come active, in each caching
The address pointer of currently transmitted data field and memory block is reset and is reset in period, specific workflow is as follows:
The first step, data acquire synthesizer within each duty cycle, are sent out according to the timing of itself crystal oscillator clock to collector
Send data synchronizing signal；
Second step, collector judges whether it is first caching period, if it is first caching period, collector foundation
The data synchronizing signal received accumulates to eliminate the time error of data acquisition synthesizer crystal oscillator, collector crystal oscillator, collector
After the rising edge for detecting data synchronizing signal, together to the address pointer of the first data buffer area, the second data buffer area
It is reset and is reset, at this time memory block of first data buffer area as current acquisition data, collector not output data；
Third step, out of, each caching period after second caching period, collector is same according to the data received
Step signal accumulates to eliminate the time error of data acquisition synthesizer crystal oscillator, collector crystal oscillator, detects data synchronizing signal
After rising edge, the address pointer of the first data buffer area, the second data buffer area is reset and reset together, while is right
First data buffer area, the second data buffer area data capacity judged, if having in data buffer 1 data, second number
According to no data in buffer area, transmission area of first data buffer area as current data is selected at this time, selects the second data buffer storage
Memory block of the area as current acquisition data, the data of the first data buffer area empty after being sent；If in data buffer 1
There are data in no data, the second data buffer area, select transmission area of second data buffer area as current data at this time, selects
Memory block of first data buffer area as current acquisition data, the data of the second data buffer area empty after being sent.
Data acquire synthesizer: issuing data synchronic command to the first data buffer zone and the second data buffer zone；It sends
Clock is read to the first data buffer zone and the second data buffer zone；The first data buffer zone and the second data buffer zone is received to pass
Digital quantity signal after the n sequence come；Receive the access clock that the first data buffer zone and the second data buffer zone are transmitted；It will
Access clock is compared with reading clock, when reading clock is consistent with the access phase of clock, to read the decline of clock
Digital quantity signal after latching sequence generates the digital quantity signal after latching；When reading clock and fetch clock phase not
When consistent, the digital quantity signal after sequence is latched with the failing edge for clock pulses of fetching；Generate the digital quantity signal after latching；It will
Latched digital amount signal is converted to serial signal, and serial signal is sent to external modulation transmitting equipment.
Data acquire synthesizer and carry out timing control to collector by control bus, right after receiving access clock
The reading clock and access clock that itself crystal oscillator generates carry out phase comparison, the decline of selection reading clock or clock pulses of fetching
Along latch data, the collector output data at this moment is read by prescribed form to data framing, then converts parallel signal
It exports for serial signal to modulating and emitting equipment, eliminates clock phase flip module.
Data of the invention acquire design of Frequency Synthesizer access clock to carry out data latch, the elimination clock phase
The detailed process of flip module are as follows:
Data acquire synthesizer receive access clock after, to itself crystal oscillator generate reading clock and access clock into
Row phase compares, if reading clock is consistent with the access phase of clock, in the failing edge latch data of reading clock pulses, reads
The collector output data at this moment is taken, 8 bit datas synthesize 1 byte, first transmit the high-order, last of byte in transmission
The low level of byte is transmitted again, then continuous byte is pressed into prescribed form to data framing；If reading the phase of clock and clock of fetching
Position is inconsistent, then in the failing edge latch data of access clock pulses, reads the collector output data at this moment, 8 bits
1 byte of Data Synthesis, first transmitted in transmission byte it is high-order, finally transmit the low level of byte again, then by continuous byte
Prescribed form is pressed to data framing to data framing by prescribed form.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (8)
1. a kind of data acquisition and active synchronization group frame system based on interaction caching technology of rattling, it is characterised in that: including n
Sensor, collector and data acquire synthesizer；N is the positive integer greater than 0；Wherein, collector includes power supply module, the first number
According to buffer area and the second data buffer zone；
Sensor: the power supply of power supply module is received；The physical parameter for the measurand that measurement obtains is converted into analog electrical signal
It exports to the first data buffer zone and the second data buffer zone；
Power supply module: it powers to n sensor；
First data buffer zone: the data synchronic command that data acquisition synthesizer transmits, the address of the first data buffer zone are received
Zero setting；I-th of period, the n analog electrical signal that n sensor transmits is received；Each analog electrical signal is successively filtered
Wave, amplification, A/D conversion process generate n digital quantity signal；Timing control is carried out to n digital quantity signal according to predetermined logic
System, the digital quantity signal after obtaining n sequence；Digital quantity signal after n sequence is stored according to preparatory chronological order；
The reading clock that data acquisition synthesizer transmits is received, the digital quantity signal after n sequence of storage is sent to data acquisition
Synthesizer；Access clock is generated simultaneously；Access clock is sent to data acquisition synthesizer；I is the odd number more than or equal to 1；
Second data buffer zone: the data synchronic command that data acquisition synthesizer transmits, the address of the second data buffer zone are received
Zero setting；In the i+1 period, the n analog electrical signal that n sensor transmits is received；Each analog electrical signal is successively carried out
Filtering, amplification, A/D conversion process, generate n digital quantity signal；Timing control is carried out to n digital quantity signal according to predetermined logic
System, the digital quantity signal after obtaining n sequence；Digital quantity signal after n sequence is stored according to preparatory chronological order；
The reading clock that data acquisition synthesizer transmits is received, the digital quantity signal after n sequence of storage is sent to data acquisition
Synthesizer；Access clock is generated simultaneously；Access clock is sent to data acquisition synthesizer；I is the odd number more than or equal to 1；
Data acquire synthesizer: issuing data synchronic command to the first data buffer zone and the second data buffer zone；Send reading
Clock is to the first data buffer zone and the second data buffer zone；It receives the first data buffer zone and the second data buffer zone transmits
Digital quantity signal after n sequence；Receive the access clock that the first data buffer zone and the second data buffer zone are transmitted；It will access
Clock is compared with reading clock, generates the digital quantity signal after latching；Latched digital amount signal is converted into serial signal,
And serial signal is sent to external modulation transmitting equipment.
2. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 1
System, it is characterised in that: the n sensor includes temperature sensor, shock transducer, vibrating sensor and pressure sensor
Four seed types；Wherein, temperature sensor measurement obtains the temperature of testee；Shock transducer measurement obtains rushing for testee
Hit acceleration；Vibrating sensor measurement obtains the vibration acceleration of testee；Pressure sensor measurement obtains testee
Pressure.
3. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 2
System, it is characterised in that: the voltage for the analog electrical signal that the sensor generates is greater than 0V, and is less than or equal to 5V.
4. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 3
System, it is characterised in that: the predetermined logic is successively according to temperature digital amount signal, impact acceleration digital quantity signal, vibration
Acceleration digital quantity signal and pressure on the number amount signal sequence are ranked up.
5. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 4
System, it is characterised in that: the preparatory chronological order is successively to add according to the temperature digital amount signal after sequence, the impact after sequence
The sequence of the pressure on the number amount signal after vibration acceleration digital quantity signal and sequence after speed digital quantity signal, sequence.
6. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 5
System, it is characterised in that: the frequency of the access clock is identical as the reading frequency of clock.
7. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 6
System, it is characterised in that: first data buffer zone and the first data buffer zone send data address zero setting, realize the first number
It carries out receiving or sending data in the same address of synchronization according to buffer area and the second data buffer zone.
8. a kind of data acquisition and active synchronization framing system based on interaction caching technology of rattling according to claim 7
System, it is characterised in that: the method that the data acquisition synthesizer is compared reading clock and clock of fetching are as follows: when reading
When clock is consistent with the access phase of clock, the digital quantity signal after sequence is latched to read the failing edge of clock, is generated after latching
Digital quantity signal；When the phase for reading clock and clock of fetching is inconsistent, row is latched with the failing edge for clock pulses of fetching
Digital quantity signal after sequence.
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| CN114363381A (en) * | 2022-03-21 | 2022-04-15 | 北京凌空天行科技有限责任公司 | Rocket data acquisition and transmission system and rocket data acquisition and transmission method |
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| CN112073460A (en) * | 2020-08-03 | 2020-12-11 | 国网山东省电力公司电力科学研究院 | Data acquisition unit, data transmission method and comprehensive energy monitoring system |
| CN114363381A (en) * | 2022-03-21 | 2022-04-15 | 北京凌空天行科技有限责任公司 | Rocket data acquisition and transmission system and rocket data acquisition and transmission method |
| CN114363381B (en) * | 2022-03-21 | 2022-07-12 | 北京凌空天行科技有限责任公司 | Rocket data acquisition and transmission system and rocket data acquisition and transmission method |
| CN115952105A (en) * | 2022-12-05 | 2023-04-11 | 深圳市朗宇芯科技有限公司 | Data transmission method and device based on data cache and storage medium |
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