CN2791883Y - Package chip improvement capable of increasing rate - Google Patents
Package chip improvement capable of increasing rate Download PDFInfo
- Publication number
- CN2791883Y CN2791883Y CN 200520001334 CN200520001334U CN2791883Y CN 2791883 Y CN2791883 Y CN 2791883Y CN 200520001334 CN200520001334 CN 200520001334 CN 200520001334 U CN200520001334 U CN 200520001334U CN 2791883 Y CN2791883 Y CN 2791883Y
- Authority
- CN
- China
- Prior art keywords
- pin
- projection
- lead frame
- bare chip
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 230000001737 promoting effect Effects 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 4
- 230000000994 depressogenic effect Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract description 9
- 230000005540 biological transmission Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 230000007812 deficiency Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011469 building brick Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 208000002193 Pain Diseases 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000036407 pain Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a packaged chip improvement which is capable of increasing speed. The packaged chip improvement which is capable of increasing speed comprises a conducting wire rack composed of a plurality of leading pins fixedly arranged on a connecting point surface having a bare chip, wherein the leading pins of the conductor wire rack can be arranged at both sides of the bare chip or arranged in the shape of a matrix and the inner ends of the leading pins are provided with conducting wires which are electrically connected with the connecting points of the bare chip. The lower ends of the leading pins of the conducting wire rack are punched with convex blocks, the convex blocks are taken as outer electrical guiding surfaces in order to connect with the soldering tin of the connecting points of a circuit board, and further, the soldering tin can be used for coating the bottom surfaces and the circumferences of the convex blocks to enhance the effects of welding stability, transmission rate, etc.
Description
Technical field
The utility model is relevant a kind of packaged chip improvement of promoting speed, refers in particular to a kind of structural improvement of each pin of lead frame.
Background technology
Existing packaged chip structure, see also shown in Figure 6, be to comprise that a bare chip 10, a lead frame 20, plural metal wire 30 and an adhesive body 40 form, wherein this lead frame 20 is to become to arrange shape plural number pin 201 by metal material through punching to be constituted, and be fixedly arranged on this bare chip 10 selected faces, be connected between bare chip 10 contacts and each pin 201 the inners by this plural number metal wire 30, and an adhesive body 40 sealing metal lines 30 welding positions, promptly form the packaged chip that can be assembled in application on the circuit board 50.
On take off existing packaged chip, each pin 201 of its lead frame 20 only is the single rectangular block structure, with each pin 201 bottom surface in order to the scolding tin 60 of circuit board 50 contacts then, because of these pin 201 bottom surfaces respectively for plane merely, cause scolding tin 60 can't stablize then, because of factor affecting such as slight impact or temperature, humidity make 201 local disengagings of one, two pin, cause its afunction easily.Person in addition, use each pin 201 bottom surface directly with scolding tin 60 then, its section that connects only limits to scolding tin 60 section scopes, so the limited chip efficiency of transmission, can't be in response to the demand of two-forty and huge signal transmission at present.
Every problem and deficiency that this case designer derives in view of existing packaged chip structure are urgently thought improve innovation, and after concentrating on studies through taking great pains to attain one's goal, successfully research and develop finally and finish the packaged chip structure that can promote speed.
The utility model content
The utility model main purpose, be that a kind of packaged chip improvement of promoting speed is being provided, especially, make the deficiency of improving existing packaged chip welding stability so as to the structural improvement of each pin of lead frame, and the transmission rate when further promoting packaged chip and using.
According to above-mentioned purpose, the utility model implementation content is to comprise that a bare chip, a lead frame, complex lead and adhesive body form, wherein:
This bare chip is for the made electronic building brick of semi-conducting material, simultaneously is provided with plural contact in it; This lead frame is the metal medium that is fixedly arranged on bare chip contact face, is have plural block pin in order to be connected between bare chip and circuit board; This complex lead is the metal wire that is welded in bare chip contact and each pin of lead frame; This adhesive body is the insulator that sealing coats the wire bonds position;
A kind of packaged chip improvement of promoting speed, comprise that this face of bare chip contact sets firmly a lead frame, in between bare chip contact and lead frame, be welded with complex lead, and be provided with an adhesive body in this complex lead weld part and form, it is characterized in that: this lead frame is to adopt to be punched to plural block pin with the metal material and to be and to arrange shape and constitute, each pin lower end dashes and is provided with a projection, and with the end face of this projection as the face that connects to external electricity, around composition can reach for the stable end face that envelopes this pin projection of scolding tin whereby, and promote the packaged chip of efficiency of transmission.
This projection comprises that can be the pin upper surface down dashes and be provided with a depression position.
This projection be included in the end can implement one plating the layer.
Effective effect of the present utility model is: a kind of packaged chip improvement of promoting speed, improving the deficiency of existing packaged chip welding stability, and promote effects such as its welding stability and transmission rate.
Brief description of drawingsfig:
Fig. 1 forms the sectional schematic diagram of state for the utility model packaged chip.
Fig. 2 forms the schematic bottom view of state for the utility model packaged chip.
Fig. 3 be the utility model lead frame pin for the schematic diagram of welded condition.
Fig. 4 is assembled in the schematic diagram of circuit board for the utility model packaged chip.
Fig. 5 is the schematic perspective view of the single pin configuration of the utility model.
Fig. 6 is the sectional schematic diagram of existing packaged chip structure.
[main figure number explanation]
Plating layer 25; Complex lead 3;
Contact 501; Scolding tin 60;
Embodiment:
Now adjoint embodiment is described in detail as follows architectural feature of the present utility model and other effect, purpose:
With reference to the accompanying drawings, the utility model is done a kind of " can promote the packaged chip improvement of speed ", this packaged chip is a kind of electronic building brick that circuit board 50 is used that is assembled in, is to comprise that a bare chip 1, a lead frame 2, complex lead 3 and adhesive body 4 form, wherein:
Borrow the architectural feature and the syntagmatic of above-mentioned bare chip 1, lead frame 2, complex lead 3 and adhesive body 4, the packaged chip (consulting shown in Figure 4) that the projection 23 of promptly forming a kind of available wire frame 2 each pin 21 and circuit board 50 welding are used makes so as to this lead frame 2 and complex lead 3 as the conducting medium of bare chip 1 with circuit board 50.
Utilization the utility model can be promoted the packaged chip improvement of speed, because its lead frame 2 each pin 21 lower ends are formed with a projection 23 and welding end face 24 respectively, so can be then corresponding to the scolding tin on circuit board 50 contacts 501 60, can provide this scolding tin 60 to envelope the end face 24 of projection 23 and (as shown in Figure 3) on every side thereof, whereby, improve the deficiency that existing packaged chip can only be followed with face, reach and promote its welding stability effect, make prevent to touch, various factors such as variations in temperature comes off short circuit.Other is the person, because of having projection 23, these lead frame 2 each pin 21 lower ends of the utility model can follow with scolding tin 60, it is followed area and comprises around the end face 24 its its, thus can increase the telecommunication efficiency of transmission by this, to meet the demand of two-forty of electronic product requirement now and huge data-handling capacity.
Person in addition sees also shown in Figure 3ly, and end face 24 places of this projection 23 of the utility model also can implement one and plate layer 25, and its material can be the higher silver of electrical efficiency etc., whereby with scolding tin 60 then after, can better reduction resistance, and promote its transmission rate.
Claims (3)
1, a kind of packaged chip improvement of promoting speed, comprise that this face of bare chip contact sets firmly a lead frame, in between bare chip contact and lead frame, be welded with complex lead, and be provided with an adhesive body in this complex lead weld part and form, it is characterized in that: this lead frame is to adopt to be punched to plural block pin with the metal material and to be and to arrange shape and constitute, each pin lower end dashes and to be provided with a projection, and with the end face of this projection as to external electricity, can be for stable end face and the face that connects on every side that envelopes this pin projection of scolding tin.
According to the described packaged chip improvement of promoting speed of claim 1, it is characterized in that 2, this projection comprises that can be the pin upper surface down dashes and be provided with a depressed part.
According to the described packaged chip improvement of promoting speed of claim 1, it is characterized in that 3, this projection is included in the end and can implements one and plating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520001334 CN2791883Y (en) | 2005-01-21 | 2005-01-21 | Package chip improvement capable of increasing rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520001334 CN2791883Y (en) | 2005-01-21 | 2005-01-21 | Package chip improvement capable of increasing rate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2791883Y true CN2791883Y (en) | 2006-06-28 |
Family
ID=36807937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520001334 Expired - Fee Related CN2791883Y (en) | 2005-01-21 | 2005-01-21 | Package chip improvement capable of increasing rate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2791883Y (en) |
-
2005
- 2005-01-21 CN CN 200520001334 patent/CN2791883Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: LIANG XIWEI Free format text: FORMER OWNER: ZI ZHONGXING Effective date: 20071012 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20071012 Address after: 100044, room 3, building 6, car 311, main street, Xicheng District, Beijing Patentee after: Liang Xiwei Address before: 226500 Rugao city of Jiangsu province Hangyuan Pu 207 building 303 room Patentee before: Zi Zhongxing |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060628 |