CN2700946Y - High-speed USB communication interface arrangement for real time signal processing - Google Patents

Abstract

The utility model discloses a high-speed USB communication interface arrangement for a real time signal processing, comprising a USB 2.0 controller which is respectively connected with a serial EEPROM memory circuit, an FPGA programmable logic circuit, a USB communication interface socket, and a voltage transformation circuit through leader lines. The USB communication interface socket is connected with a supervisory computer PC machine through a USB transmission cable. The utility model provides a communication interface used to complete a fast real-time transmission with large data volume between a signal analyzer and the supervisory computer PC machine, according to the USB 2.0 protocol and the EZ-USBFX2 technology, and the real-time signal analyzer can be conveniently and fast connected with the supervisory computer PC machine in a common signal process occasion by the support of the software, under the USB2.0 protocol frame; further more, a communication of large data volume can be realized.

Description

The high speed USB communication interface device of real time signal processing

Affiliated technical field

The utility model includes line transmission system, relates in particular to a kind of high speed USB communication interface device of real time signal processing.

Background technology

In the present signal processing system of China, adopt following structure mostly: slave computer only is responsible for data acquisition and Signal Pretreatment and data is sent to the function of host computer by certain interface (serial port, parallel port etc.), signal processing tasks (as spectrum processing, digital filtering, correlation analysis etc.), application, data are preserved finishes with showing etc. all by host computer (be PC), such communication interface data transmission rate is not high, and real-time is very poor.In addition, the employed program code of instrument generally must solidify in advance to be fired in chip, then needs to fire again when instrumental analysis software need update, very inconvenient.Along with the DSP broad application, now begin to adopt the signal processing structure of international popular gradually, promptly utilize the special DSP processor to finish signal Processing, PC carries out parameter setting, demonstration, data storage etc., the high interface mode of transfer rate is adopted in the communication of slave computer and host computer, such as pci bus, USB etc., these high efficiency communication interface modes also make the renewal of instrumentation program code become convenient and swift simultaneously.

Summary of the invention

The purpose of this utility model is to provide a kind of high speed USB communication interface device of real time signal processing, is used for solving the quick communication problem of big data quantity in real time of various Signal Analysis System signal analyzers and host computer.

In order to achieve the above object, the technical solution adopted in the utility model is that it comprises: USB2.0 controller, serial ports eeprom memory circuit, FPGA Programmable Logic Device, USB communication interface socket, voltage conversion circuit; The USB2.0 controller through extension line respectively with serial ports eeprom memory circuit, the Programmable Logic Device of FPGA, the USB communication interface socket, voltage conversion circuit connects; The USB communication interface socket is connected to the host computer PC through the USB transmission cable.

1) USB2.0 controller: comprise the CY7C68013 chip of USB2.0 controller, the crystal oscillating circuit that bipod crystal oscillator Y1 and the 1st, 2 electric capacity are formed; By the 1st switch, the 1st resistance, the reseting switch circuit that the 3rd electric capacity is formed; By the 2nd resistance, the 2nd switch, the wake-up circuit that the 4th electric capacity is formed; The 1st pull-up resistor, the 1st pilot lamp and insert the 3rd resistance, the 1st signal input resistance, the 1st～10 chip decoupling capacitance;

2). serial ports eeprom memory circuit: comprise that capacity is the 24LC01 chip of 16 bytes, be connected to the CY7C68013 chip of USB2.0 controller by lead-in wire SCL and SDA, other has the 2nd, 3 pull-up resistors;

3) .FPGA Programmable Logic Device: comprise FPGA Programmable Logic Device chip XC2S50E, crystal oscillator chip CB3LV-3C-40.00, JTAG download interface element U5, and by data line FD0～FD15, address wire GDAR0～GDAR8, control line CTL0, CTL1, CTL2, CTL3 links to each other with the CY7C68013 chip, the CY7C68013 chip is by signal wire PROGRAM in addition, DIN, DONE, CCLK links to each other with the FPGA Programmable Logic Device, the 4th～7 pull-up resistor, signal inserts the 4th resistance, the 2nd pilot lamp L2, the 1st current-limiting resistance, the 5th electric capacity, the 11st～22 chip decoupling capacitance;

4) .USB communication interface socket (4): use general USB socket, link to each other with the CY7C68013 chip of USB2.0 controller by line USBD+ and USBD one;

5). voltage conversion circuit: comprise voltage transformation chip TPS767D318, the 8th pull-up resistor, the 1st, 2 protective resistances, the mu balanced circuit of forming by the 1st～3 diode, the current stabilization circuit of forming by the 6th～11 electric capacity.

The utility model provides a kind of communication interface of realizing quick real-time big data quantity between signal analyzer and the host computer PC that is used to finish in conjunction with USB2.0 agreement and EZ-USB FX2 technology.Under the USB2.0 protocol frame,, can conveniently be linked on the host computer PC at real-time signal analyzer under the common signal processing occasion, and can realize the communication of big data quantity by the support of software.

The utility model is compared with background technology, and the useful effect that has is:

1, plug and play: all have USB interface on most at present PC mainboards, can be linked into easily in the host computer so have the real-time signal analyzer of this interface, easy for installation, need not to open computing machine integrated circuit board is installed;

2, easy communication is quick: need only the corresponding driving program be installed on host computer, the real-time signal analyzer with this interface just can insert host computer and carry out communication;

3, high-speed data communications: this interface arrangement can be realized the data throughput of big data quantity under the support of USB2.0 agreement, can reach 240Mbit/s the soonest, thereby realize real time signal processing better;

4, software refreshing is efficient and convenient: using this kind communication interface can be by carrying out the software refreshing of real-time signal analyzer device from host computer download program code mode, it is efficient and convenient that more original chip internal program is fired mode, and do not need hardware to carry out the physics change;

5, applied range: be applied to the various chips such as the dsp chip of signal analysis, A/D and D/A chip etc. can be linked into host computer by this USB communication interface device then by articulating FPGA;

6, favorable expandability: because the controller of USB2.0 directly is connected with the FPGA Programmable Logic Device, has boundless extendability, and this device can be compatible at a high speed or the PC of usb bus interface at full speed, select automatically to be operated at a high speed or under the pattern at full speed;

7, simple and compact for structure: general FPGA needs the outside to add the PROM element to be used for depositing configuration file, and this device leaves configuration file in the host computer in, in real time FPGA is configured by usb bus, so do not need the PROM element.

Description of drawings

The utility model is described in further detail below in conjunction with drawings and Examples.

Fig. 1 is a structured flowchart of the present utility model;

Fig. 2 is serial ports eeprom memory circuit theory diagrams;

Fig. 3 is a USB controller circuitry schematic diagram;

Fig. 4 is a FPGA Programmable Logic Device schematic diagram;

Fig. 5 is USB communication interface socket circuit theory diagrams;

Fig. 6 is the voltage control circuit schematic diagram.

Embodiment

As shown in Figure 1, it comprises the utility model: USB2.0 controller 1, serial ports eeprom memory circuit 2, FPGA Programmable Logic Device 3, USB communication interface socket 4, voltage conversion circuit 5.USB2.0 controller 1 through extension line respectively with serial ports eeprom memory circuit 2, the Programmable Logic Device 3 of FPGA, USB communication interface socket 4, voltage conversion circuit 5 connects; USB communication interface socket 4 is connected to the host computer PC through the USB transmission cable.

As shown in Figure 3, USB2.0 controller circuitry 1: comprise USB2.0 controller CY7C68013 chip, bipod crystal oscillator and C1, the crystal oscillating circuit that C2 forms, by S1, R1, the reseting switch circuit that C3 forms, by R2, SP1, C4 forms wake-up circuit.Pull-up resistor R3.Pilot lamp L1 and access resistance R 4, signal input resistance R5, power protecting circuit capacitor C 5, C6, C7, C8, C9, C10, C11, C12, C13, C14.CY7C68013 is by read-write control line, and address wire links to each other with FPGA with the IO line of data line and part.CY7C68013 passes through I in addition ²The C bus links to each other with eeprom memory, also with being connected with the usb bus interface by the usb signal line.

As shown in Figure 2, serial ports eeprom memory circuit 2: comprise eeprom chip 24LC01 and two pull-up resistors.The CY7C68013 of USB2.0 controller passes through I ²The C bus links to each other with 24LC01.EEPROM mainly is a sequence number of depositing producer and product.

As shown in Figure 4, FPGA Programmable Logic Device 3: comprise fpga chip XC2S50E, the brilliant shake of 40M chip, JTAG download interface.The JTAG mouth is to be used for debugging, by data line FD0～FD15, and address wire GDAR0～GDAR8, control line CTL0, CTL1, CTL2, CTL3, IO mouth line PE0, PE1, PE2, RDY0, RDY1, RDY2 etc. link to each other with CY7C68013.Whether pilot lamp L2 downloads success for the program of indicating FPGA.And IO line FPG0～FPG31, signal wire FSX1, CLKX1, TINP1,2CE3 etc. are connected with the logical circuit of outside, are at present to be connected with digital signal processor DSP.The mode of operation base pin selection M0 of FPGA in addition, M1, M2 is external pull-up resistor, the configuration mode that promptly shows FPGA has adopted the configuration of driven serial ports pattern.Configurable clock generator pin CCLK links to each other with the TXD0 of the serial ports 0 of CY7C68013, and configuration data input pin DIN links to each other with the RXDOOUT of serial ports 0, configuration programming pin PROGRAM and configuration finish pin DONE respectively with the I0 pin PA3 of CY7C68013, PA1 links to each other.

As shown in Figure 5: USB communication interface socket circuit 4: by signal wire D+, D-is connected with the CY7C68013 of USB2.0 controller.

As shown in Figure 6: voltage control circuit 5: mainly comprise voltage transformation chip TPS767D318, pull-up resistor R14, protective resistance R15, R16.The 5V of input is converted to 3.3V and 1.8V, gives whole device power supply.

Below to concrete course of work explanation of the present utility model:

1, equipment inserts: the USB cable by special use links to each other the USB interface of real-time signal analyzer with USB interface of computer, computing machine can detect this connection by built-in Root Hub interrupt routine automatically, that is have equipment to insert, and the order of sending the fetch equipment sequence number to the USB peripheral hardware.

2, computing machine is for the enumeration process of USB controller: the CY7C68013 kernel of USB2.0 controller can move a very simple program, (deposit the sequence number and the ID of product from EEPROM, this part is fired in advance) in read this sequence number, and send host computer to.COMPUTER DETECTION is sent query requests automatically to there being equipment to insert, and USB device is responded this request, sends the Vendor ID and the Product ID of equipment, and computing machine loads the corresponding apparatus driver according to these two ID, finishes enumeration process.

3, install driver: host computer is searched corresponding driver (driver can be stored on the main frame in advance) according to this sequence number.If can not find, then can point out user installation driver (driver can load by CD-ROM).The hypothesis driven program has been installed, and WINDOWS can find and move the corresponding driving program so.Can find after the operation of this driver to be custom-designed 8051 codes of this hardware, and it is downloaded in the internal storage of CY7C68013 of USB2.0 controller.

4, setting up communication connects: the CY7C68013 of USB2.0 controller is by changing special control word, changes the enabling address of program into the new porch that downloads, then temporary transient be connected (but physical connection does not change) that disconnects with computing machine.Behind several milliseconds, recover it and connect, the operation of 8051 in USB2.0 controller firmware program.Thereby, set up normal communication between the CY7C68013 of host computer and USB2.0 controller.

5, download the FPGA program: at first call the subroutine of the download FPGA in the firmware, height behind several milliseconds, is put with PA3, promptly the zero clearing of FPGA internal register with the IO mouth PA3 zero clearing of the CY7C68013 of USB2.0 controller again by elder generation.Dispose serial ports 0 afterwards and be synchronous mode, the HEX configuration file of FPGA leaves in the host computer at the beginning.By usb bus, configuration file is transferred in the data register of serial ports 0.CCLK sends synchronous clock, and the DIN pin sends data.FPGA is carried out the configuration of driven serial ports pattern, until the DONE signal is high, the L2 lamp is bright.Represent FPGA configuration successful so.This moment, FPGA can work.

The utility model is mainly used in real-time signal analyzer, and this quasi-instrument will use DSP to finish Signal Processing usually.Using under the prerequisite of the present utility model, relevant DSP program code can be downloaded from host computer by USB interface, and can under the situation that does not change the circuit physical arrangement, just can realize new function, need only total system restart and get final product by downloading new program code.

Claims (2)

1, a kind of high speed USB communication interface device of real time signal processing, it is characterized in that it comprises: USB2.0 controller (1), serial ports eeprom memory circuit (2), FPGA Programmable Logic Device (3), USB communication interface socket (4), voltage conversion circuit (5); USB2.0 controller (1) through extension line respectively with serial ports eeprom memory circuit (2), the Programmable Logic Device of FPGA (3), USB communication interface socket (4), voltage conversion circuit (5) connects; USB communication interface socket (4) is connected to the host computer PC through the USB transmission cable.

2, according to the high speed USB communication interface device of the described a kind of real time signal processing of claim 1, it is characterized in that:

1) USB2.0 controller (1): comprise the CY7C68013 chip of USB2.0 controller, the crystal oscillating circuit that bipod crystal oscillator Y1 and the 1st, 2 electric capacity (C1, C2) are formed; By the 1st switch (S1), the 1st resistance (R1), the reseting switch circuit that the 3rd electric capacity (C3) is formed; By the 2nd resistance (R2), the 2nd switch (SP1), the wake-up circuit that the 4th electric capacity (C4) is formed; The 1st pull-up resistor (R3), the 1st pilot lamp (L1) and insert the 3rd resistance (R4), the 1st signal input resistance (R5), the 1st～10 chip decoupling capacitance (C5～C14);

2). serial ports eeprom memory circuit (2): comprise that capacity is the 24LC01 chip of 16 bytes, be connected to the CY7C68013 chip of USB2.0 controller by lead-in wire SCL and SDA, other has the 2nd, 3 pull-up resistors (R6, R7);

3) .FPGA Programmable Logic Device (3): comprise FPGA Programmable Logic Device chip XC2S50E, crystal oscillator chip CB3LV-3C-40.00, JTAG download interface element U5, and by data line FD0～FD15, address wire GDAR0～GDAR8, control line CTL0, CTL1, CTL2, CTL3 links to each other with the CY7C68013 chip, the CY7C68013 chip is by signal wire PROGRAM in addition, DIN, DONE, CCLK links to each other with the FPGA Programmable Logic Device, the 4th～7 pull-up resistor (R8, R9, R10, R11), signal inserts the 4th resistance (R12), the 2nd pilot lamp L2, the 1st current-limiting resistance (R13), the 5th electric capacity (C15), and the 11st～22 chip decoupling capacitance (C16～C27);

4) .USB communication interface socket (4): use general USB socket, link to each other with the CY7C68013 chip of USB2.0 controller by line USBD+ and USBD-;

5). voltage conversion circuit (5): comprise voltage transformation chip TPS767D318; the 8th pull-up resistor (R14); 1st, 2 protective resistances (R15, R16), (mu balanced circuit of D1～D3) form is by the 6th～11 electric capacity (current stabilization circuit of C28～C33) form by the 1st～3 diode.

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