CN2526908Y

CN2526908Y - Universal system board of single board computer based on PSD

Info

Publication number: CN2526908Y
Application number: CN 01249834
Authority: CN
Inventors: 杨智; 吕伟云
Original assignee: Wuhan University WHU
Current assignee: Wuhan University WHU
Priority date: 2001-06-14
Filing date: 2001-06-14
Publication date: 2002-12-18
Anticipated expiration: 2011-06-14

Abstract

The utility model provides a PSD-based general system board of a single chip microcomputer, comprising the single chip microcomputer and basic circuits connecting data, an address, a control bus and a memory through an address latch circuit and a chip select decode circuit and the utility model adopts a programmable system device (PSD) chip to expand an analog-digital conversion circuit, a digital-analog conversion circuit, a display and keyboard controlling circuit, an I/O expanded circuit, an interrupt expanded circuit, a bus driving circuit, an RS 232 serial interface circuit, a power monitor and control circuit, a voltage reference source circuit, a main interface, a JTAG programming interface and a micro-printer interface. The system board has the advantages of complete functions, steady performance and is easy to upgrade.

Description

Controller general system board based on PSD

The utility model relates to a kind of controller general system board based on PSD, belongs to electronic product.

Single Chip Microcomputer (SCM) system plate on the current home market exists a lot of functions and technical defective and deficiency, as not being implemented in system programmable (ISP) and using reprogrammed (IAP) function; The upgrading and towards the multitask difficulty; Do not solve the limited problem of single-chip microcomputer addressing capability, be not easy to realize the storage space expansion; The function that does not have encryption system; The pcb board space can not make full use of, and is difficult to accomplish miniaturization; There is electromagnetic compatibility (EMC) problem, the poor reliability of system.

The purpose of this utility model is exactly in order to overcome the deficiency of above-mentioned current Single Chip Microcomputer (SCM) system, and a kind of ISP of having and IAP function are provided, and can be easy to upgrading, multiple functional Single Chip Microcomputer (SCM) system plate towards multitask.

For achieving the above object, this use is novel has adopted following technical solution:

The utility model mainly is made up of following each several part: single-chip microcomputer, programmable system device PSD chip, analog to digital conversion circuit, D/A converting circuit, demonstration and keyboard control circuit, I/O expanded circuit, interruption expanded circuit, bus driving circuits, RS232 serial interface circuit, power supply supervisory circuit, voltage reference source circuit, main interface, JTAG DLL (dynamic link library) and mini-printer interface etc.

Its connected mode is: the data of single-chip microcomputer, address bus directly are connected with the PSD chip; Data bus is connected to analog to digital conversion circuit, I/O expanded circuit and interrupts expanded circuit after driving; The PSD chip produces various logic functions, is connected to analog to digital conversion circuit, D/A converting circuit, demonstration and keyboard control circuit, I/O expanded circuit, interrupts expanded circuit etc.; Keyboard and display control circuit supervisory keyboard and demonstration; The RS232 serial interface circuit connects native system and PC; The power supply of power supply supervisory circuit control single chip computer and resetting; Voltage reference source circuit provides the voltage reference of D/A converting circuit; The jtag circuit of PSD built-in chip type is connected to the JTAG DLL (dynamic link library); Data, address, control bus, interruption expansion, I/O expansion etc. are connected to main interface and mini-printer interface.

The native system plate has designed complete at system programmable (ISP) with in the solution of using reprogrammed (IAP), under the constant condition of hardware circuit, can be only by being applicable to different mission requirementses with being configured at system's reprogramming, and current Single Chip Microcomputer (SCM) system can not realize such function.

Its technical scheme is, the C mouth of PSD chip is configured to multiplex mode, its built-in JTAG DLL (dynamic link library) is drawn by the JTAG DLL (dynamic link library) of 14 pins, and every signal wire is pulled to high level with the resistance of I0K, utilize PSD chip programming device Flashlink from PC, code and configuration to be downloaded to the native system plate.

Its principle of work is, generally speaking, the C mouth of PSD chip uses as the I/O mouth, when needs are realized IPS and IAP function, by the P1.6 port of switch notice single-chip microcomputer, the single-chip microcomputer service routine is forbidden the C mouth I/O function of PSD chip, and uses its JTAG function, Flashlink utilizes the JTAG DLL (dynamic link library) on the native system plate, and the flat cable by 14 cores downloads to code on the PC and configuration on the native system plate.When realizing ISP, single-chip microcomputer is an off-line; When realizing IAP, single-chip microcomputer guides and controls whole implementation process.

The PSD chip that the native system plate uses is programmable logic device (PLD) (PLD), utilize its needed logic function of realization system and be connected logic, and designed the suitable interface of PSD chip and other peripheral circuits, compare current Single Chip Microcomputer (SCM) system, saved that sheet is translated decoding circuit, address latch circuit selectively and other are used to realize the circuit of various logic functions.

Its technical scheme is with being configured to the PA0 port of the PSD chip of latch address output, to be connected to the latch address input port AD0 that interrupts extended chip 8259, the chip selection signal of the PB1 port generation 8259 of PSD chip.

In general Single Chip Microcomputer (SCM) system, for solve 8259 with single-chip microcomputer sequential compatibling problem, be to utilize RD behind not gate 74HC04, to produce the INTA signal through the hardware circuit that Sheffer stroke gate 74HC00 constitutes jointly, and utilize RD behind not gate 74HC04, to produce the RD signal through the hardware circuit that Sheffer stroke gate 74HC00 constitutes jointly with INTA8259 with INT8259.

And the native system plate utilizes the PLD unit of PSD chip, the PB5-7 port of PSD chip is configured to INT8259, INTA8259 and RD8259 respectively, it is connected with the RD port with 8259 INT, INTA respectively, and above circuit only needs following two equations to realize:

inta8259＝！(！_rd?&?int8259)；

rd8259＝！(！_rd?&?inta8259)；

Thereby save a 74HC00 and a 74HC04.

With the PA0 and the PA1 port arrangement of PSD chip is latch address output, offer the AD0 and the AD1 port of parallel extended chip 8255, and produce 8255 chip selection signal by the PA2 port of PSD chip, and compare conventional one-piece machine system board, saved address latch and sheet is translated decoding circuit selectively.

Because the address latch of Single Chip Microcomputer (SCM) system makes its signal ALE can lose a pulse when the read-write external data, can't utilize it to use, have a kind of Single Chip Microcomputer (SCM) system to adopt RD, WR now through the common hardware circuit generation ALEFIX signal that constitutes by Sheffer stroke gate 74HC00 behind not gate 74HC04 solves this problem with door 74HC08 and ALE as standard frequency.

The native system plate utilizes the PLD unit of PSD chip, defines an internal node ALEFIX, only needs following equation can realize the function of above-mentioned hardware circuit:

aleout＝！(！ale?&?(_wr#_rd))；

The native system plate has adopted the storage paging scheme, has broken through the restriction that conventional one-piece machine system can only have the 64KB storage space at most, and maximum can enlarge 256 times with the addressing space of single-chip microcomputer.

Its technical scheme and principle be, the page register of Single-chip Controlling PSD chip internal will be mapped to the different pages respectively greater than the storage space of 64KB, and the storage space that each page distributes is no more than 64KB.Make the address realm and the page of SRAM and I/O equipment irrelevant, in data space, no matter which storage page is effective, and MCU can visit SRAM and I/O equipment.In the program space, open up and one section irrelevant space of the page, place resetting and initialization subroutine, interrupt service subroutine, I/O and memory management subroutine, IAP load module code and of single-chip microcomputer no matter select which storage page, necessary addressable any other content, no matter which storage page is effective like this, system can both operate as normal, and single-chip microcomputer also can be visited the data and the program space above 64KB simultaneously.

The native system plate does not have defective secret and defencive function at general Single Chip Microcomputer (SCM) system plate, has designed the privacy protection system, both can all encrypt the logic and the data of total system, can encrypt a certain section of data separately yet.

Its technical scheme and principle be, when the PSD chip is configured, its position (setsecurity) of maintaining secrecy is set, and then the logic of total system plate and data are protected, can't read any content in the chip; By the storage compartments safeguard bit is set, can protect a certain storage compartments respectively, to prevent accidental erasure.Simultaneously, in system's operational process, flash protection and configuration protection register that can also be by the PSD chip internal be maintained secrecy and are protected setting.

The native system plate uses switching capacity filter MAX7403 and digital-to-analog conversion adapter amplifier MAX400 on backward channel, and design suitable selection circuit, make native system can select the polarity of exporting, also can select the output of digital-to-analog conversion whether to pass through wave filter simultaneously.

Its technical scheme is to design the bridle wire apparatus JP1-JP4 of four three pins, and each pin according to the form below of each wire jumper is connected.

Its principle of work is, when JP1 and JP2 were 1,2 pin short circuits, the output of backward channel was applicable to tasks such as audio playback through wave filter; When JP1 and JP2 were 2,3 pin short circuits, the input/output terminal of filtering chip MAX7403B was all by unsettled, and the obstructed wave filter of the output of backward channel goes for intelligent measurement and control type task.When JP3 and JP4 are 1,2 short circuits, select unipolarity output; When JP3 and JP4 are 2,3 short circuits, select bipolarity output.

Because the utility model has adopted above technical scheme, thereby improves the performance of this system board greatly, have powerful, characteristics such as adaptability strong, stable performance.

The utility model is described in further detail below in conjunction with accompanying drawing:

Fig. 1 is a theory diagram of the present utility model.

Fig. 2 is the JTAG programmed circuit figure in the utility model.

Fig. 3 is the interruption Extended Principle Diagram in the utility model.

Fig. 4 is the backward channel wire jumper synoptic diagram in the utility model.

Fig. 1 is a theory diagram of the present utility model.Wherein 1 is single-chip microcomputer, the 2nd, Power Monitoring Unit, the 3rd, serial communication module, the 4th, PSD chip, the 5th, voltage reference module, the 6th, JTAG DLL (dynamic link library), the 7th, analog-to-digital conversion module, the 8th, D/A converter module, the 9th, parallel expansion module, the 10th, interrupt expansion module, the 11st, keyboard display module, the 12nd, I/O expansion interface.Wherein 1 control the total system plate, 4 produce logic and other circuits needed control signal, 2,3,5,7-11 gets in touch by address, DCB and 1 and 4,6 draw the JTAG needed signal wire of programming, 12 draw various other resources of leaving the user on the system board for.

Fig. 2 is the JTAG programmed circuit figure in the utility model.It is that PSD chip 4 is by the catenation principle figure of JTAG DLL (dynamic link library) 6 with Flashlink programmable device 13.The PSD chip relates to the six roots of sensation signal wire of JTAG programming, is connected to JTAG DLL (dynamic link library) 6 by pull-up resistor, and Flashlink programmable device 13 is programmed in the PSD chip 4 by 6 from PC download code and configuration.

Fig. 3 is the interruption Extended Principle Diagram in the utility model.The PB5-7 port of PSD chip 4 is configured to INT8259, INTA8259 and RD8259 respectively, it is connected with the RD port with the INT, the INTA that interrupt expansion module 10 respectively, utilize 4 to produce 10 needed steering logics; And PA0 with 4 and PA1 port arrangement are latch address output, offer 10 AD0 and AD1 and import as latch address, and the chip selection signal CS8259 of the PB1 port generation 10 with 4 is connected to 10 CS port.

Fig. 4 is the backward channel wire jumper synoptic diagram in the utility model.It is unipolarity or bipolarity that wire jumper JP1-JP4 is used to select the output of digital-to-analog conversion, also can select output whether to pass through wave filter simultaneously.What do not mark in each pin of four wire jumpers is unsettled, when JP1 and JP2 are 1,2 pin short circuits, the OUT end of MAX542 chip outputs to the IN end of MAX7403B chip, and the OUT of MAX7403B chip end outputs to the IN+ end of MAX400 chip, the output process wave filter of backward channel; When JP1 and JP2 were 2,3 pin short circuits, the input/output terminal of filtering chip MAX7403B was all by unsettled, the obstructed wave filter of the output of backward channel.When JP3 and JP4 were 1,2 short circuits, the OUT of MAX400 chip end was connected with the IN-end of self, and the selection unipolarity is exported; When JP3 and JP4 were 2,3 short circuits, the OUT of MAX400 chip end was connected with the REFB end of MAX542 chip, and the IN-of MAX400 chip end is held with the INV of MAX542 chip and is connected simultaneously, and the selection bipolarity is exported.

Claims

1, a kind of Single Chip Microcomputer (SCM) system plate based on PSD, comprise single-chip microcomputer and translate decoding circuit selectively by address latch circuit and sheet, with data, the address, the basic circuit that control bus is connected with storer, it is characterized in that: use programming device PSD chip, the PSD chip directly and the data of single-chip microcomputer, address bus connects, data bus is connected to analog to digital conversion circuit after driving, I/O expanded circuit and interruption expanded circuit, simultaneously, each logic function line of PSD chip correspondence respectively is connected to analog to digital conversion circuit, D/A converting circuit, show and keyboard control circuit, the I/O expanded circuit, interrupt expanded circuit, the jtag circuit of PSD built-in chip type is connected to JTAG DLL (dynamic link library), data, the address, control bus, interrupt expanded circuit, the I/O expanded circuit also links to each other with the mini-printer interface with main interface.

2, the controller general system board based on PSD according to claim 1, it is characterized in that: be connected with power supply supervisory circuit on the single-chip microcomputer, be connected by the RS232 serial interface circuit between PC and native system plate, also be connected with voltage reference source circuit on the D/A converting circuit.

3, the controller general system board based on PSD according to claim 1 and 2, it is characterized in that: the C mouth of PSD chip is configured to multiplex mode, its built-in JTAG DLL (dynamic link library) is drawn by the JTAG DLL (dynamic link library) of 14 pins, and the resistance that is connected to 10K on every signal wire makes each signal wire be pulled to high level, and the code and the configuration that utilize PSD chip programming device Flashlink to download from PC are housed in the simultaneity factor plate.

4, controller general system board based on PSD according to claim 1 and 2, it is characterized in that: interrupt expanded circuit and select interruption extended chip 8259 for use, the PA0 port that is configured to the PSD chip of latch address output is connected to the latch address input port AD0 that interrupts extended chip 8259, the PB1 port of PSD chip produces 8259 chip selection signal, the PB5-7 port of PSD chip is configured to INT8259 respectively, INTA8259 and RD8259, with its respectively with 8259 INT, INTA is connected with the RD port, utilizes the PLD unit of PSD chip to produce 8259 needed logics.

5, the controller general system board based on PSD according to claim 1 and 2 is characterized in that:

The native system version uses switching capacity MAX7403 and digital-to-analogue to transform adapter amplifier MAX400 on backward channel, and MAX542, design wire jumper JP1-JP4, being used to select the output of digital-to-analog conversion is unipolarity or bipolarity, also can select simultaneously output whether to pass through wave filter, each pin annexation of each wire jumper is as shown in the table: When JP1 and JP2 were 1,2 pin short circuits, the OUT of MAX542 chip end outputed to the IN end of MAX7403B chip, and the OUT of MAX7403B chip end outputs to the IN+ end of MAX400 chip, and the output of backward channel is through wave filter; When JP1 and JP2 are 2,3 pin short circuits, the input/output terminal of filtering chip MAX7403B is all by unsettled, the obstructed wave filter of the output of backward channel, when JP3 and JP4 were 1,2 short circuits, the OUT of MAX400 chip end was connected with the IN-end of self, and the selection unipolarity is exported, when JP3 and JP4 are 2,3 short circuits, the OUT end of MAX400 chip is connected with the REFB end of MAX542 chip, and the IN-of MAX400 chip end is connected with the INV end of MAX542 chip simultaneously, selects bipolarity output.