CN2687849Y - Four-side flat chip packaging structure - Google Patents
Four-side flat chip packaging structure Download PDFInfo
- Publication number
- CN2687849Y CN2687849Y CN 200420019341 CN200420019341U CN2687849Y CN 2687849 Y CN2687849 Y CN 2687849Y CN 200420019341 CN200420019341 CN 200420019341 CN 200420019341 U CN200420019341 U CN 200420019341U CN 2687849 Y CN2687849 Y CN 2687849Y
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- packaging structure
- fin
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a packaging structure of a four-side flat chip. The traditional packaging structure has the problem of unfavorable radiation effect. The packaging structure includes a substrate, a chip, a radiation fin and a pin. The chip is pasted on one side of the substrate; the radiation fin is pasted on the other side of the substrate; the pin is electrically connected to the chip by a gold thread; the substrate, the chip and the radiation fin are packaged in a plastic packaging body. The packaging structure is characterized in that: the pin bends to one side of the chip. When the integrated circuit with the packaging structure is installed on a circuit board, the radiation fin can be provided upward, so as to effectively enhance the radiation effect.
Description
Technical field
The utility model relates to the encapsulation of integrated circuit (IC) chip, relates in particular to a kind of flat-four-side (QFP) chip-packaging structure with preferable heat dispersion.
Background technology
The Chip Packaging form of flat-four-side (QFP) is by extensive and a large amount of technology of using in the present integrated circuit encapsulation field.Be accompanied by the development of electronic technology high density and miniaturization, the integrated level of integrated circuit (IC) chip is more and more higher, and it is more and more serious that the heat dissipation problem of corresponding devices also becomes.Though PBGA encapsulation has become present main flow packing forms, the QFP encapsulating structure also plays a part indispensable, thereby the heat dissipation problem of QFP encapsulating structure, also becomes one of problem that people pay special attention to.Below the structure of traditional QFP encapsulation is done a summary.
See also Fig. 1, Fig. 1 shows traditional a kind of QFP chip-packaging structure.In this structure, chip 105 is secured on the substrate 106, and chip 105 electrically connects by gold thread 101 and pin 102, and chip 105 and substrate 106 are encapsulated in the plastic-sealed body 103.In the time of on being installed in printed circuit (PCB) plate 104, the heat radiation approach of this encapsulating structure has following several, and first, the heat that produces of chip 105 conducts heat on the pcb board 104 by gold thread 101, pin 102, by pcb board 104 heat is loose again; The second, the heat that produces of chip 105 conducts to the bottom of integrated circuit by plastic-sealed body 103, and then by pcb board 104 heat is taken away; Three, the heat that produces of chip 104 conducts to the top of integrated circuit, heats sink in the middle of the air by radiation then.Because the conductive coefficient of copper pin is higher than plastic-sealed body 103 far away, so the heat overwhelming majority that common Q FP encapsulating structure produces is taken away by article one approach.
See also Fig. 2, QFP encapsulating structure shown in Figure 2 is the improvement to Fig. 1, and its difference is to have increased a fin 107 on the basis of the encapsulating structure of Fig. 1.Fin 107 sticks on a side of substrate 106, and is encapsulated in equally in the plastic-sealed body 103.This mode has improved the radiating efficiency of above-mentioned second approach greatly.Yet as shown in Figure 2, the integrated circuit of this encapsulating structure is on being installed to pcb board 104 time, and fin 107 is towards pcb board, and its efficient still can not be given full play to.
The utility model content
Therefore, the purpose of this utility model is to provide a kind of encapsulating structure through improved flat-four-side chip, and this structure has better radiating effect.
According to above-mentioned purpose, the encapsulating structure of flat-four-side chip of the present utility model comprises: substrate, the pin that is pasted on chip on described substrate one side, is pasted on the fin on the described substrate another side and electrically connects by gold thread and described chip, described substrate, described chip and described fin are packaged in the plastic-sealed body, it is characterized in that described pin is to described chip one lateral buckling.
In the encapsulating structure of above-mentioned flat-four-side chip, the surface of described fin is exposed to outside the described plastic-sealed body.
As mentioned above the integrated circuit of encapsulating structure when mounted, fin is towards the top, so, the heat on the fin distributes by air, thereby improves the radiating effect of this encapsulating structure.
Description of drawings
Fig. 1 is the schematic diagram of an example of traditional QFP chip-packaging structure;
Fig. 2 is the schematic diagram of another example of traditional QFP chip-packaging structure;
Fig. 3 is the schematic diagram of QFP chip-packaging structure of the present utility model.
Embodiment
Comparison diagram 3 and structure shown in Figure 2 as can be seen, the internal structure of QFP chip-packaging structure of the present utility model is similar, includes substrate 206, chip 205 sticks on the side of substrate 206, chip 205 electrically connects by gold thread 201 and pin 202.On the another side of substrate 206, be pasted with fin 207.Substrate 206, chip 205 and fin 207 all are packaged in the plastic-sealed body 203.For improving radiating effect, fin 207 can be exposed to outside the plastic-sealed body 203.
The improvements of QFP chip-packaging structure of the present utility model are: changed the overbending direction of pin 202, with the overbending direction of pin 202 by traditional changing into towards chip one side towards fin one side.After this improvement, when so packaged integrated circuits is on being installed to circuit board 204, can make the one side of being with fin 207, thereby improve the radiating effect of this encapsulating structure towards the top.
Claims (2)
1, a kind of encapsulating structure of flat-four-side chip comprises: substrate, the pin that is pasted on chip on described substrate one side, is pasted on the fin on the described substrate another side and electrically connects by gold thread and described chip, described substrate, described chip and described fin are packaged in the plastic-sealed body, it is characterized in that described pin is to described chip one lateral buckling.
2, the encapsulating structure of flat-four-side chip as claimed in claim 1 is characterized in that, the surface of described fin is exposed to outside the described plastic-sealed body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420019341 CN2687849Y (en) | 2004-01-09 | 2004-01-09 | Four-side flat chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420019341 CN2687849Y (en) | 2004-01-09 | 2004-01-09 | Four-side flat chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2687849Y true CN2687849Y (en) | 2005-03-23 |
Family
ID=34669126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420019341 Expired - Lifetime CN2687849Y (en) | 2004-01-09 | 2004-01-09 | Four-side flat chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2687849Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100464405C (en) * | 2005-10-31 | 2009-02-25 | 台达电子工业股份有限公司 | Method and structure for packaging power module |
| CN101729803A (en) * | 2008-10-10 | 2010-06-09 | 索尼株式会社 | Solid-state image pickup device and signal processing system |
-
2004
- 2004-01-09 CN CN 200420019341 patent/CN2687849Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100464405C (en) * | 2005-10-31 | 2009-02-25 | 台达电子工业股份有限公司 | Method and structure for packaging power module |
| CN101729803A (en) * | 2008-10-10 | 2010-06-09 | 索尼株式会社 | Solid-state image pickup device and signal processing system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: RIYUEGUANG ENCAPSULATION TESTING ( SHANGHAI ) CO., Free format text: FORMER NAME: WEI-YU TECHNOLOGY TEST PACKAGE (SHANGHAI) CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: Shanghai City, Pudong Zhangjiang High tech Zone GuoShouJing road 669, zip code: 201203 Patentee after: ASE Assembly & Test (Shanghai) Limited Address before: Floor 1, building 5, building 200, Newton Road, Zhangjiang hi tech park, Shanghai, Pudong 201203, China Patentee before: Weiyu Science & Technology Test Package (Shanghai) Co. Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20140109 Granted publication date: 20050323 |