CN2678026Y - Storage structure of intelligent card - Google Patents
Storage structure of intelligent card Download PDFInfo
- Publication number
- CN2678026Y CN2678026Y CN 03255249 CN03255249U CN2678026Y CN 2678026 Y CN2678026 Y CN 2678026Y CN 03255249 CN03255249 CN 03255249 CN 03255249 U CN03255249 U CN 03255249U CN 2678026 Y CN2678026 Y CN 2678026Y
- Authority
- CN
- China
- Prior art keywords
- mapping
- address space
- group
- memory
- logical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Memory System (AREA)
Abstract
The utility model relates to a storage structure of intelligent card, comprising a storage management unit (1), and a linearity physical address space (2) compising a program storage (21), an external data storage (22), and a nonvolatile storage (23); a data pointer in a program counter and the external data storage (22) of the program storage (21) denotes a logic address and is provided with eight groups of mapping relation; the linearity physical address space (2) is mapped through the control of the storage management unit (1), and every group of mappings can be addressed in linearity physical address space. The utility model has the advantages that because the mapping relation isn't overlapped physically so that the code and data of the various application programs are completely isolated to considerably increase the flexibility of the smart card application.
Description
Technical field
The utility model relates to a kind of design of Intelligent Card, relates in particular to a kind of memory construction of smart card.
Background technology
Now, smart card has obtained using very widely, as traffic, hotel, finance and social security.Use just because of have so widely, so smart card needs often to upgrade or increase the program of downloading and often carry out great amount of data transmission, encryption and storage.Require the energy consumption of smart card low simultaneously, less demanding to the arithmetic speed of CPU.Therefore, the CPU of most smart card and memory construction all are to improve to obtain on the basis of 8051 single-chip microcomputers of standard.
8051 single-chip microcomputers of standard have five independently storage spaces:
64K byte program storage space (0 ~ 0FFFFH);
256 byte inner ram spaces (0 ~ 0FFH);
128 byte inner special function register spaces (80H ~ 0FFH);
Bit addressing space (0 ~ 0FFH);
64K byte external data memory space (0 ~ 0FFFFH).
Program memory space is the 64K byte, and its address pointer is the programmable counter PC of sixteen bit.The external data memory space is the 64K byte, and its address pointer is the data pointer DPTR of sixteen bit.
But in the face of complicated day by day application, memory data output increases, and intelligent card in processing speed needs to increase.Need expanded data or code memory space to comprise program storage and external data memory, Zhi Ling execution speed will be accelerated simultaneously.The kernel of standard 8051 is obviously not competent.
And the increase of storage space obviously can not reach by the figure place that increases programmable counter (PC) and data pointer (DPTR).Because such way underaction, even can't reach the requirement of some application.When in program storage, coexisting, require on code and data, to isolate fully each other, rely on above-mentioned way just can't solve such as a plurality of application programs.
Summary of the invention
The utility model technical issues that need to address have provided a kind of memory construction of smart card, are intended to solve at present when a plurality of application programs coexist in program storage, the defective of isolation fully on code that can not be each other and the data.
In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:
Memory construction of the present utility model comprises Memory Management Unit (MMU), linear physical address space;
Described linear physical address space comprises program storage (ROM) and external data memory (XRAM) and nonvolatile memory (NVM); With programmable counter in the program storage and the data pointer presentation logic address in the external data memory, eight groups of mapping relations are set, shine upon linear physical address space by the control of Memory Management Unit, each group mapping can be in linear physical address space addressing.
Compared with prior art, the beneficial effects of the utility model are: owing to accomplished that mapping relations do not overlap each other physically, the code and the data of various application programs can be kept apart completely, increase the dirigibility of application of IC cards greatly.
Description of drawings
Fig. 1 is a structural representation of the present utility model;
Fig. 2 is a system model 0-3 group mapping synoptic diagram;
Fig. 3 is an application model 4-7 group mapping synoptic diagram;
Fig. 4 is a logical segment pointer structure synoptic diagram;
Fig. 5 is linear physical address space addressing synoptic diagram;
Fig. 6 is the mapping of logical address to linear physical address space;
Fig. 7 is a logical segment pointer addressing synoptic diagram;
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:
By Fig. 1,2,3,4,5,6 as seen: memory construction of the present utility model comprises Memory Management Unit 1, linear physical address space 2; Described linear physical address space comprises program storage 21 and external data memory 22 and nonvolatile memory 23; With the data pointer presentation logic address in programmable counter in the program storage 21 and the external data memory 22, eight groups of mapping relations are set, shine upon linear physical address space 2 by the control of Memory Management Unit 1, each group mapping can be in linear physical address space 2 addressing;
Described linear physical address space 2 is 1M bytes, and the start address of program storage 21 is 00000H, and the end address is 3FFFFH; The start address of external data memory 22 is 40000H, and the end address is 7FFFFH; The start address of nonvolatile memory 23 is 80000H, and the end address is FFFFFH;
Described logical address is that address with original code and data addressing space is as logical address, be divided into two logical segments respectively, be respectively logical program memory address space and logic external data memory address space, each logical segment be the 32K byte to the maximum, the scope of addressing all is the 64K byte;
Described eight groups of mapping relations are 0-7 groups;
Described the 0th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 1st group of mapping is high 32K bytes range;
Described the 2nd group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 3rd group of mapping is high 32K bytes range;
Described the 4th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 5th group of mapping is high 32K bytes range;
Described the 6th group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 7th group of mapping is high 32K bytes range;
0-3 is organized mapping relations belong to system model, 4-7 group mapping relations belong to application model;
Described logical segment pointer (mapping relations) comprises three bytes, and first byte is the length of logical segment, and second and third byte is the Gao Siwei of the plot of logical segment in linear physical address space 2 and hangs down eight;
To be logical addresses add plot with respect to the side-play amount of logical segment reference position to described linear physical address space 2;
It is that the present mode that other except that the 0th group 7 groups, the current mapping relations that should use of decision and control smart card kernel is set by Memory Management Unit 1 is system model or application model that linear physical address space 2 is shone upon in described control by Memory Management Unit 1;
Described nonvolatile memory 23 can be EEPROM.
Control method of the present utility model realizes by following steps:
Linear physical address space is divided into program storage, external data memory and nonvolatile memory;
With programmable counter in the program storage and the data pointer presentation logic address in the external data memory, eight groups of mapping relations are set;
Shine upon linear physical address space by the control of Memory Management Unit, each group mapping can be in linear physical address space addressing.
In the described first step: described linear physical address space is the 1M byte, and the start address of program storage is 00000H, and the end address is 3FFFFH; The start address of external data memory is 40000H, and the end address is 7FFFFH; The start address of EEPROM is 80000H, and the end address is FFFFFH;
In described second step: logical address is that address with original code and data addressing space is as logical address, be divided into two logical segments respectively, be respectively logical program memory address space and logic external data memory address space, each logical segment be the 32K byte to the maximum, the scope of addressing all is the 64K byte;
Described eight groups of mapping relations are 0-7 groups;
Described the 0th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 1st group of mapping is high 32K bytes range;
Described the 2nd group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 3rd group of mapping is high 32K bytes range;
Described the 4th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 5th group of mapping is high 32K bytes range;
Described the 6th group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 7th group of mapping is high 32K bytes range;
0-3 is organized mapping relations belong to system model, 4-7 group mapping relations belong to application model;
Described logical segment pointer (mapping relations) comprises three bytes, and first byte is the length of logical segment, and second and third byte is the Gao Siwei of the plot of logical segment in linear physical address space and hangs down eight;
To be logical address add plot with respect to the side-play amount of logical segment reference position to described linear physical address space;
In described the 3rd step: be that the present mode that other except that the 0th group 7 groups, the current mapping relations that should use of decision is set and controls the smart card kernel by Memory Management Unit is system model or application model
Below principle of the present utility model is described as follows:
The utility model proposes a kind of notion of memory mapped, promptly the linear physical address space of a 1M byte is shone upon in programmable counter and data pointer presentation logic address by Memory Management Unit.The nonvolatile memory (NVM, that use in the utility model is EEPROM) that linear physical address space has comprised program storage and external data memory and forever preserved data or code.In order to increase dirigibility, be provided with eight groups of mapping relations altogether.Each group mapping (the 0th group outer) can be in any addressing of the physical address space of linearity, and such eight groups of mappings independently are mapped to specific physical address separately.Because EEPROM is erasable and can preserve data when power down, so just can be after dispatching from the factory random therein burned application program, increased the dirigibility of application of IC cards greatly.As long as accomplish that simultaneously mapping relations do not overlap each other physically, just the code and the data of various application programs can be kept apart completely.In order to show the mapping relations of current use, be provided with a pointer in the middle of the MMU design, the state that this pointer determining program counter (PC) and instruction are carried out points to corresponding mapping, carries out the addressing of physical address by this pointer.
Memory Management Unit is being controlled the use of mapping relations, determines the current mapping relations that should use.By the execution of decision instruction and the position of programmable counter, MMU is controlling the present mode of smart card kernel simultaneously.
Have two kinds of patterns: system model and application model.System model uses the 0th ~ 3 group of mapping relations down, uses the 4th ~ 7 group of mapping relations under the application model.
Under the system model, the low 32K bytes range of logical program memory address space is used the 0th group of mapping, and high 32K bytes range is used the 1st group of mapping; The low 32K bytes range of logic external data memory address space is used the 2nd group of mapping, and high 32K bytes range is used the 3rd group of mapping.
Under the application model, the low 32K bytes range of logical program memory address space is used the 4th group of mapping, and high 32K bytes range is used the 5th group of mapping; The low 32K bytes range of logic external data memory address space is used the 6th group of mapping, and high 32K bytes range is used the 7th group of mapping.
Adopted the logical segment pointer in the design of MMU, promptly register is used for indicating presently used mapping group.The logical segment pointer is used for logical address, each pointer of program memory address space and external data memory address space.The program storage segment pointer can be 0,1,4 and 5, and the external data memory segment pointer can be 2,3,6 and 7.
Eight groups of mapping relations corresponding respectively the eight groups of registers that can revise.One group of register is three bytes, and first byte has been pointed out the length of logical segment, and second and third byte is pointed out the Gao Siwei of the plot of logical segment in physical memory address space and hanged down eight.Logical address adds that with respect to the side-play amount of logical segment reference position plot is exactly the physical address of ultimate demand.
The start address of program storage is 00000H, and the end address is 3FFFFH; The start address of external data memory is 40000H, and the end address is 7FFFFH; The start address of nonvolatile memory is 80000H, and the end address is FFFFFH.Can calculate ROM on this basis and be the 256K byte to the maximum, XRAM is the 256K byte to the maximum, and EEPROM is the 512K byte to the maximum.This just can adapt to the setting under the current application environment, as long as the production technology of chip and designed capacity allow, can continue to expand physical address space fully.
The beginning of physics ROM storer comprises interrupts entry address and interrupt vector, has only from just entering interrupt service routine (ISR) here.
For can be on the basis of standard 8051 addressing capabilities the scope of expanded addressing, the code of standard 8051 and data address are removed the specific part of addressing physical memory space as logical address by the mapping of Memory Management Unit (MMU).Logical code and external data address space are divided into two sections of 32K byte respectively, use different mapping relations addressing physical storages.Respectively use four groups of mapping relations under system model and the application model.System model uses the 0th ~ 3 group of mapping relations down, uses the 4th ~ 7 group of mapping relations under the application model.System model offers operating system and uses, the code that all kinds of resources that the operating system assigns applications is used, the system call of response application program and division application program are used and the physical storage of data.Therefore, the 0th group of mapping relations are the 32K byte space that fixing 0 address that is mapped to physical memory address space of the logic addressing space of initial 32K byte begins from the logical zero address under the system model, the just low 32K byte of physics ROM storer.So only just can enter interrupt service routine under system model, calling by operating system that assurance is interrupted monitored.Use the other four groups of mapping relations that are different from system model under the application model, can set these four groups of mapping relations under the system model in advance.
Eight groups of mapping relations are actual to be eight groups of registers.Each group register comprises the data of three bytes, and first byte has been pointed out the length of logical segment, and second and third byte is pointed out the Gao Siwei of the plot of logical segment in physical memory address space and hanged down eight.Logical segment is the 32K byte to the maximum, is span with 256 bytes, so low 7 sizes that just can determine logical segment of designated length byte, a high position is waited until in the future and expanded.Plot has 12 significance bits, is span with 256 bytes also, so plot can be located in size is the amount of physical memory of 1M byte.High-order plot is waited until when expanding in the future and is used.
The computing method of physical address when using a certain group of mapping relations.The reference position of logical address PC or the relative logical segment of DPTR is got low 15 of side-play amount, and base address the right adds eight 0, has just obtained physical address corresponding afterwards with offset addition.
All the other can be provided with eight groups of registers except that the 0th group, and for logical segment to the mapping of physical address space without any restriction.Therefore can logical code be mapped to ROM and XRAM and NVM by mapping relations are set, be that code will be carried out from XRAM or NVM, in like manner we also can be mapped to XRAM and NVM and ROM to the logic external data, and external data just can be taken out from the code of ROM storage like this.Can be in NVM the code storage of application program, during the needs execution, just can be as long as logical code is mapped to NVM from wherein carrying out.Code among the NVM can upgrade according to different application, downloads again also can revise code when application changes after.The structure that can see the sort memory mapping has very large dirigibility.
In addition, the 4th ~ 7 group of mapping relations are that specific assigned is used to application program.Data in the mapping register are that operating system is distributed in advance, as long as being arranged on of mapping is physically not overlapping, just can guarantee that the code of application program and data are kept apart each other completely.This point embodied the sort memory mapping structure security.
Memory Management Unit is between CPU and the physical storage device, and it determines the operator scheme of current C PU, and code or the data map relation correct according to model selection.In the design of MMU, in order correctly to indicate current code that should use or data map relation, we have introduced the notion of logical segment pointer.Segment pointer points out that current which group mapping relations of should using are mapped to physical address with logical address.One has two segment pointers, a code segment pointer, and another is the data segment pointer.As shown in Figure 7, if current being under the system model, when PC is positioned between logical address 8000H ~ FFFFH, the code segment pointer should be changed to 1, promptly use the 1st group of mapping relations to come the addressing physical address, and DPTR is when being positioned between the 0000H ~ 7FFFH of logical data address, and the data segment pointer should be changed to 2, promptly uses the 2nd group of mapping relations to come the addressing physical address.In like manner in application model following time, the code segment pointer should be changed to 5, and the data segment pointer should be changed to 6.
Segment pointer is actually register, by the corresponding conversion value of condition of judgment model conversion.The notion of segment pointer make the code of design be easily understood, cheer and bright, and very clear of when programming thinking.
Memory construction of the present utility model has good expansion capacity.Physical base address field in the mapping register group has in fact only been used 12, if its whole 16 are all used, and the physical memory address space that maximum can addressing 16M byte.And the logical segment length field has been used 7, if use the maximum length of 8 logical segments to be the 64K byte, if only use 6, the maximum length of logical segment is the 16K byte so.So just can adapt to the application of differing complexity.
In sum, the utility model is with respect to the advantage of existing smart card memory administrative skill, increased storage space greatly, can hold a plurality of application programs, application program is isolated on code and data to each other and between application program and operating system fully, safe, also have very strong extended capability simultaneously.
Claims (3)
1. the memory construction of a smart card is characterized in that: comprise Memory Management Unit (1), linear physical address space (2); Described linear physical address space comprises program storage (21) and external data memory (22) and nonvolatile memory (23); With the data pointer presentation logic address in programmable counter in the program storage (21) and the external data memory (22), eight groups of mapping relations are set, shine upon linear physical address space (2) by the control of Memory Management Unit (1), each group mapping can be in linear physical address space (2) addressing.
2. the memory construction of smart card according to claim 1, it is characterized in that: described linear physical address space (2) is the 1M byte, and the start address of program storage (21) is 00000H, and the end address is 3FFFFH; The start address of external data memory (22) is 40000H, and the end address is 7FFFFH; The start address of nonvolatile memory (23) is 80000H, and the end address is FFFFFH;
Described logical address is that address with original code and data addressing space is as logical address, be divided into two logical segments respectively, be respectively logical program memory address space and logic external data memory address space, each logical segment be the 32K byte to the maximum, the scope of addressing all is the 64K byte;
Described eight groups of mapping relations are 0-7 groups;
Described the 0th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 1st group of mapping is high 32K bytes range;
Described the 2nd group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 3rd group of mapping is high 32K bytes range;
Described the 4th group of mapping is the low 32K bytes range of logical program memory address space;
Described the 5th group of mapping is high 32K bytes range;
Described the 6th group of mapping is the low 32K bytes range of logic external data memory address space;
Described the 7th group of mapping is high 32K bytes range;
0-3 is organized mapping relations belong to system model, 4-7 group mapping relations belong to application model;
Described logical segment pointer (mapping relations) comprises three bytes, and first byte is the length of logical segment, and second and third byte is the Gao Siwei of the plot of logical segment in linear physical address space 2 and hangs down eight;
To be logical addresses add plot with respect to the side-play amount of logical segment reference position to described linear physical address space 2;
It is that the present mode that other except that the 0th group 7 groups, the current mapping relations that should use of decision and control smart card kernel is set by Memory Management Unit 1 is system model or application model that linear physical address space 2 is shone upon in described control by Memory Management Unit 1.
3. the memory construction of smart card according to claim 1 and 2, it is characterized in that: described nonvolatile memory 23 can be EEPROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03255249 CN2678026Y (en) | 2003-07-04 | 2003-07-04 | Storage structure of intelligent card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03255249 CN2678026Y (en) | 2003-07-04 | 2003-07-04 | Storage structure of intelligent card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2678026Y true CN2678026Y (en) | 2005-02-09 |
Family
ID=34580390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03255249 Expired - Fee Related CN2678026Y (en) | 2003-07-04 | 2003-07-04 | Storage structure of intelligent card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2678026Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103186812A (en) * | 2011-12-28 | 2013-07-03 | 国民技术股份有限公司 | Smart memory card and method for visiting smart memory card |
| CN103761118A (en) * | 2013-12-27 | 2014-04-30 | 北京大唐智能卡技术有限公司 | Intelligent card and method for deploying applications in same |
| CN103186812B (en) * | 2011-12-28 | 2016-12-14 | 国民技术股份有限公司 | Intelligent memory card and the method accessing intelligent memory card |
-
2003
- 2003-07-04 CN CN 03255249 patent/CN2678026Y/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103186812A (en) * | 2011-12-28 | 2013-07-03 | 国民技术股份有限公司 | Smart memory card and method for visiting smart memory card |
| CN103186812B (en) * | 2011-12-28 | 2016-12-14 | 国民技术股份有限公司 | Intelligent memory card and the method accessing intelligent memory card |
| CN103761118A (en) * | 2013-12-27 | 2014-04-30 | 北京大唐智能卡技术有限公司 | Intelligent card and method for deploying applications in same |
| CN103761118B (en) * | 2013-12-27 | 2018-05-04 | 北京大唐智能卡技术有限公司 | A kind of smart card and the method for smartcard internal administration application |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5895501A (en) | Virtual memory system for vector based computer systems | |
| US7509391B1 (en) | Unified memory management system for multi processor heterogeneous architecture | |
| KR102309798B1 (en) | SR-IOV based non volatile memory controller and method for dynamically allocating resources to queues by the non volatile memory controller | |
| US6499095B1 (en) | Machine-independent memory management system within a run-time environment | |
| CN101375248B (en) | Hardware Javatm bytecode translator | |
| US20180095892A1 (en) | Processors, methods, systems, and instructions to determine page group identifiers, and optionally page group metadata, associated with logical memory addresses | |
| CN87100507A (en) | Stack frame cache on the microprocessor chip | |
| KR20130048206A (en) | Hierarchical translation tables control | |
| CN1950802A (en) | Memory allocation | |
| CN101063957A (en) | System and method for managing replacement of sets in a locked cache | |
| EP3855318A1 (en) | Apparatus and method for configuring sets of interrupts | |
| US20090037501A1 (en) | Method and system for managing memory for a program using area | |
| TWI779438B (en) | Methods of storing data, electronic devices and storage media | |
| EP4020234A1 (en) | Circuitry and methods for low-latency page decompression and compression acceleration | |
| CN101777061A (en) | JAVA card object management method and JAVA card | |
| EP3732576A1 (en) | Systems, methods, and apparatuses for patching pages | |
| CN1567367A (en) | Memory construction of smart card and control method thereof | |
| CN2678026Y (en) | Storage structure of intelligent card | |
| CN1801092A (en) | Embedded chip and its program space extension method | |
| EP1067461B1 (en) | Unified memory management system for multi process heterogeneous architecture | |
| CN100351813C (en) | Method of storage unit access in digital signal processing system and processing system therefor | |
| CN200953143Y (en) | Virtual hardware system | |
| CN108804222B (en) | Temporary variable data area allocation method | |
| EP4030292A1 (en) | Autonomous and extensible resource control based on software priority hint | |
| US7676651B2 (en) | Micro controller for decompressing and compressing variable length codes via a compressed code dictionary |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |