CN200953143Y - Virtual hardware system - Google Patents
Virtual hardware system Download PDFInfo
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- CN200953143Y CN200953143Y CN 200620136595 CN200620136595U CN200953143Y CN 200953143 Y CN200953143 Y CN 200953143Y CN 200620136595 CN200620136595 CN 200620136595 CN 200620136595 U CN200620136595 U CN 200620136595U CN 200953143 Y CN200953143 Y CN 200953143Y
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Abstract
This utility model publicizes a virtual hardware system, consists of father hardware and virtual hardware, in which, the father hardware is connected with the virtual hardware, the virtual hardware outputs the command data, the father hardware receives the command data; the father hardware outputs the command running results, the virtual hardware receives the command running results. This virtual hardware system may read and transfer one command data of virtual hardware through system father hardware, and call the internal resources according to this command, and operate the process flow corresponding to this command according to the called internal resources, reduce the command execution period, thus increase the command execution speed of virtual hardware. Moreover, this utility model may not require to store the identical logic code for realizing the same functions on the system father hardware and virtual hardware respectively, save the system resources.
Description
Technical field
The utility model relates to computer technology, particularly a kind of virtual hardware system.
Background technology
In the computer system, comprise the processor that is used to carry out the particular system instruction set.Different types of processor only can be carried out the pairing instruction set of such processor, and promptly the instruction set of different processor is incompatible.Yet, by carrying out different instruction set, all types of processors can embody different performance advantages, and for example the instruction set of Intel80X86 CPU (central processing unit) (CPU) can realize complicated processing capacity based on complex instruction set computer (CISC) (CICS) form; And the instruction set of Motorola Power PC then based on Reduced Instruction Set Computer (RISC) form, can be carried out the simple process function at a high speed.
Prior art constitutes another kind of processor by the emulation logic unit by in a kind of processor, and the instruction operation process by emulation another kind processor, solves the incompatibility of different instruction collection.In the in esse processor, realize that the hardware resource of original function is called father's hardware, the hardware resource that is made of the emulation logic unit is called virtual hardware.In the virtual hardware system based on the virtual hardware technology, father's hardware can merge the performance advantage of different processor, has cross-platform independence, can guarantee the binary compatible of the code write for virtual hardware when father's hardware platform is changed; And, when the developing instrument of father's hardware is difficult for realizing, can enriches exploitative virtual hardware and compile by having, thereby reduce development difficulty.
Fig. 1 is based on the instruction executing method process flow diagram of virtual hardware system in the prior art.As shown in Figure 1, be that A processor, virtual hardware are that the B processor is an example with father's hardware, the instruction executing method based on virtual hardware system in the prior art may further comprise the steps:
Step 101 is given the B processor with the memory allocation of A processor, as the storage space of the command memory of B processor and data-carrier store etc.;
Instruction after step 104, A processor carry out to transform, and the result that will instruct returns to the data memory space of B processor, returns step 102, the A processor continues to read next bar director data of B processor.
In the above-mentioned flow process, the A processor need read and change each bar instruction in the process of utilizing virtual hardware B processor operating instruction flow process, carry out the instruction of a B processor, may need the instruction of many A processors to realize.
This shows, in the existing virtual hardware system, father's hardware is simulated the execution process instruction of virtual hardware by the mode that reads, transforms instruction one by one, therefore, the instruction that father's hardware is carried out each bar virtual hardware all needs tens even up to a hundred instruction cycles, execution speed is slow, can't satisfy the calculation process process of high performance requirements.And, because father's hardware is simulated the execution process instruction of virtual hardware by the mode that reads, transforms instruction one by one, instruction is carried out and is only limited to the bottom instruction, thereby, existing virtual hardware also can't use the senior resource in father's hardware, the limited resources that only can use father's hardware to distribute make that the range of application of virtual hardware system is less.
The utility model content
In view of this, fundamental purpose of the present utility model is: a kind of virtual hardware system is provided, can executes instruction at a high speed.
According to an above-mentioned fundamental purpose, the utility model provides a kind of virtual hardware system, comprising: father's hardware and virtual hardware, wherein,
Father's hardware links to each other with virtual hardware, virtual hardware output order data, and father's hardware receives director data; Father's hardware output order operation result, virtual hardware receives the instruction operation result.
Described father's hardware comprises: main control unit and resource transfer unit, wherein,
Main control unit links to each other with the resource transfer unit, resource transfer unit output internal resource, and main control unit receives internal resource.
Father's hardware comprises that further the master uses the location of instruction, wherein
Main control unit links to each other with the location of instruction with main, the instruction of master control location of instruction output father hardware, and main control unit receives the instruction of father's hardware;
Main control unit links to each other with virtual hardware, the director data of virtual hardware output virtual hardware and the computing variable of director data correspondence.
Main control unit links to each other with described virtual hardware, described main control unit output operation result, and described virtual hardware receives operation result.
Described virtual hardware comprises: fictitious order storage unit and virtual data storage unit, wherein,
The fictitious order storage unit links to each other with described main control unit, fictitious order storage unit output order data, and described master receives director data with the location of instruction;
The virtual data storage unit links to each other with described main control unit, described main control unit output operation result, and described virtual data storage unit receives operation result, described virtual data storage unit output computing variable, described main control unit receives the computing variable.
Described father's hardware further comprises: the master uses data storage cell, wherein,
The main data storage cell of using links to each other with described main control unit, and described main control unit output computing intermediate value is main with data storage cell reception computing intermediate value; Main with data storage cell output computing intermediate value, described main control unit receives the computing intermediate value.
Described main control unit is electrically-erasable ROM (read-only memory) E
2PROM or random access memory ram;
Described master is a read only memory ROM with the location of instruction;
Described master is RAM with data storage cell;
Described resource transfer unit is E
2PROM.
Described fictitious order storage unit is E
2PROM;
Described virtual data storage unit is RAM.
Described father's hardware is the XA2 processor, and described virtual hardware is 8051 processors.
As seen from the above technical solution, virtual hardware system of the present utility model, director data by the virtual hardware of father's hardware reading and converting in the system, according to this instruction calls internal resource, for example power function and multiple senior resource, and utilize the internal resource that calls, move the corresponding treatment scheme of this instruction, substitute many instruction interaction processes with virtual hardware, reduced instruction execution cycle, thereby improved the instruction execution speed of virtual hardware.And the utility model is by calling the internal resource of father's hardware, need be in father's hardware of system and virtual hardware respectively storage be used to realize the identity logic code of identical function, saved system resource.
Description of drawings
Fig. 1 is based on the instruction executing method process flow diagram of virtual hardware system in the prior art.
Fig. 2 is the exemplary block diagram of virtual hardware system in the utility model.
Fig. 3 is the structural drawing of virtual hardware system among the utility model embodiment.
Fig. 4 is based on the instruction executing method process flow diagram of virtual hardware system among the utility model embodiment.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the utility model is further described.
Fig. 2 is the exemplary block diagram of virtual hardware system in the utility model.As shown in Figure 2, virtual hardware system of the present utility model comprises: father's hardware 201 and virtual hardware 202.
Father's hardware 201 is used for from virtual hardware 202 reading command data, the treatment scheme of the instruction correspondence that operation is read; Send result to virtual hardware 202;
Wherein, be used for the instruction that instruction that father's hardware 201 calls internal resource is made an appointment for father's hardware and virtual hardware, promptly between father's hardware 201 and virtual hardware 202, have mapping relations; Internal resource can be power function, also can be senior resources such as file system; In the instruction set of virtual hardware 202, comprise the corresponding director data of external call instruction with father's hardware, also comprise the director data corresponding with the ordinary instruction of father's hardware, father's hardware 201 only after reading the director data corresponding with the external call instruction, can call the power function of storage inside.
The utility model based on the principle of work of virtual hardware system is: father's hardware 201 father's hardware read the director data in the virtual hardware 202, according to the mapping relations that set in advance, call the internal resource of the director data correspondence that reads; Father's hardware 201 utilizes the internal resource that calls, and moves the corresponding treatment scheme of this instruction, result is returned to virtual hardware 202, and continue to read next bar director data of virtual hardware 202.
Wherein, when the instruction after father's hardware transforms is ordinary instruction, can be according to the method for prior art, the instruction in the reading and converting instruction set one by one.
Below, in conjunction with specific embodiments, be elaborated to virtual hardware system of the present utility model with based on the instruction executing method of virtual hardware system.
Present embodiment is high speed expansion structure microprocessor (the Smart eXtended Architecture 2nd generation of Philip (Philips Semiconductors) company with the physical hardware, SmartXA2) be example, SmartXA2 is called for short XA2, be one 16 microprocessor, be applicable to as Software Development Platform.
Fig. 3 is the structural drawing of virtual hardware system among the utility model embodiment.As shown in Figure 3, be that virtual 8051 processors are example with virtual hardware, virtual hardware system of the present utility model comprises: XA2 processor 301 and virtual 8051 processors 302.
Wherein, XA2 processor 301 comprises: main control unit 310, main with the location of instruction 311 and resource transfer unit 312; Main control unit 310 corresponding physical entities can be the electrically-erasable ROM (read-only memory) (E of physical hardware XA2
2PROM) any storage space in also can be any storage space in the random access memory (RAM); Main is the ROM (read-only memory) (ROM) of physical hardware XA2 with the location of instruction 311 corresponding physical entities; Resource transfer unit 312 corresponding physical entities are the E of physical hardware XA2
2The lower memory space of PROM.
Main be used for the instruction of storing X A2 processor 301, and when powering on, instruction offered main control unit 300 in system with the location of instruction 311.
Virtual 8051 processors 302 comprise fictitious order storage unit 321 and virtual data storage unit 322; Fictitious order storage unit 321 corresponding physical entities are the E of physical hardware XA2
2The higher memory space of PROM; Virtual data storage unit 322 corresponding physical entities are the higher memory space of the RAM of physical hardware XA2.
Fictitious order storage unit 321 is used for the director data of storing virtual 8051 processors 302, and director data is offered the main control unit 310 of XA2 processor 301;
Virtual data storage unit 322 is used for the corresponding computing variable of all instructions of storing virtual 8051 processors 302, and offers the main control unit 310 of XA2 processor 301; Reception is from the result of the main control unit 310 of XA2 processor 301.
In the practical application, main control unit 310 also is used for carrying out the ordinary instruction after transforming when the instruction after the conversion is ordinary instruction, and the result of ordinary instruction is sent to virtual 8051 processors 302.
In this case, main control unit 310 is further used for the corresponding computing intermediate value of each bar instruction is sent to main with data storage cell 313, and when next bar instruction of operation, according to this instruction from the master with reading the computing intermediate value the data storage cell 313.
The virtual hardware system of present embodiment is based on that XA2 realizes, system call interfaces is the mapping relations table between various special instructions and the internal resource; Resource transfer unit 312 and fictitious order storage unit 321 are respectively E among the XA2
2The lower memory space of PROM and higher memory space, the size in space can preestablish as required, also can be set to resource transfer unit 312 as fictitious order storage unit 321, higher memory space for virtual 8051 processors 302 the lower memory allocation of space; Main lower memory space and the higher memory space that is respectively RAM among the XA2 with data storage cell 313 and virtual data storage unit 322, the size in space can preestablish as required, and it is main with data storage cell 313 also to be set to the lower memory allocation of space can for virtual 8051 processors 302 as virtual data storage unit 322, higher memory space.
In the present embodiment, virtual hardware is virtual 8051 processors, with the storage space of RAM in the physical hardware as virtual data storage unit 322, when virtual hardware is the processor of other types, also can be with E
2The storage space of PROM receives the result from XA2 processor 301 as the data storage cell 322 of virtual hardware.
In the present embodiment, virtual hardware is virtual 8051 processors, and virtual RAM 322 is as data space, when virtual hardware is the processor of other types, and virtual E
2PROM 321 also can be used as the data space of virtual hardware, receives the result from XA2 processor 301.
The virtual hardware system of present embodiment also can be based on other physical hardwares, and for example (Advanced RISC Machines ARM), realizes enhancement mode reduced instruction set computer single-chip microcomputer; Virtual hardware in the present embodiment also can also be XA2 itself for reduced instruction set computer single-chip microcomputer (AVR) waits other processors.
Below, the instruction executing method based on said system is elaborated.
Fig. 4 is based on the instruction executing method process flow diagram of virtual hardware system among the utility model embodiment.As shown in Figure 4, the utility model may further comprise the steps based on the instruction executing method of virtual hardware system:
Step 401 is virtual 8051 processor distribution resource spaces.
In the present embodiment, with E in the XA2 processor
2The higher memory allocation of space of PROM is given main control unit; With E
2The lower memory allocation of space of PROM is given virtual 8051 processors, as the fictitious order storage space of virtual 8051 processors; With E
2The residual memory space of PROM is distributed to the XA2 processor, as the resource transfer unit of XA2 processor; Give virtual 8051 processors with the higher memory allocation of space of RAM, as the data space of virtual 8051 processors; Give the XA2 processor with the lower memory allocation of space of RAM, as the data space of XA2 processor.
In the present embodiment, the XA2 processor is from E
2The higher memory space of PROM, be in the fictitious order storage space of virtual 8051 processors, read the command adapted thereto data of 8051 instruction set, the instruction set rule according to virtual 8051 processor correspondences is converted into the instruction that the XA2 processor can be carried out with the director data that reads; Simultaneously, from the data space of virtual 8051 processors, read the corresponding computing variable of this instruction.
In this step, store the mapping table of 8051 instruction set and XA2 instruction set in the XA2 processor, XA2 reads after 8051 instructions, searches inner mapping table, 8051 instructions can be converted into the XA2 instruction, also can transform by other modes.
In this step, the address of the pointed in the ordinary instruction is in the normal address scope of virtual 8051 processors, when the address of pointed is the special address of making an appointment, and there are mapping relations in this instruction and internal resource, judges that then this instruction is the external call instruction; Perhaps, when the order number that reads is the special instruction of A5, and there are mapping relations in this instruction and internal resource, judges that then this instruction is the external call instruction; Structure external call instruction also can be adopted other modes.
In the instruction set of virtual 8051 processors, the instruction of needs being carried out functional operation is set at above-mentioned special instruction, and stores the special instruction mapping table in the XA2 processor, can realize calling of power function.
For example, carry out the instruction of instruction for calling 2000H (16 system) address subroutine of sine function computing in virtual 8051 processors, and the normal address scope of virtual 8051 processors is 1400H, this instruction is special instruction.It is the special address of carrying out sinusoidal computing that XA2 and virtual 8051 processors can be arranged 2000H in advance, when virtual 8051 hardware are carried out the instruction of calling 2000H address subroutine, the address that the XA2 processor is judged earlier in this instruction does not belong in the normal range, search this address in the mapping table of storage internally again, after finding this address, according to the mapping relations of this address in mapping table, can judge the function that need call is sine function, and calls sine function.
In the prior art, the instruction of calling 2000H address subroutine is a disable instruction, carry out sine function and need call the subprogram segment of a hop count hundred even thousands of instructions, and thousands of instructions are converted to the instruction that father's hardware can be carried out one by one, arithmetic speed is obviously very slow; And in the utility model, the XA2 processor is judged the corresponding XA2 instruction of this instruction and is sine function according to the command mappings table of storage inside.
In this step, because what carry out is the function of father's hardware XA2, do not need conversion, therefore speed is much higher than the speed that virtual hardware is carried out, also avoided simultaneously in the prior art must realizing the wasting of resources that two sections identical functions of logic cause in order on father's hardware and virtual hardware, to realize identical function, for virtual 8051 processors, execution in step 404 is not significantly distinguished with calling virtual 8051 processor built-in subroutines, influences the normal operation of virtual 8051 processors hardly; When the mapping result in the special instruction mapping table when calling senior resource, the XA2 processor then calls the upper strata resource in the computer system, for example file system or high-level functions storehouse.
Step 405 is carried out the ordinary instruction after transforming, and result is sent to the data space of virtual 8051 processors, and returns step 402, and the XA2 processor continues to read next bar instruction of virtual 8051 processors.
The implementation of this step can be same as the prior art, and the ordinary instruction after the conversion can be many XA2 instructions; When the instruction of the XA2 processor after the instruction according to virtual 8051 processors transforms is many, can be after carrying out each bar instruction, result is stored in the data space of XA2 processor, when carrying out next bar instruction, from the data space of XA2 processor, read the result of a last instruction again.
In the present embodiment, the data space of virtual 8051 processors can be RAM, also can be the E that is assigned to
2The higher memory space of PROM.
Resources allocation in the present embodiment also can be carried out according to other modes.
In the instruction executing method of present embodiment, also can be in the conversion process of step 402, judge the whether external call instruction of corresponding father's hardware of the director data read, determination methods is: earlier the director data that reads is transformed, if director data can transform according to the instruction rule of virtual hardware in the prior art, then conversion results is an ordinary instruction, and execution in step 405; If the director data that reads can't transform according to the instruction rule of virtual hardware in the prior art, then from external call command mappings table, search this director data, if find this director data, then the instruction that obtains according to mapping relations is the external call instruction, and execution in step 404, if do not comprise this director data in the mapping table, then father's hardware instruction of this director data correspondence is a disable instruction, and process ends.
Based on the instruction executing method of virtual hardware system, also be applicable to other in the present embodiment, for example based on the virtual hardware system of ARM based on other physical hardwares; Method in the present embodiment is applicable to that also virtual hardware is the virtual hardware system of other processors, for example AVR, XA2 etc.
The above is preferred embodiment of the present utility model only, is not to be used to limit protection domain of the present utility model.All within spirit of the present utility model and principle, any modification of being done, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (9)
1, a kind of virtual hardware system is characterized in that, comprising: father's hardware and virtual hardware, wherein,
Father's hardware links to each other with virtual hardware, virtual hardware output order data, and father's hardware receives director data; Father's hardware output order operation result, virtual hardware receives the instruction operation result.
2, the system as claimed in claim 1 is characterized in that, described father's hardware comprises: main control unit and resource transfer unit, wherein,
Main control unit links to each other with the resource transfer unit, resource transfer unit output internal resource, and main control unit receives internal resource.
3, system as claimed in claim 2 is characterized in that, father's hardware comprises that further the master uses the location of instruction, wherein
Main control unit links to each other with the location of instruction with main, the instruction of master control location of instruction output father hardware, and main control unit receives the instruction of father's hardware;
Main control unit links to each other with virtual hardware, the director data of virtual hardware output virtual hardware and the computing variable of director data correspondence.
As claim 2 or 3 described systems, it is characterized in that 4, main control unit links to each other with described virtual hardware, described main control unit output operation result, described virtual hardware receives operation result.
5, system as claimed in claim 4 is characterized in that, described virtual hardware comprises: fictitious order storage unit and virtual data storage unit, wherein,
The fictitious order storage unit links to each other with described main control unit, fictitious order storage unit output order data, and described master receives director data with the location of instruction;
The virtual data storage unit links to each other with described main control unit, described main control unit output operation result, and described virtual data storage unit receives operation result, described virtual data storage unit output computing variable, described main control unit receives the computing variable.
As claim 2 or 3 described systems, it is characterized in that 6, described father's hardware further comprises: the master uses data storage cell, wherein,
The main data storage cell of using links to each other with described main control unit, and described main control unit output computing intermediate value is main with data storage cell reception computing intermediate value; Main with data storage cell output computing intermediate value, described main control unit receives the computing intermediate value.
7, system as claimed in claim 6 is characterized in that, described main control unit is electrically-erasable ROM (read-only memory) E
2PROM or random access memory ram;
Described master is a read only memory ROM with the location of instruction;
Described master is RAM with data storage cell;
Described resource transfer unit is E
2PROM.
8, system as claimed in claim 5 is characterized in that, described fictitious order storage unit is E
2PROM;
Described virtual data storage unit is RAM.
9, the system as claimed in claim 1 is characterized in that, described father's hardware is the XA2 processor, and described virtual hardware is 8051 processors.
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| CN 200620136595 CN200953143Y (en) | 2006-09-30 | 2006-09-30 | Virtual hardware system |
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| CN 200620136595 CN200953143Y (en) | 2006-09-30 | 2006-09-30 | Virtual hardware system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11350993B2 (en) | 2006-08-24 | 2022-06-07 | Pipstek, Llc | Dental and medical treatments and procedures |
| US11701202B2 (en) | 2013-06-26 | 2023-07-18 | Sonendo, Inc. | Apparatus and methods for filling teeth and root canals |
| USD997355S1 (en) | 2020-10-07 | 2023-08-29 | Sonendo, Inc. | Dental treatment instrument |
| US11918432B2 (en) | 2006-04-20 | 2024-03-05 | Sonendo, Inc. | Apparatus and methods for treating root canals of teeth |
-
2006
- 2006-09-30 CN CN 200620136595 patent/CN200953143Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11918432B2 (en) | 2006-04-20 | 2024-03-05 | Sonendo, Inc. | Apparatus and methods for treating root canals of teeth |
| US11350993B2 (en) | 2006-08-24 | 2022-06-07 | Pipstek, Llc | Dental and medical treatments and procedures |
| US11426239B2 (en) | 2006-08-24 | 2022-08-30 | Pipstek, Llc | Dental and medical treatments and procedures |
| US11684421B2 (en) | 2006-08-24 | 2023-06-27 | Pipstek, Llc | Dental and medical treatments and procedures |
| US11701202B2 (en) | 2013-06-26 | 2023-07-18 | Sonendo, Inc. | Apparatus and methods for filling teeth and root canals |
| USD997355S1 (en) | 2020-10-07 | 2023-08-29 | Sonendo, Inc. | Dental treatment instrument |
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