CN2611989Y

CN2611989Y - Intelligence card chip with self testing microprocessor

Info

Publication number: CN2611989Y
Application number: CN 03230078
Authority: CN
Inventors: 印义中; 印义言; 郭俊; 黄激; 卢君明
Original assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Current assignee: HUAYUAN MICRO ELECTRONIC TECHNOLOGY Co Ltd SHANGHAI
Priority date: 2003-04-04
Filing date: 2003-04-04
Publication date: 2004-04-14
Anticipated expiration: 2013-04-04

Abstract

An intelligent card chip with self-test, provided with a microprocessor comprises a main circuit and a self-test circuit bidirectional connected with the main circuit to completely test the main circuit. The self-test circuit comprises a test model input, a multi-path switch for judging normal working data input or test data input, a test image generator controlled by an input test command a test mode, and a character analyzer for analyzing and outputting test result and the accident type, wherein the test image generator generates test data to each module of the main circuit to respectively test the integral function of each module. Therefore, user can avoid connecting external test device to test and check the intelligent card chip, thereby reducing test cost and test time.

Description

Intelligent card chip with microprocessor capable of making automatic test

Technical field

The utility model relates to a kind of intelligent card chip with microprocessor, relates in particular to a kind of intelligent card chip that carries out the band microprocessor of self-test.

Background technology

The smart card that has integrated circuit is promoted rapidly and development in the national economy every field.The smart card that has CPU is a topmost class in the smart card.It is widely used in every field such as finance, communication, social security, traffic, paying, Identity Management.

Because the singularity of application of IC cards has extra high requirement to security and reliability, if will not cause very big harm because the defective chip of each side factors such as design, manufacturing, technology generation is detected to enter in user's hand.Therefore the intelligent card chip for band CPU must all carry out comprehensively detailed test to each sheet chip.

The intelligent card chip inside that has CPU has comprised CPU, large capacity data memory EEPROM, random access memory ram.The program memory ROM that is used for the deposit operation system is used for the cryptographic coprocessor of encryption and decryption computing and the modules such as 7816 serial ports of external communication and has formed a complete system in a chip.

The basic point of Test Design is controllability and observability, and controllability is meant can both carry out the set and the control that resets to each node of circuit inside, and observability is directly or indirectly to observe the state of any node in the circuit.

The method of testing of the intelligent card chip of band CPU is seen Fig. 1 at present, produce test vector by external test facility, externally test mode signal control is sent into test vector in the chip main circuit by the ISO7816 serial port down one by one, test result is exported by the ISO7816 serial port, by testing apparatus test result is analyzed, judged whether the every function of chip, performance adhere to specification.

Because the smart card of band CPU has been formed the holonomic system that comprises operating system software in a chip, integrated level and system complexity are along with the increase system complexity and the integrated level of demands such as ecommerce are more and more higher, again because also rising day by day of the requirement of smart card aspect the security reliability of band CPU, must carry out full test to CPU, ROM, RAM, cryptographic coprocessor, eeprom memory, especially must adopt different pieces of information to carry out reading and writing, wipe and the test of data maintenance aspect repeatedly to each storage unit eeprom memory.Testing apparatus price height, the test duration is long.Make the production cost raising and influence delivery date.The market demand requires that a kind of reduction testing cost can be arranged, and reduces the method for test duration.

Summary of the invention

Technical problem to be solved in the utility model is to have increased the built-in self-test circuit in the intelligent card chip of band CPU, makes the user needn't connect external test facility basically, just can carry out the test and the checking of this intelligent card chip.

In order to solve the problems of the technologies described above, the utility model has adopted following technical proposals: in having the intelligent card chip of CPU, increased built-in and with the two-way self testing circuit that is connected of this main circuit, this self testing circuit can carry out full test to main circuit.Described self testing circuit comprises:

A multi-way switch of the operate as normal data or the test command of input being sent into main circuit according to the state of external testing mode signal; The pattern generator that can produce test data according to the test command control that multi-way switch comes; The feature analyzer that can compress and test result is analyzed and exported test result;

The self-test and outputing test result voluntarily of this intelligent card chip, differentiate whether qualified and fault type of chip, the user needn't connect external test facility basically, just can carry out the test and the checking of this intelligent card chip, thereby the reduction testing cost reduces the test duration.

Description of drawings

Fig. 1 is conventionally test circuit theory diagrams of being with the intelligent card chip of CPU at present.

But Fig. 2 is the circuit theory diagrams of smart card of the band microprocessor of self-test of the present utility model.

Fig. 3 is the circuit theory diagrams of multi-way switch shown in Figure 2.

Fig. 4 is the circuit theory diagrams of pattern generator TPG shown in Figure 2.

Fig. 5 is the circuit theory diagrams of feature analyzer SA shown in Figure 2.

Embodiment

As shown in Figure 2: an intelligent card chip with microprocessor capable of making automatic test that provides in the present embodiment, be provided with self testing circuit in it, this self testing circuit can be to the main circuit in the intelligent card chip 1, be that CPU11, ROM12, RAM13, EEPROM14, cryptographic algorithm coprocessor 15 carry out full test, this self testing circuit comprises that one will be sent into the multi-way switch 3 of main circuit 1 from the operate as normal data or the test command of input serial ports 2 inputs according to the state of external testing mode signal.4, one of the pattern generators (TPG) that basis produces test data by the test instruction control of multi-way switch 3 compress test result data and test result are analyzed and with the feature analyzer (SA) 5 of test result from 6 outputs of output serial ports.Import serial ports 2 in the present embodiment and output serial ports 6 is 7816 or the USB serial ports.

As shown in Figure 3: described multi-way switch 3 comprises: forms by input and not sum phase inverter, will be according to the condition judgement of outside input testing mode by the operate as normal data of input serial ports 2 or Sheffer stroke gate ND1 and the Sheffer stroke gate ND2 that test command is delivered to main circuit 1 or pattern generator 4 respectively, and control and test pattern is controlled No. 8 register reg0-reg7 that 8 road concurrent testing data of pattern generator 4 delivered to main circuit by band clock (CLK).

As shown in Figure 3, when chip was tested, the external testing mode signal was in test mode (test pattern port input high level), and this signal is opened Sheffer stroke gate ND2, and Sheffer stroke gate ND1 closes., enter chip through ISO7816 or USB serial ports 2 and deliver to pattern generator 4 by data input pin IN input from the chip exterior test command through Sheffer stroke gate ND2.It is erasable that test command can be divided into eeprom memory, cpu instruction test, ROM, the test of RAM and cryptographic coprocessor.Needs according to test are imported the corresponding command from the outside.

When external testing mode port input low level, be in normal operating conditions, this signal is closed Sheffer stroke gate ND2, Sheffer stroke gate ND1 opens, and the normal service data of chip exterior enters chip through ISO7816 or USB serial ports and delivers to main circuit through Sheffer stroke gate ND1, and chip enters normal operating condition.When no signal on the external testing pattern end was imported, because the effect Sheffer stroke gate ND1 of pull down resistor R1 opens, Sheffer stroke gate ND2 closes chip also can only work in normal operating condition.

Under test pattern, the test data D (7:0) that comes from pattern generator TPG delivers to register Reg0 ~ Reg7 the multi-way switch MUX as shown in Figure 3, register Reg0 ~ Reg7 tested person mode signal and synchronous clock CLK control.Test data is delivered to main circuit among register Reg0 ~ Reg7, for the chip self-test.

Described pattern generator 4 is seen Fig. 4, and these pattern generator 4 inside comprise the test logic circuit 41 and the ROM ROM (read-only memory) 42 of two-way connection.The test instruction that this pattern generator 4 receives by multi-way switch 3.Send control signal to CPU11, receive the address date that CPU11 comes, and, deliver to tested EEPROM14, RAM13, ROM12 and CPU11 respectively the test data of ROM ROM (read-only memory) 42.And the correct result that will test delivers to and carries out test result in the feature analyzer 5 relatively.

As shown in Figure 4, test instruction is delivered in the test logic circuit 41 of surveying diagrammatic sketch shape generator 4 through multi-way switch during chip testing, this test logic circuit 41 is sent into ROM ROM (read-only memory) 42 from the address that CPU11 gets resolution chart, ROM ROM (read-only memory) 42 with the resolution chart data after tested logic deliver to main circuit 1 and test.Simultaneously test logic circuit 41 obtains the correct data of test result from ROM ROM (read-only memory) 42, and correct test result data is delivered to feature analyzer 5 and test result compares.Because the test result data amount is very big, for saving the self-test time, in test logic circuit 41, adopt the correct data of 411 pairs of test results of CRC circuit to compress, obtain the condition code of former data sequence and deliver to feature analyzer 5 again.

Described feature analyzer SA sees Fig. 5, and this feature analyzer 5 comprises: one is compressed the CRC circuit 51 of the condition code of obtaining former data sequence, test result data register 52, correct data register 53, a data comparer 54 with test result data.

Under test mode signal control, deliver to main circuit when test data as seen from Figure 5, by the main circuit data that output test result by multi-way switch MUX.This result data is delivered to feature analyzer 5, is compressed by 51 pairs of test result data of CRC circuit in the feature analyzer 5, obtains the condition code of former data sequence, delivers to test result data register 52.The correct data register 53 of being delivered to feature analyzer 5 by the test result correct data condition code after compression of pattern generator 4 compares the value in test result data register 52 and the correct data register 53 in data comparator 54, then can obtain test result, whether the reflection chip can pass through this test.This test result is sent CPU from data bus, and CPU provides the test result of different test-types according to the kind of the judgement of test result and test command, and test result is through ISO7816 or the output of USB serial port.

Claims

1, a kind of intelligent card chip with microprocessor capable of making automatic test comprises main circuit (1), it is characterized in that, also is provided with and the two-way self testing circuit that is connected of this main circuit (1), and this self testing circuit can carry out full test to main circuit (1).

2, intelligent card chip with microprocessor capable of making automatic test according to claim 1 is characterized in that, described self testing circuit comprises:

A multi-way switch (3) of the operate as normal data or the test command of input being sent into main circuit according to the state of external testing mode signal;

The pattern generator (4) that can produce test data according to the test command control that multi-way switch (3) comes;

The feature analyzer (5) that can compress and test result is analyzed and exported test result;

3, intelligent card chip with microprocessor capable of making automatic test according to claim 2 is characterized in that, described self testing circuit also comprises:

One can input to operate as normal data or test command the input serial ports (2) of multi-way switch (3);

One can be with the output serial ports (6) of the output of the test result after analyzing;

4, intelligent card chip with microprocessor capable of making automatic test according to claim 3 is characterized in that, described input serial ports (2) and output serial ports (6) are ISO7816 or USB serial ports.

5, according to claim 2 or 3 described intelligent card chip with microprocessor capable of making automatic tests, it is characterized in that, described multi-way switch (3) comprises a Sheffer stroke gate (ND1) that is connected with main circuit (1) and a Sheffer stroke gate (ND2) that is connected with pattern generator (4), when test pattern port input high level, Sheffer stroke gate (ND1) is closed, Sheffer stroke gate (ND2) is opened, when test pattern port input low level, Sheffer stroke gate (ND1) is opened, Sheffer stroke gate (ND2) is closed, when test pattern port no signal was imported, Sheffer stroke gate (ND1) was opened, and Sheffer stroke gate (ND2) is closed.

6, intelligent card chip with microprocessor capable of making automatic test according to claim 5, it is characterized in that, described multi-way switch (3) comprises that also one can receive the register (reg0-reg7) from the test data of pattern generator (4), and this register can be delivered to test data main circuit (1).

7, intelligent card chip with microprocessor capable of making automatic test according to claim 2, it is characterized in that, described pattern generator (4) comprises the test logic circuit (41) and the ROM ROM (read-only memory) (42) of two-way connection, described test logic circuit (41) receives the test instruction from multi-way switch 3, and ROM ROM (read-only memory) (42) is sent in the address of obtaining resolution chart from main circuit, described ROM ROM (read-only memory) (42) with the resolution chart data after tested logic deliver to main circuit (1) and test, simultaneously test logic circuit (41) obtains the correct data of test result from ROM ROM (read-only memory) (42), and correct test result data is delivered to feature analyzer (5) and test result compares.

8, intelligent card chip with microprocessor capable of making automatic test according to claim 7, it is characterized in that, described test logic circuit (41) comprises that one can compress the correct data of test result, obtains the CRC circuit (411) of the condition code of former data sequence.

9, intelligent card chip with microprocessor capable of making automatic test according to claim 2, it is characterized in that described feature analyzer (5) comprising: a CRC circuit (51) that test result data is compressed the condition code of obtaining former data sequence, a test result data register (52) that receives above-mentioned condition code, reception is from the correct data register (53) of the correct data of the CRC circuit (411) in the test logic circuit (41), the data comparator (54) that value in test result data register (52) and the correct data register (53) is compared.

10, the intelligent card chip of the band microprocessor of the mode of testing oneself according to claim 1 is characterized in that, described main circuit (1) comprises CPU (11), ROM (12), RAM (13), EEPROM (14), cryptographic algorithm coprocessor (15).