CN2578894Y

CN2578894Y - Monitor of computer principle demonstrator

Info

Publication number: CN2578894Y
Application number: CN 02267134
Authority: CN
Inventors: 严义
Original assignee: HANGZHOU YIYI AUTOMATION CO Ltd
Current assignee: HANGZHOU YIYI AUTOMATION CO Ltd
Priority date: 2002-09-11
Filing date: 2002-09-11
Publication date: 2003-10-08
Anticipated expiration: 2012-09-11

Abstract

The utility model discloses a monitor of computer principle demonstrator. The monitor is connected with individual functional units of the demonstrator. The data of the monitor is transmitted in unidirectional mode. The functional unit comprises a clock unit, an input and output unit, a register unit, an arithmetic unit, an instruction decoding unit, an interrupt location, an address unit and a bus unit. The monitor monitors all signals of above units only and dose not control the signals. A main control unit and a memory unit whose systems are provided with memory devices are connected with the monitor. The data is transmitted in two-way mode. The memory device can be read and written by the monitor and the monitor can conduct data monitoring. The comparison of control signal output and input can be realized by the monitoring for the main control unit and the functional modules. The monitor of computer principle demonstrator is provided with a strong capability of error correcting. The signal received by individual functional units does not have sub-process. Thus, the diaphaneity of student's experiment is high.

Description

A kind of monitoring device of Experiment Instrument of Computer Composition Principle

Technical field

The utility model relates to a kind of monitoring device of Experiment Instrument of Computer Composition Principle, belongs to the computer-experiment instrument field.

Background technology

The monitoring device of existing Experiment Instrument of Computer Composition Principle, they mainly are divided into two kinds of frame modes.First kind is to be linked to each other with each unit of theory of constitution (as: arithmetical unit unit, logic decoding unit, register cell, address location etc.) respectively as control module by single-chip microcomputer.Control module control of forming by single-chip microcomputer and gating and the read signal that switches each unit reach control and monitor the purpose of each unit.The gating signal that main control unit in the theory of constitution experiment instrument of this mode (micro controller unit) sends is not directly to each element circuit, but deliver to the Single-chip Controlling unit earlier, output to each element circuit by the Single-chip Controlling unit again, the student does not detect each gating signal when doing experiment, the transparency of experiment is not enough, this in addition frame mode monitoring is less than each unit all control control signal and data, and monitoring function is not enough, maintenance is inconvenient.Second kind is theory of constitution various piece composition model computer system, directly carries out communication with host computer and the state of each unit of theory of constitution is provided.This mode is because a little less than the normatron function of theory of constitution experiment instrument composition 7, the ability of monitoring is more weak.

Summary of the invention

The purpose of this utility model is to overcome above-mentioned supervising device to make experiment instrument transparency difference and the weak shortcoming of monitoring capacity, a kind of not monitoring device of the Experiment Instrument of Computer Composition Principle of interference experiment instrument control signal that has is provided, realizes the false wiring measuring ability by the output input signal that monitoring device reads on all experiment instruments.

The utility model is a kind of monitoring device of Experiment Instrument of Computer Composition Principle, comprising:

1) functional unit of this monitoring device and experiment instrument is connected by lead, the data one-way transmission, functional unit comprises clock unit, input-output unit, register cell, the arithmetical unit unit, instruction decoding unit, interrupt location, address location, bus unit, the signal wire of clock unit, input-output unit, signal wire, the signal wire of register cell, the signal wire of arithmetical unit unit, the signal wire of instruction decoding unit, the signal wire of interrupt location, the signal wire of address location, the data signal line of bus unit links to each other with the monitoring device corresponding port respectively;

2) and the unit of system's tape storage spare: main control unit, memory cell are connected with monitoring device, the data double-way transmission, the signal wire of main control unit links to each other with the monitoring device corresponding port respectively, and the signal wire of memory cell links to each other with the monitoring device corresponding port respectively.

Above-mentioned data one-way transmission is meant that monitoring device receives only the signal that input-output unit, register cell, arithmetical unit unit, instruction decoding unit, interrupt location, address location, bus unit are sent here; Clock unit receives only the single step clock signal that monitoring device is sent here.

Above-mentioned data double-way transmission is meant main control unit and the memory cell for system's tape storage spare, and monitoring device switches the flow direction of the signal of main control unit and memory cell by digital two-way switch.

The output data of main control unit is delivered to the output termination by decoding scheme, and monitoring device receives the reception data of main control unit output data and each functional unit, by two groups of data of comparison, and the wiring of can correcting a mistake, monitoring capability is strong.

Monitoring device is controlled it during only to the main control unit of tape storage spare, memory cell read-write.The gating signal that monitoring device does not interfere each unit to receive, there is not pilot process in the signal that each functional unit receives, and the student can measure each gating signal when doing experiment really, and the transparency is strong.

Description of drawings

Fig. 1 is the general structure schematic diagram;

Fig. 2 is the line graph of monitoring device and each functional part;

Fig. 3 is the monitoring device circuit theory diagrams;

Fig. 4 is a monitoring device and being connected of memory cell;

Fig. 5 is a monitoring device and being connected of main control unit;

Fig. 6 is the principle detail drawing of Fig. 3.

Embodiment

As Fig. 1, Fig. 2, shown in Figure 6, this structure detailed content is as follows:

1) functional unit of this monitoring device 1 and experiment instrument is connected by lead, the data one-way transmission, functional unit comprises clock unit 2, input-output unit 3, register cell 4, arithmetical unit unit 5, instruction decoding unit 7, interrupt location 8, address location 9, bus unit 10, the CPU-STEP signal wire of clock unit 2, the I/O-R of input-output unit 3, the I/O-W signal wire, the B-R3 of register cell 4, B-R2, B-R1, B-R0, R3-B, R2-B, R1-B, the R0-B signal wire, the S3 of arithmetical unit unit 5, S2, S1, S0, M, Ci, B-DA1, B-DA2, ALU-B, 299-B, FC, the FZ signal wire, the B-IR of instruction decoding unit 7, J1, J2, J3, J4, the J5 signal wire, the INT-R signal wire of interrupt location 8, the B-PC of address location 9, PC+1, PC-B, the B-AR signal wire, the D0-D7 data signal line of bus unit 10 links to each other with monitoring device 1 corresponding port respectively;

2) unit of system's tape storage spare: main control unit 6, memory cell 11 are connected with monitoring device 1, the data double-way transmission, the MA0-MA6 of main control unit 6, MD0-MD2 signal wire link to each other with monitoring device 1 corresponding port respectively, and the RA0-RA7 of memory cell 11, RD0-RD7 signal wire link to each other with monitoring device 1 corresponding port respectively.

From figure shown in Figure 1 as can be seen monitoring device only monitor the gating signal of each functional unit, do not interfere the gating signal of each functional unit.Each functional unit is formed a normatron.Its workflow is: clock unit 2 sends work clock for main control unit 6, the work of driving Main Control Unit, master controller takes out corresponding data according to the microcode address, these data are sent control signal by a fixing decoding, and other functional unit receives control signal and carries out corresponding work.This workflow is similar to the workflow of common computer CPU.

From Fig. 2 (in conjunction with Fig. 1), the concrete signal of each functional unit in the monitoring device monitoring model computing machine as can be seen.

Main control unit 1, the signal that it delivers to monitoring device 1 is MA, MD.Wherein MA (7BIT) is the microcode address that will carry out, and MD (24 BIT) is the microcode data.MD produces one group of gating signal of issuing other each functional unit through decoding.And CPU-W, CPU-R delivers to the read-write of main control unit 6 when being monitoring device 1 read-write microcode.

Arithmetic element 5, the signal that it delivers to monitoring device 1 is S3, S2, S1, S0, M, Ci, B-DAl, B-DA2, ALU-B, 299-B, FC, FZ.It comprises arithmetical unit and shift unit, arithmetical unit is that DA1 and DA2 are added, subtract, take advantage of, remove and wait arithmetic or logical operation, specifically S3, the S2, S1, S0, M, the Ci that are sent by main control unit 6 of the computing of carrying out decides, and B-DAl and B-DA2 are that to send bus data be that result with arithmetical unit passes out to bus unit 10 to DA1 and DA2, ALU-B; Shift unit carries out shifting function to the data in the shift unit, and concrete action is that data with shift unit pass out to bus unit (10) by S1, S0 and 299-B decision 299-B.FC, FZ are the states of computing.

Register cell 4, the signal that it delivers to monitoring device 1 is B-R3, B-R2, B-R1, B-R0, R3-B, R2-B, R1-B, R0-B; Wherein B-R3, B-R2, B-R1, B-R0 signal are that the data in the register are sent into from bus, and R3-B, R2-B, R1-B, R0-B signal are that the data in the register are passed out to bus unit 10.

Instruction decoding unit 7, the signal that it delivers to monitoring device 1 is B-IR, J1, J2, J3, J4, J5.Wherein B-IR delivers to bus data in the order register of this unit, and J1-J5 is the rotaring signal that looses.

Input-output unit 3, the signal that it delivers to monitoring device 1 is I/O-R, I/O-W.Wherein I/O-R delivers to bus unit 10 with the data of INPUT, and the I/O-W signal is delivered to OUTPUT with the data of bus unit 10.

Interrupt location (8), the signal that it delivers to monitoring device 1 is INT-R.Wherein the INT-R signal is that interrupt vector is sent into bus unit 10.

Address location 9, the signal that it delivers to monitoring device 1 is B-PC, PC+1, PC-B, B-AR.Wherein B-PC and PC+1 send the data of bus unit 10 into program counter, and single PC+1 is that program counter adds 1 certainly, and PC-B delivers to bus unit 10 with the data of program counter.B-AR delivers to the data of bus unit 10 in the address register.

Memory cell 11, the logic data signal that it delivers to monitoring device 1 is CPU-R1, CPU-W1.Wherein M-R is the memory read signal, and M-W is a memory write signals.RA0-RA7 and RD0-RD7 deliver to when being monitoring device 1 read/write memory memory cell address and data.

Bus unit 10, the data that it delivers to monitoring device 1 are the data D0-D7 (8) on the bus.

Fig. 3 is the circuit diagram of monitoring means, and it is made up of a slice 89c51 and 4 8255, and above-mentioned all signals are connected (details drawing is seen Fig. 6) by 8255 with 89c51.

To operate be in order to realize the read-write to memory cell to 1 pair of memory cell 11 of monitoring device among Fig. 4.When CPU-M is effective, the address of storer and data are provided by monitoring device 1, read-write M-R, the M-W of memory cell 11 provided by the CPU-R1 and the CPU-W1 of monitoring device, and the M-R of data line that address wire that address location 9 is even come and bus unit are even come and main control unit, M-W signal wire and memory cell 11 are isolated; When CUP-M is invalid, the data signal line of switch left end and memory cell conducting, monitoring device 1 connects the signal wire of coming and is isolated.

2816 is memory devices of depositing microcode in the main control unit among Fig. 5, and the control of 1 pair of main control unit of monitoring device is in order to realize the read-write to 2816.2816 read-write was provided by monitoring device 1 when CPU-CS was effective, and data and address are also provided by monitoring device 1, and the data signal line of switch left end and 2816 is isolated; When CPU-CS is invalid, the data signal line of left end and 2816 conductings, the CPU-R of monitoring device 1, CPU-W is isolated, the MA0-MA6 of monitoring device 1, the address end of MD0-MD23 end one-way transmission 2816 and the data-signal of data terminal are to monitoring device 1.

Claims

1. the monitoring device of an Experiment Instrument of Computer Composition Principle is characterized in that comprising:

1) functional unit of this monitoring device (1) and experiment instrument is connected by lead, the data one-way transmission, functional unit comprises clock unit (2), input-output unit (3), register cell (4), arithmetical unit unit (5), instruction decoding unit (7), interrupt location (8), address location (9), bus unit (10), the CPU-STEP signal wire of clock unit (2), (the I/O-R of input-output unit (3), I/O-W) signal wire, (the B-R3 of register cell (4), B-R2, B-R1, B-R0, R3-B, R2-B, R1-B, R0-B) signal wire, (the S3 of arithmetical unit unit (5), S2, S1, S0, M, Ci, B-DA1, B-DA2, ALU-B, 299-B, FC, FZ) signal wire, (the B-IR of instruction decoding unit (7), J1, J2, J3, J4, J5) signal wire, (INT-R) signal wire of interrupt location (8), (the B-PC of address location (9), PC+1, PC-B, B-AR) signal wire, (D0-D7) data signal line of bus unit (10) links to each other with monitoring device (1) corresponding port;

2) unit of system's tape storage spare: main control unit (6), memory cell (11) are connected with monitoring device (1), the data double-way transmission, (MA0-MA6, MD0-MD23) signal wire of main control unit (6) links to each other with monitoring device (1) corresponding port respectively, and (RA0-RA7, RD0-RD7) signal wire of memory cell (11) links to each other with monitoring device (1) corresponding port respectively.

2. the monitoring device of Experiment Instrument of Computer Composition Principle according to claim 1 is characterized in that described data one-way transmission is meant that monitoring device (1) receives only the signal that input-output unit (3), register cell (4), arithmetical unit unit (5), instruction decoding unit (7), interrupt location (8), address location (9), bus unit (10) are sent here; Clock unit (2) receives only the single step clock signal that monitoring device is sent here.

3. the monitoring device of Experiment Instrument of Computer Composition Principle according to claim 2, it is characterized in that described data double-way transmission is meant main control unit (6) and the memory cell (11) for system's tape storage spare, monitoring device (1) switches the flow direction of the signal of main control unit (6) and memory cell (11) by digital two-way switch.

4. the monitoring device of Experiment Instrument of Computer Composition Principle according to claim 3, the output data that it is characterized in that main control unit (6) is delivered to the output termination by decoding scheme, monitoring device (1) receives the reception data of main control unit output data and each functional unit, can error correction by comparing.